coreboot January 2014

coreboot@coreboot.org

54 participants
116 discussions

Re: [coreboot] coreboot engineer needed
by Scott Duplichan 09 Jan '14

09 Jan '14

David Hubbard [mailto:david.c.hubbard+coreboot@gmail.com] wrote: ]Hi Scott, ]Without additional information about the following questions, ]the job offer misses some candidates. Still, in this economy, ]kudos for the offer. I have never worked for Intel so I can only guess about the job details. I suspect the creation of this position is a consequence of coreboot now being the fastest growing boot firmware used in the PC market: http://www.theregister.co.uk/2013/07/11/chromebooks_fastest_growing_pc_mark… The listing's incorrect capitalization of coreboot shows that coreboot is a new thing to Intel managers. Intel has been pushing for UEFI as the standard x86 boot firmware since 1999, so the recent success of coreboot (through chromebook) has probably taken some Intel managers by surprise. ]1. What does "coreboot engineer" mean? An engineer who has ]experience with coreboot -- or an engineer who will be working ]openly, supporting the coreboot project, and contributing ]patches, source code, and documentation? I can only guess about the job details. These job descriptions often contain lots of cut and paste, and little proofreading. At least this one lists "Demonstrated C coding skills". The nearly universal use of "C/C++" in job advertisements is annoying (in my opinion, C and C++ are quite different languages). It is also odd to see a requirement for 5 years of UEFI or coreboot experience. Probably some of both would be better, given that the reference code must be packaged for both UEFI and coreboot use. ]2. What legally binding signatures does the position require? ]For example, Intel has a standard NDA as well as several Trade ]Secret documents; please include an exhaustive list and highlight ]the agreements that will have a material affect on the engineer's ]efforts to improve http://www.coreboot.org/Binary_situation either ]during their free time after hours, or after they no longer work ]for Intel. ]3. Will the position require the engineer to intermittently work ]with Microsoft products, outside of compatibility tests? Will the ]position require the engineer to work on open source projects that ]are incompatible with the GPLv3, specifically the non-Tivoization ]clause? Will the position require the engineer to support UEFI ]Secure Boot? I can't answer for Intel, but I really doubt any Microsoft OS boot work is involved. The only Windows logo approved boot method is UEFI. Intel already has a UEFI BIOS team to handle that. Same for secure boot. I would be willing to bet that Intel wants pure (UEFI free) coreboot here. Microsoft is the only company that wants 'secure boot'. Google has their own security mechanisms that seem to be getting the job done. Microsoft has UEFI. Thanks, Scott ]If you are not at liberty to discuss these kinds of details, it's fine. ] ]David ] ]On Thu, Jan 9, 2014 at 7:37 AM, Scott Duplichan <scott(a)notabs.org> wrote: ] ]https://intel.taleo.net/careersection/10000/jobdetail.ftl?job=725464 ] ]Thanks, ]Scott

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Re: [coreboot] [RFC] MMC support in coreboot
by mrnuke 09 Jan '14

09 Jan '14

On 01/09/2014 12:26 PM, ron minnich wrote: > The other suggestion: take your time, and let's evolve this by looking > at code. Think about the interface first. Start a Google doc and we > can pitch in. That's how a lot of early linuxbios was done, via > emphasizing discussion of the API before we wrote code. > I've jotted down some ideas here: http://www.coreboot.org/User_talk:MrNuke Let's see if we can build on that. Anyone with better ideas, feel free to edit that page. Ale

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Re: [coreboot] [RFC] MMC support in coreboot
by ron minnich 09 Jan '14

09 Jan '14

The other suggestion: take your time, and let's evolve this by looking at code. Think about the interface first. Start a Google doc and we can pitch in. That's how a lot of early linuxbios was done, via emphasizing discussion of the API before we wrote code. ron

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Re: [coreboot] blob matrix
by Patrick Georgi 08 Jan '14

08 Jan '14

Am 08.01.2014 06:16, schrieb ron minnich: > As an experiment I've started a page linked from the top I'm calling > the Blob Matrix. It's partly because the discussion got a little > confusing for me about blobs, and partly because it's not always > clear, moving from one system to another, that you're really reducing > your blob count. I'm a bit confused on the scope of that page. I don't know for sure if the X60 comes with Intel AMT firmware or not, but I've never seen a Management Engine on i945/ICH7. Also, what's the "BIOS" bit supposed to mean? ACPI and SMM aren't exactly blobs, at least not more than all vendor BIOS bits. On coreboot they're neatly contained. The ME blob on Pixel is mentioned "replacable, signed", which is physically true, but still meaningless because of the "signed" bit. On the other hand MRC is "not practically replaceable" even though "all" it takes is reverse engineering similar to the effort for the nehalem support for x201. As far as I can see, there are four different aspects intermingled right now: 1. What is shipping by default (eg. BIOS, ACPI, SMM) 2. Where might nastygrams hide on your device (eg. ACPI, SMM) 3. What can be replaced physically (ME firmware, but not BL0) 4. What can be replaced logically (MRC and VGA BIOS can, with tons of effort, ME firmware can't) Which one are you aiming for? Regards, Patrick

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Re: [coreboot] blob matrix
by mrnuke 08 Jan '14

08 Jan '14

On 01/07/2014 11:16 PM, ron minnich wrote: > As an experiment I've started a page linked from the top I'm calling > the Blob Matrix. It's partly because the discussion got a little > confusing for me about blobs, and partly because it's not always > clear, moving from one system to another, that you're really reducing > your blob count. > Oh! Almost forgot. A source of inspiration: http://www.coreboot.org/Binary_situation

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Re: [coreboot] blob matrix
by mrnuke 08 Jan '14

08 Jan '14

On 01/07/2014 11:16 PM, ron minnich wrote: > As an experiment I've started a page linked from the top I'm calling > the Blob Matrix. It's partly because the discussion got a little > confusing for me about blobs, and partly because it's not always > clear, moving from one system to another, that you're really reducing > your blob count. > > I don't know how to do a matrix on the mediawiki, but I'm interested > in comments and improvements. > You can use tables. Just copy the table structure from any other page and fill in your details.

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blob matrix
by ron minnich 08 Jan '14

08 Jan '14

As an experiment I've started a page linked from the top I'm calling the Blob Matrix. It's partly because the discussion got a little confusing for me about blobs, and partly because it's not always clear, moving from one system to another, that you're really reducing your blob count. I don't know how to do a matrix on the mediawiki, but I'm interested in comments and improvements. thanks ron

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Remove GENERATE_ACPI_TABLES
by Vladimir 'φ-coder/phcoder' Serbinenko 07 Jan '14

07 Jan '14

By now most boards and OS don't run correctly if ACPI tables are not supplied. Ability by user to enable/disable their generation is just increasing configuration matrix for no benefit. So I propose to hardwire it to HAVE_ACPI_TABLES. I feel like in current config there are too many options of kind "Do you want a working system? (y/n)" and they should be hardwired to right answer rather than adding configuration. http://review.coreboot.org/#/c/4609/

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does coreboot support kvm & WPCE775x & other questions
by dhan.war 06 Jan '14

06 Jan '14

hi all i am using toshiba satellite c850d-m5010. the kvm is disabled by default in BIOS. it seems to me that many laptop manufacturers does not fully support kvm. my output of the superiotool : # superiotool superiotool r6637 Found Nuvoton WPCE775x / NPCE781x (id=0x00, rev=0x01) at 0x2e i did a search on website & it points to me 2 links only [[a] & [b]]. the link [a] is silent about BIOS & CB. the link [b] is silent about datasheets & comment. the output of superiotool -V also states that dump is available. there is also a request to add WPCE775x on mailing list [c] & there seems to no answer to the thread. my questions: [1] does coreboot support kvm ? [2] can i install coreboot on Nuvoton WPCE775x / NPCE781x ? [3] does the support for Nuvoton WPCE775x / NPCE781x is added in coreboot ? [4] what does the dump available mean in output of superiotool -V ? if you need any further information please let me know. please also provide appropriate commands if it involves any packages. thank you reading the message patiently. even though i am subscribed to mailing list, please always cc me. [a] http://www.coreboot.org/Superiotool [b] http://www.coreboot.org/Embedded_controller [c] http://www.coreboot.org/pipermail/coreboot/2010-July/059274.html regards, dhan.war

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Re: [coreboot] does coreboot support kvm & WPCE775x & other questions
by Vladimir 'φ-coder/phcoder' Serbinenko 06 Jan '14

06 Jan '14

On 05.01.2014 07:15, Gregg Levine wrote: > Part of the problem with laptops is that there is a thing on them > called an Embedded Controller, EC for short. Those devices do all of > the housekeeping chores that the main system has delegated to them. > For example certain functions are on it. > > To that end most laptops aren't supported because these devices are > proprietary in their designs and the programing of them. While ECs are a problem for flashrom (unless they run off a separate flash), they are usually of marginal importance to coreboot. You cn always use external flasher.

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coreboot January 2014