coreboot August 2013

coreboot@coreboot.org

29 participants
54 discussions

Re: [coreboot] Set-top box Geode SC1201 based
by Piero 12 Aug '13

12 Aug '13

Hi Peter, thank you for your quick response :-) Peter wrote: >Good times. When I first came to coreboot some 13 years ago > I worked on a competing product based on the same Geode. Wow so you are a pro :-) > Don't confuse "freely" with free as in speech, but anyway I don't > think XpressROM was ever free. I totally agree with you, I performed a lot of searches on google and, at the end, I discover that XpressROM was not free. > If you have the right background and want to learn about these old > platforms you could probably reach a working system after a few > months of intense hacking, reverse engineering and studying. My SW/HW engineer background span from the reverse engineering on Linux and Windows X86 applications to embedded systems. But, to be honest, I never properly reverse a bios (just some quick customization, i.e. on the Kreatel bios :)), so I want to start to learn more about it. On the google there are not a lot of books or guides that treat this topic, so it is a little bit complicated for me understard where to start. > How much do you value your time? The time is never enought for me, this type of job/passion requires ton of time, two good eyes and a lot of patience :) > I somehow know the platforms and I would still recommend not to > bother, but to just buy an ASRock E350M1 mainboard, where coreboot > is known to already work. I totally agree, now the two Kreatel boards are so old and with a few of Euros is possible to buy a good new board with new interfaces! I know :-) Maybe what I'm starting to write is a little bit off-topic, but I'd like to ask you an advise or just an opinion: One of my curiosity and task (I wanted to do this with the Kreatel board, but I understand that it is a little bit complicated :)) is try to figure out how this guy was able to customize and modifiy the Ati-VgaBios: http://tinyurl.com/y47dk7 I don't know if you already know how the Arcade monitors work. Some of them have a "non-standard" Hsync freq (15kHz) and this guy was able to customize the native and built-in freq. table inside the ATI bios, as you can see at the end of this page: http://tinyurl.com/mgcqnar How can I start to understand how to do this? I tried to start to reverse with some debugger (IDA i.e.) the original Bios X550 (that you could find on the ATI website) it seems that there is not any type of freq. table. In the past, this guy, has customized and modified other Ati video bios models. Thank you another time for your help :-) Peter

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Set-top box Geode SC1201 based
by Piero 11 Aug '13

11 Aug '13

Hi all, I have in my hands two "old" set-top boxes branded as Kreatel Tornado/K5 2.0. In the link provided below you would see some board pictures (38MB, password: "CorebootLinux"): http://tinyurl.com/kh4qllr This set-top box works (or better worked) by loading remotely the Linux kernel via Ethernet. The bios inside the ST49LF020 chip (as you can see in the picture, I removed the chip and I solder a PLCC32 socket to speed-up the new bios flashing :-)) is a customize version of XpressRom. I tried to find on Google some information about the XpressRom development platform (as indicated in the AMD guide Geode document, the evaluation platform must be distributed freely) but it seems that the software is not longer available. I'd like to say you if I could flash inside the set-top box a coreboot Linux bios. My intent is to convert the set-top box in an Emulator-PC (Nes, Snes, Mame) connected to a TV or an old arcade monitor cabinet. On the net is available a guide to load (via Ethernet or USB) a Linux kernel (2.6.22) in this specific set-top box, but no information are provided to customize the bios. I want to remove the old firmware and transform the top-box in a free Linux system. I want to add an IDE HDD, a Serial Port and customize the box as I want :-) FYI the link to the guide is the follow (sorry but it is in Italian language only): http://tinyurl.com/lyetzlx According to the guide above the main characteristics are (lspci): 00:00.0 Host bridge: Cyrix Corporation PCI Master 00:0f.0 Multimedia controller: Philips Semiconductors TriMedia TM-1300 (rev 83) 00:10.0 Ethernet controller: National Semiconductor Corporation DP83815 (MacPhyter) Ethernet Controller 00:12.0 ISA bridge: National Semiconductor Corporation SCx200 Bridge 00:12.1 Bridge: National Semiconductor Corporation SCx200 SMI 00:12.2 IDE interface: National Semiconductor Corporation SCx200, SC1100 IDE controller (rev 01) 00:12.3 Multimedia audio controller: National Semiconductor Corporation SCx200, SC1100 Audio Controller 00:12.4 VGA compatible controller: National Semiconductor Corporation SCx200 Video (rev 01) 00:12.5 Bridge: National Semiconductor Corporation SCx200 XBus- 00:13.0 USB Controller: Compaq Computer Corporation ZFMicro Chipset USB (rev 08) The Set-Top Box has RGB output, 1 Spdif output, 1 IR for remote controller, 2 SCART (video), 2 USB, 1 SmartCard Reader, 1 Ethernet Port, 128MB RAM and an AMD Geode SC1201 cpu. Datasheet from the vendor: http://tinyurl.com/kxesx82 I downloaded a ton of guides, circuit diagrams (taken from the restrict AMD development page) but no information about the bios programming so I'd like to ask you an help how to proceed :) Thank you very much in advance for the help :) Peter.

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coreboot projects using GizmoSphere
by Iurie 10 Aug '13

10 Aug '13

hello, i would like to know what coreboot projects could be done using GizmoSphere. is somebody already using the GizmoSphere to make some coreboot projects? i thank you in advance for the answer best regards

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Re: [coreboot] coreboot Digest, Vol 102, Issue 5
by John Lewis 07 Aug '13

07 Aug '13

You are asking in the wrong place. If you have a question in relation to something off my website, then you should ask in the comments section of my website. John. On 07/08/2013 06:39, Joseph Smith wrote: > When I tried using flashrom and the file downloaded off John's site, > I > get a failure result. If I flash back to the backup.bios it says > sucess. > Why would this be happened on the Samsung 550? > > On Tue, Aug 6, 2013 at 3:00 AM, <coreboot-request(a)coreboot.org [10]> > wrote: > >> Send coreboot mailing list submissions to >> coreboot(a)coreboot.org [1] >> >> To subscribe or unsubscribe via the World Wide Web, visit >> http://www.coreboot.org/mailman/listinfo/coreboot [2] >> or, via email, send a message with subject or body 'help' to >> coreboot-request(a)coreboot.org [3] >> >> You can reach the person managing the list at >> coreboot-owner(a)coreboot.org [4] >> >> When replying, please edit your Subject line so it is more specific >> than "Re: Contents of coreboot digest..." >> >> Today's Topics: >> >> 1. haswell firmware graphics support (ron minnich) >> >> >> ---------------------------------------------------------------------- >> >> Message: 1 >> Date: Mon, 5 Aug 2013 20:29:07 -0700 >> From: ron minnich <rminnich(a)gmail.com [5]> >> To: coreboot <coreboot(a)coreboot.org [6]> >> Subject: [coreboot] haswell firmware graphics support >> Message-ID: >> <CAP6exYJY6j27tiY1KsTawMki6q=ARV3jwbUQ-JTRRb_q0GhXcg(a)mail.gmail.com >> [7]> >> Content-Type: text/plain; charset=ISO-8859-1 >> >> is now there in coreboot. >> >> If you have a board, such as a wtm2, and would like to work to get >> this set up on your board, please let me know. >> >> All the heavy lifting in the final phase of this work was done by >> Furquan Shaikh, in his summer internship here at Google. He's done a >> very fine job. The code is IMHO really good. What we've learned can >> also be applied to older chipsets, so let me know if you have >> interest >> along those lines. >> >> We're finally breaking open the video bios situation; with luck, it >> will soon be as open as ARM platforms ;-) >> >> thanks >> >> ron >> >> ------------------------------ >> >> _______________________________________________ >> coreboot mailing list >> coreboot(a)coreboot.org [8] >> http://www.coreboot.org/mailman/listinfo/coreboot [9] >> >> End of coreboot Digest, Vol 102, Issue 5 >> ****************************************

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Re: [coreboot] coreboot Digest, Vol 102, Issue 5
by Joseph Smith 07 Aug '13

07 Aug '13

When I tried using flashrom and the file downloaded off John's site, I get a failure result. If I flash back to the backup.bios it says sucess. Why would this be happened on the Samsung 550? On Tue, Aug 6, 2013 at 3:00 AM, <coreboot-request(a)coreboot.org> wrote: > Send coreboot mailing list submissions to > coreboot(a)coreboot.org > > To subscribe or unsubscribe via the World Wide Web, visit > http://www.coreboot.org/mailman/listinfo/coreboot > or, via email, send a message with subject or body 'help' to > coreboot-request(a)coreboot.org > > You can reach the person managing the list at > coreboot-owner(a)coreboot.org > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of coreboot digest..." > > > Today's Topics: > > 1. haswell firmware graphics support (ron minnich) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Mon, 5 Aug 2013 20:29:07 -0700 > From: ron minnich <rminnich(a)gmail.com> > To: coreboot <coreboot(a)coreboot.org> > Subject: [coreboot] haswell firmware graphics support > Message-ID: > <CAP6exYJY6j27tiY1KsTawMki6q= > ARV3jwbUQ-JTRRb_q0GhXcg(a)mail.gmail.com> > Content-Type: text/plain; charset=ISO-8859-1 > > is now there in coreboot. > > If you have a board, such as a wtm2, and would like to work to get > this set up on your board, please let me know. > > All the heavy lifting in the final phase of this work was done by > Furquan Shaikh, in his summer internship here at Google. He's done a > very fine job. The code is IMHO really good. What we've learned can > also be applied to older chipsets, so let me know if you have interest > along those lines. > > We're finally breaking open the video bios situation; with luck, it > will soon be as open as ARM platforms ;-) > > thanks > > ron > > > > ------------------------------ > > _______________________________________________ > coreboot mailing list > coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > > End of coreboot Digest, Vol 102, Issue 5 > **************************************** >

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Re: [coreboot] haswell firmware graphics support
by Luc Verhaegen 07 Aug '13

07 Aug '13

On Mon, Aug 05, 2013 at 08:29:07PM -0700, ron minnich wrote: > > We're finally breaking open the video bios situation; with luck, it > will soon be as open as ARM platforms ;-) To be brutally honest, this was done before (http://libv.livejournal.com/19432.html), as part of my, soon, 10y old struggle to get rid of the ludicrous dependency on video bioses (it seems ludicrous now, but i once was on my own with this view). But this was on (now) much less interesting hw, namely VIA chipsets. And if only AMD hadn't lost control over ATI, we would've easily had it with discrete ATI cards too 6 years ago (as we had reduced the BIOS dependency to only a few hundred lines of board specific bootstrap code). But good to see this work being done now on recent IGPs. Luc Verhaegen.

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Re: [coreboot] haswell firmware graphics support
by Marc Jones 06 Aug '13

06 Aug '13

Well done, Furquan. On Mon, Aug 5, 2013 at 9:29 PM, ron minnich <rminnich(a)gmail.com> wrote: > is now there in coreboot. > > If you have a board, such as a wtm2, and would like to work to get > this set up on your board, please let me know. > > All the heavy lifting in the final phase of this work was done by > Furquan Shaikh, in his summer internship here at Google. He's done a > very fine job. The code is IMHO really good. What we've learned can > also be applied to older chipsets, so let me know if you have interest > along those lines. > > We're finally breaking open the video bios situation; with luck, it > will soon be as open as ARM platforms ;-) > > thanks > > ron > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- http://se-eng.com

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haswell firmware graphics support
by ron minnich 06 Aug '13

06 Aug '13

is now there in coreboot. If you have a board, such as a wtm2, and would like to work to get this set up on your board, please let me know. All the heavy lifting in the final phase of this work was done by Furquan Shaikh, in his summer internship here at Google. He's done a very fine job. The code is IMHO really good. What we've learned can also be applied to older chipsets, so let me know if you have interest along those lines. We're finally breaking open the video bios situation; with luck, it will soon be as open as ARM platforms ;-) thanks ron

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Re: [coreboot] Question regarding two registers on the LPC bridge in AMD Hudson
by Wei Hu 03 Aug '13

03 Aug '13

On Sat, Aug 3, 2013 at 1:09 AM, Wei Hu <wei(a)aristanetworks.com> wrote: > Hi, > > I see hudson_enable_rom() in southbridge/amd/agesa/hudson/bootblock.c > enables LPC ROM decoding and sets up ROM address range 2 to be > identical to ROM size. In particular I'm referring to the two > registers at 0x48 and 0x6c. > > However, when I boot into Linux I found the LPC ROM Range Port Enable > bits were cleared, which is fine I suppose since the boot rom is off > SPI instead of LPC? And the ROM Address Range 2 was set to start from > 0xff00_0000. I think it should start from 0xffc0_0000 instead since > the flash size is 4MB. > > I'm curious what else would bother to write to those registers? Also, > what register on AMD chip is used to cancel the legacy BIOS mapping at > 1MB? On Intel northbridge there are the PAM (programmable attribute > map) registers. On AMD we control the access through the RdDram/WrDram bits in the fixed MTRRs. With bit set, access goes to RAM, otherwise gets passed down to southbridge. Is it correct? > > Thanks, > Wei

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Question regarding two registers on the LPC bridge in AMD Hudson
by Wei Hu 03 Aug '13

03 Aug '13

Hi, I see hudson_enable_rom() in southbridge/amd/agesa/hudson/bootblock.c enables LPC ROM decoding and sets up ROM address range 2 to be identical to ROM size. In particular I'm referring to the two registers at 0x48 and 0x6c. However, when I boot into Linux I found the LPC ROM Range Port Enable bits were cleared, which is fine I suppose since the boot rom is off SPI instead of LPC? And the ROM Address Range 2 was set to start from 0xff00_0000. I think it should start from 0xffc0_0000 instead since the flash size is 4MB. I'm curious what else would bother to write to those registers? Also, what register on AMD chip is used to cancel the legacy BIOS mapping at 1MB? On Intel northbridge there are the PAM (programmable attribute map) registers. Thanks, Wei

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coreboot August 2013