coreboot April 2013

coreboot@coreboot.org

42 participants
125 discussions

Re: [coreboot] UDELAY_IO
by Aaron Durbin 26 Apr '13

26 Apr '13

On Fri, Apr 26, 2013 at 2:29 PM, Aaron Durbin <adurbin(a)chromium.org> wrote: > Question for the masses: does anyone actually use UDELAY_IO? If not, > can we get rid of it? I'll prepare the patch. With APICs, HPETs, TSCs, > etc I really don't see the need for such a thing. Same question for UDELAY_TIMER2.

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UDELAY_IO
by Aaron Durbin 26 Apr '13

26 Apr '13

Question for the masses: does anyone actually use UDELAY_IO? If not, can we get rid of it? I'll prepare the patch. With APICs, HPETs, TSCs, etc I really don't see the need for such a thing. -Aaron

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Re: [coreboot] On loongson CPU or MIPS ARCH
by ron minnich 26 Apr '13

26 Apr '13

Are there development systems for this CPU that we could buy to assist in the effort? Is there reference memory startup code? ron

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Re: [coreboot] Boot flow flexibility changes
by ron minnich 26 Apr '13

26 Apr '13

I will happily confirm you are a great mind :) ron

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Re: [coreboot] Boot flow flexibility changes
by Aaron Durbin 26 Apr '13

26 Apr '13

That sounds exactly the way my thoughts were proceeding. Please confirm you and I are both great minds. :) I hope so because my experience dictates otherwise. On Thu, Apr 25, 2013 at 11:28 PM, ron minnich <rminnich(a)gmail.com> wrote: > we have this notion of timer_init() or whatever we called it on arm. > On all platforms, timer_init could record the clock value when it's > called, and then timer_us could report the time relative to the > starting value of timer_init. > > And then our time would be a 'microseconds since coreboot started' and > would still, I think, easily fit in 32 bits. > > ron

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Re: [coreboot] Boot flow flexibility changes
by ron minnich 26 Apr '13

26 Apr '13

we have this notion of timer_init() or whatever we called it on arm. On all platforms, timer_init could record the clock value when it's called, and then timer_us could report the time relative to the starting value of timer_init. And then our time would be a 'microseconds since coreboot started' and would still, I think, easily fit in 32 bits. ron

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Re: [coreboot] Boot flow flexibility changes
by Aaron Durbin 26 Apr '13

26 Apr '13

On Thu, Apr 25, 2013 at 6:42 PM, David Hendricks <dhendrix(a)google.com> wrote: > On Thu, Apr 25, 2013 at 4:00 PM, ron minnich <rminnich(a)gmail.com> wrote: >> >> Am I doing the math right ... >> >> a 32-bit microsecond timer is about 20 minutes. If we ever take more >> than 20 seconds we need a new job. >> >> That was my logic. > > > Who says the timer has to start at zero? What about the reboot case? This is true, but I was thinking it would start at 0 and be valid for the duration of ramstage. -Aaron

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Re: [coreboot] Boot flow flexibility changes
by Aaron Durbin 26 Apr '13

26 Apr '13

On Thu, Apr 25, 2013 at 6:00 PM, ron minnich <rminnich(a)gmail.com> wrote: > Am I doing the math right ... > > a 32-bit microsecond timer is about 20 minutes. If we ever take more > than 20 seconds we need a new job. > > That was my logic. > You are doing your math correctly. However, not all platforms may have this perfect 1MHz clock. That means the microsecond resolution clock needs to be derived off of a faster ticking hardware clock. That's where we need to be more careful about polling intervals against the hardware source clock. Anyway, it's not impossible; tick rates just need to be worked out. -Aaron

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Re: [coreboot] Boot flow flexibility changes
by Aaron Durbin 26 Apr '13

26 Apr '13

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Re: [coreboot] Boot flow flexibility changes
by David Hendricks 26 Apr '13

26 Apr '13

On Thu, Apr 25, 2013 at 4:00 PM, ron minnich <rminnich(a)gmail.com> wrote: > Am I doing the math right ... > > a 32-bit microsecond timer is about 20 minutes. If we ever take more > than 20 seconds we need a new job. > > That was my logic. > Who says the timer has to start at zero? What about the reboot case? -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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coreboot April 2013