coreboot April 2013

coreboot@coreboot.org

42 participants
125 discussions

Re: [coreboot] On loongson CPU or MIPS ARCH
by Paul Menzel 30 Apr '13

30 Apr '13

Am Sonntag, den 28.04.2013, 20:21 -0700 schrieb ron minnich: > On Sun, Apr 28, 2013 at 7:24 PM, Vladimir 'φ-coder/phcoder' Serbinenko > <phcoder(a)gmail.com> wrote: > > > Could we have a sane discussion about why it's not suitable for this or > > that scenario and what would need to be fixed? Not just quasi-fanatical > > "I don't want it". > > I guess I missed the part where not wanting something was considered insane. […] Could you all please read what Vladimir actually wrote and not put something in his mouth! »You need something as GRUB for it since the chip is too small to hold a kernel anyway.« The »something« makes a difference. He just informed Guang, that he needs a payload, which Guang did not consider yet. As Vladimir already knows coreboot due to his X201s work and dealt with Loongson I find it very nice of him to share his opinion. Thanks, Paul

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[Coreboot ] LGA775 support
by CTO of SPCTNC 29 Apr '13

29 Apr '13

How do you do. Thank you for your effort for supporting coreboot. I saw your patch to coreboot for LGA775 soket. I 'm porting Coreboot to Gigabyte GA-945GCM board(LGA775 socket, i945GC northbridge). In my view, Coreboot does not support LGA775 perfectly. Coreboot seems to have several problems with LGA775. In my case, when it calls wbinvd on "smm_init" function(southbridge/intel/i82801gx/smi.c: Line352), , system goes away. Here is the log: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> ... PCI: 00:1f.3 cmd <- 101 PCI: 02:00.0 cmd <- 03 done. Initializing devices... Root Device init CPU_CLUSTER: 0 init start_eip=0x00001000, code_size=0x00000031 <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< When the code calls wbinvd(), it stops. So, I skipped the calls of wbinvd() or calls of disable_cache(). Then it go out more. But it also stops on [SMM-1]. Here is the log: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000007f800000 size 0x7f740000 type 6 0x000000007f800000 - 0x0000000100000000 size 0x80800000 type 0 call enable_fixed_mtrr() CPU physical address size: 36 bits MTRR: default type WB/UC MTRR counts: 2/2. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 MTRR: 1 base 0x000000007f800000 mask 0x0000000fff800000 type 0 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local apic... apic_id: 0x00 done. CPU: 0 2 siblings memalign Enter, boundary 8, size 152, free_mem_ptr 0015ac70 memalign 0015ac70 CPU: 0 has sibling 1 CPU #0 initialized CPU1: stack_base 00158000, stack_end 00158ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 1. After apic_write. [SMM-1] <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Have you ever seen any board on which Coreboot works well? If you have any idea, please contact me. Thanks & regards. Spcinc.

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Re: [coreboot] On loongson CPU or MIPS ARCH
by Denis 'GNUtoo' Carikli 29 Apr '13

29 Apr '13

On Mon, 29 Apr 2013 12:40:18 -0700 David Hendricks <dhendrix(a)google.com> wrote: > For romstage, > we use a technique called "cache-as-RAM" to exploit the processor > cache (or embedded SRAM, if available) as a temporary location to set > up a stack and run C code. Vladimir pointed to me(on IRC) that romcc is not ported to MIPS yet. Denis.

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Re: [coreboot] UDELAY_IO
by Patrick Georgi 29 Apr '13

29 Apr '13

Am 29.04.2013 17:49, schrieb ron minnich: > some of the super primitive chips used to need it. With any luck its > day is done, as is TIMER2 ... I think biffer board requires it. Patrick

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Re: [coreboot] UDELAY_IO
by ron minnich 29 Apr '13

29 Apr '13

some of the super primitive chips used to need it. With any luck its day is done, as is TIMER2 ... ron

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Trac reminder: list of new ticket(s)
by coreboot tracker 29 Apr '13

29 Apr '13

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Re: [coreboot] On loongson CPU or MIPS ARCH
by Vladimir 'φ-coder/phcoder' Serbinenko 29 Apr '13

29 Apr '13

On 29.04.2013 04:09, ron minnich wrote: > not everyone wants or needs grub. So that's part of the point. Could we have a sane discussion about why it's not suitable for this or that scenario and what would need to be fixed? Not just quasi-fanatical "I don't want it".

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Re: [coreboot] On loongson CPU or MIPS ARCH
by Paul Menzel 29 Apr '13

29 Apr '13

Dear Li¹, welcome to coreboot. If I am not mistaken you are already active in the SeaBIOS project. Am Donnerstag, den 25.04.2013, 11:59 +0800 schrieb li guang: > do we have plan to add loongson CPU or MIPS ARCH support? There is no plan that I know of. > It seems no person from loongson contribute to this, > and can I try to make some efforts on this topic? I guess people contributing stuff are always welcome. Though I have no experience with loongson and MIPS, so I cannot comment how feasible this is. Thanks, Paul ¹ Is that your first name? PS: You should probably subscribe to the coreboot list, so your message are not delivered with a delay.

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Re: [coreboot] On loongson CPU or MIPS ARCH
by li guang 29 Apr '13

29 Apr '13

在 2013-04-26五的 11:10 -0700，David Hendricks写道： > On Thu, Apr 25, 2013 at 5:13 PM, li guang <lig.fnst(a)cn.fujitsu.com> > wrote: > > > > > > Am Donnerstag, den 25.04.2013, 11:59 +0800 schrieb li guang: > > > > > do we have plan to add loongson CPU or MIPS ARCH support? > > > > There is no plan that I know of. > > > > > It seems no person from loongson contribute to this, > > > and can I try to make some efforts on this topic? > > > > I guess people contributing stuff are always welcome. Though > I have no > > experience with loongson and MIPS, so I cannot comment how > feasible this > > is. > > > OK. > So, firstly, I will try to add loongson 2E support. > > > Great! As you may be aware, we have recently added ARMv7 support which > you might want to use as an example. The architecture code is in > src/arch/armv7, the CPU code is in > src/cpu/samsung/{exynos5250,exynos5-common}, and the first ARM > motherboard target is in src/mainboard/google/snow. > > > The ARM stuff is still under active development, and we are still > making changes to code that was imported from another codebase > (u-boot). But overall it works and we are able to load a payload and > boot Linux. Thanks! I will get help from ARMv7 code. > > > -- > David Hendricks (dhendrix) > Systems Software Engineer, Google Inc.

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Re: [coreboot] On loongson CPU or MIPS ARCH
by Vladimir 'φ-coder/phcoder' Serbinenko 26 Apr '13

26 Apr '13

On 26.04.2013 23:07, ron minnich wrote: > I'll look at that code. > As a side note: fwstart.S inits video on yeeloong, this was done so because I was under impression that watchdog was conditioned on video init while in fact I applied wrong GPIO map. It stayed this way but doesn't have to be so. Also if there is enough interest I'm willing to consider detaching init code in a way reusable by other payloads as long as it doesn't incur maintainance time on me. > ron >

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coreboot April 2013