coreboot October 2013

coreboot@coreboot.org

32 participants
72 discussions

Re: [coreboot] The OS of open source solution
by jstkf2012＠126.com 09 Oct '13

09 Oct '13

Hi Zoran, About the generic mechanism which incorporates INTEL FSPs into Coreboot , you can see this: http://www.intel.cn/content/dam/www/public/us/en/documents/training/intel-f… Thanks, Tank From: Stojsavljevic, Zoran Date: 2013-10-09 00:38 To: jstkf2012(a)126.com CC: David Hendricks; coreboot Subject: RE: [coreboot] The OS of open source solution Hello Tank, Good to know. It is interesting how you did manage to incorporate IVB FSP into the present Coreboot, since I am not aware of generic mechanism which incorporates INTEL FSPs into Coreboot. Another option will be that you used IVB FSP instead of/simply replacing Google binary SNB mrc.bin … Did NOT come to my mind earlier. Good to know! Another idea to explore. ;-) Aren't you? And, no, FSP is much more than BIOS MRC: http://www.intel.de/content/dam/www/public/us/en/documents/presentation/bld… Here, on page 11, you can see (public document) that FSP is actually SEC + PEIM phases (bit less, board init is not there), in nutshell. Zoran _______ Most of The Time you should be “intel inside” to be capable to think “out of the box”. _______ From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of jstkf2012(a)126.com Sent: Tuesday, October 08, 2013 11:05 AM To: Stojsavljevic, Zoran Cc: David Hendricks; coreboot Subject: Re: [coreboot] The OS of open source solution Hi Zoran, I am now using Intel's Fsp. I doesn't have the source code of the Fsp .But in my opinion, it just like traditional bios's MRC. Thanks, Tank From: Stojsavljevic, Zoran Date: 2013-10-08 16:30 To: jstkf2012(a)126.com; David Hendricks CC: coreboot Subject: Re: [coreboot] The OS of open source solution Hello Tank, Are you using with your CC2 only EFI and/or UEFI BIOS? Or you are also using Google’s SNB mrc.bin? Or maybe you have tried with INTEL’s IVB FSP? Thank you, Zoran _______ Most of The Time you should be “intel inside” to be capable to think “out of the box”. From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of jstkf2012(a)126.com Sent: Tuesday, October 08, 2013 9:28 AM To: David Hendricks Cc: coreboot Subject: Re: [coreboot] The OS of open source solution Hi David， Thanks for your great help. My mainboard is cougarcanyon2 ,now I can boot to DOS by the solution of Coreboot+Seabios. But it can't install OS(both Win7 32bit , ubuntu 32bit,android) by CD-ROM. 1.I use CD-ROM to install the OS ,but it seems that both android & linux & win7 will halt during the installation . 2.Firstly, I install the OS(android , linux , win7) into sata by traditional UEFI bios. Secondly, I flash the coreboot.rom on my board. Finally, I can boot to the OS (android , linux) which is installed by traditional UEFI bios. Generally speaking,does coreboot support to use CD-ROM to install the OS? Thanks, TankTang From: David Hendricks Date: 2013-10-08 10:48 To: jstkf2012(a)126.com CC: coreboot Subject: Re: [coreboot] The OS of open source solution On Mon, Oct 7, 2013 at 6:25 PM, jstkf2012(a)126.com <jstkf2012(a)126.com> wrote: Hi Maillinglist, I’m now trying to boot OS with open source solution (Coreboot + SeaBIOS), but have some questions. For example, 1.Which OS can be supported by this kind of solution? For example, is Win7 or Win8 supported? Win7 has been booted successfully, along with others: http://www.coreboot.org/SeaBIOS#Windows 2.How to build/create or customize the OS images? You should not need to customize the OS images. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft: Feldkirchen bei Muenchen Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk Registergericht: Muenchen HRB 47456 Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052 Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft: Feldkirchen bei Muenchen Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk Registergericht: Muenchen HRB 47456 Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052

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Re: [coreboot] The OS of open source solution
by jstkf2012＠126.com 08 Oct '13

08 Oct '13

Hi Zoran, I am now using Intel's Fsp. I doesn't have the source code of the Fsp .But in my opinion, it just like traditional bios's MRC. Thanks, Tank From: Stojsavljevic, Zoran Date: 2013-10-08 16:30 To: jstkf2012(a)126.com; David Hendricks CC: coreboot Subject: RE: [coreboot] The OS of open source solution Hello Tank, Are you using with your CC2 only EFI and/or UEFI BIOS? Or you are also using Google’s SNB mrc.bin? Or maybe you have tried with INTEL’s IVB FSP? Thank you, Zoran _______ Most of The Time you should be “intel inside” to be capable to think “out of the box”. From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of jstkf2012(a)126.com Sent: Tuesday, October 08, 2013 9:28 AM To: David Hendricks Cc: coreboot Subject: Re: [coreboot] The OS of open source solution Hi David， Thanks for your great help. My mainboard is cougarcanyon2 ,now I can boot to DOS by the solution of Coreboot+Seabios. But it can't install OS(both Win7 32bit , ubuntu 32bit,android) by CD-ROM. 1.I use CD-ROM to install the OS ,but it seems that both android & linux & win7 will halt during the installation . 2.Firstly, I install the OS(android , linux , win7) into sata by traditional UEFI bios. Secondly, I flash the coreboot.rom on my board. Finally, I can boot to the OS (android , linux) which is installed by traditional UEFI bios. Generally speaking,does coreboot support to use CD-ROM to install the OS? Thanks, TankTang From: David Hendricks Date: 2013-10-08 10:48 To: jstkf2012(a)126.com CC: coreboot Subject: Re: [coreboot] The OS of open source solution On Mon, Oct 7, 2013 at 6:25 PM, jstkf2012(a)126.com <jstkf2012(a)126.com> wrote: Hi Maillinglist, I’m now trying to boot OS with open source solution (Coreboot + SeaBIOS), but have some questions. For example, 1.Which OS can be supported by this kind of solution? For example, is Win7 or Win8 supported? Win7 has been booted successfully, along with others: http://www.coreboot.org/SeaBIOS#Windows 2.How to build/create or customize the OS images? You should not need to customize the OS images. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft: Feldkirchen bei Muenchen Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk Registergericht: Muenchen HRB 47456 Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052

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Re: [coreboot] The OS of open source solution
by jstkf2012＠126.com 08 Oct '13

08 Oct '13

Hi David， Thanks for your great help. My mainboard is cougarcanyon2 ,now I can boot to DOS by the solution of Coreboot+Seabios. But it can't install OS(both Win7 32bit , ubuntu 32bit,android) by CD-ROM. 1.I use CD-ROM to install the OS ,but it seems that both android & linux & win7 will halt during the installation . 2.Firstly, I install the OS(android , linux , win7) into sata by traditional UEFI bios. Secondly, I flash the coreboot.rom on my board. Finally, I can boot to the OS (android , linux) which is installed by traditional UEFI bios. Generally speaking,does coreboot support to use CD-ROM to install the OS? Thanks, TankTang From: David Hendricks Date: 2013-10-08 10:48 To: jstkf2012(a)126.com CC: coreboot Subject: Re: [coreboot] The OS of open source solution On Mon, Oct 7, 2013 at 6:25 PM, jstkf2012(a)126.com <jstkf2012(a)126.com> wrote: Hi Maillinglist, I’m now trying to boot OS with open source solution (Coreboot + SeaBIOS), but have some questions. For example, 1.Which OS can be supported by this kind of solution? For example, is Win7 or Win8 supported? Win7 has been booted successfully, along with others: http://www.coreboot.org/SeaBIOS#Windows 2.How to build/create or customize the OS images? You should not need to customize the OS images. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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iasl compiler/disassembler getting confused by Scope operator
by Michael S. Tsirkin 08 Oct '13

08 Oct '13

I observe the following issue with acpica-tools-20130823-2.fc19.i686: Compile a file, disassemble it then compile again, this fails because the Extern directives produced by disassembler confuse the compiler. Wiuld be nice if this was fixed disasseble then compile is a nice sanity-check tool. Thanks! ---> Original: /* * Intel ACPI Component Architecture * AML Disassembler version 20130823-32 [Aug 28 2013] * Copyright (c) 2000 - 2013 Intel Corporation * * Disassembly of SSDT, Mon Oct 7 09:48:29 2013 * * Original Table Header: * Signature "SSDT" * Length 0x00000FE0 (4064) * Revision 0x01 * Checksum 0x9F * OEM ID "BOCHS " * OEM Table ID "BXPCSSDT" * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("SSDT.aml", "SSDT", 1, "BOCHS ", "BXPCSSDT", 0x00000001) { External (_SB_.PCI0, DeviceObj) External (_SB_.PCI0.ISA_, DeviceObj) External (BNUM, FieldUnitObj) External (CPEJ, MethodObj) // 2 Arguments External (CPMA, MethodObj) // 1 Arguments External (CPST, MethodObj) // 1 Arguments External (PCEJ, MethodObj) // 2 Arguments External (PCID, FieldUnitObj) External (PCIU, FieldUnitObj) Scope (\) { Name (P0S, 0x80000000) Name (P0E, 0xFEBFFFFF) Name (P1V, 0x00) Name (P1S, Buffer (0x08) { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) Name (P1E, Buffer (0x08) { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) Name (P1L, Buffer (0x08) { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) } Scope (\) { Name (_S3, Package (0x04) // _S3_: S3 System State { One, One, Zero, Zero }) Name (_S4, Package (0x04) // _S4_: S4 System State { 0x02, 0x02, Zero, Zero }) Name (_S5, Package (0x04) // _S5_: S5 System State { Zero, Zero, Zero, Zero }) } Scope (\_SB.PCI0.ISA) { Device (PEVT) { Name (_HID, "QEMU0001") // _HID: Hardware ID Name (PEST, 0x0000) OperationRegion (PEOR, SystemIO, PEST, One) Field (PEOR, ByteAcc, NoLock, Preserve) { PEPT, 8 } Method (_STA, 0, NotSerialized) // _STA: Status { Store (PEST, Local0) If (LEqual (Local0, Zero)) { Return (Zero) } Else { Return (0x0F) } } Method (RDPT, 0, NotSerialized) { Store (PEPT, Local0) Return (Local0) } Method (WRPT, 1, NotSerialized) { Store (Arg0, PEPT) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, 0x0000, // Range Minimum 0x0000, // Range Maximum 0x01, // Alignment 0x01, // Length _Y03) }) CreateWordField (_CRS, \_SB.PCI0.ISA.PEVT._Y03._MIN, IOMN) // _MIN: Minimum Base Address CreateWordField (_CRS, \_SB.PCI0.ISA.PEVT._Y03._MAX, IOMX) // _MAX: Maximum Base Address Method (_INI, 0, NotSerialized) // _INI: Initialize { Store (PEST, IOMN) Store (PEST, IOMX) } } } Scope (_SB) { Scope (PCI0) { Name (BSEL, Zero) Device (S18) { Name (_SUN, 0x03) // _SUN: Slot User Number Name (_ADR, 0x00030000) // _ADR: Address Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device { PCEJ (BSEL, _SUN) } } Method (DVNT, 2, NotSerialized) { If (And (Arg0, 0x08)) { Notify (S18, Arg1) } } Method (PCNT, 0, NotSerialized) { Store (Zero, BNUM) DVNT (PCIU, One) DVNT (PCID, 0x03) ^S20.PCNT () } Device (S20) { Name (_SUN, 0x04) // _SUN: Slot User Number Name (_ADR, 0x00040000) // _ADR: Address Name (BSEL, One) Method (PCNT, 0, NotSerialized) { Store (One, BNUM) } } } } } --- Compile with iasl foo.dsl Disassemble with iasl -d -e DSDT SSDT.aml (see DSDT.dsl at the end of the mail). /* * Intel ACPI Component Architecture * AML Disassembler version 20130823-32 [Aug 28 2013] * Copyright (c) 2000 - 2013 Intel Corporation * * Disassembly of SSDT.aml, Mon Oct 7 10:10:41 2013 * * Original Table Header: * Signature "SSDT" * Length 0x00000207 (519) * Revision 0x01 * Checksum 0xBF * OEM ID "BOCHS " * OEM Table ID "BXPCSSDT" * OEM Revision 0x00000001 (1) * Compiler ID "INTL" * Compiler Version 0x20130823 (538118179) */ DefinitionBlock ("SSDT.aml", "SSDT", 1, "BOCHS ", "BXPCSSDT", 0x00000001) { External (_SB_.PCI0.ISA_, DeviceObj) External (BNUM, FieldUnitObj) External (PCEJ, MethodObj) // 2 Arguments External (PCI0, DeviceObj) External (PCID, FieldUnitObj) External (PCIU, FieldUnitObj) Scope (\) { Name (P0S, 0x80000000) Name (P0E, 0xFEBFFFFF) Name (P1V, Zero) Name (P1S, Buffer (0x08) { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) Name (P1E, Buffer (0x08) { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) Name (P1L, Buffer (0x08) { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) } Scope (\) { Name (_S3, Package (0x04) // _S3_: S3 System State { One, One, Zero, Zero }) Name (_S4, Package (0x04) // _S4_: S4 System State { 0x02, 0x02, Zero, Zero }) Name (_S5, Package (0x04) // _S5_: S5 System State { Zero, Zero, Zero, Zero }) } Scope (\_SB.PCI0.ISA) { Device (PEVT) { Name (_HID, "QEMU0001") // _HID: Hardware ID Name (PEST, Zero) OperationRegion (PEOR, SystemIO, PEST, One) Field (PEOR, ByteAcc, NoLock, Preserve) { PEPT, 8 } Method (_STA, 0, NotSerialized) // _STA: Status { Store (PEST, Local0) If (LEqual (Local0, Zero)) { Return (Zero) } Else { Return (0x0F) } } Method (RDPT, 0, NotSerialized) { Store (PEPT, Local0) Return (Local0) } Method (WRPT, 1, NotSerialized) { Store (Arg0, PEPT) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, 0x0000, // Range Minimum 0x0000, // Range Maximum 0x01, // Alignment 0x01, // Length _Y00) }) CreateWordField (_CRS, \_SB.PCI0.ISA.PEVT._Y00._MIN, IOMN) // _MIN: Minimum Base Address CreateWordField (_CRS, \_SB.PCI0.ISA.PEVT._Y00._MAX, IOMX) // _MAX: Maximum Base Address Method (_INI, 0, NotSerialized) // _INI: Initialize { Store (PEST, IOMN) Store (PEST, IOMX) } } } Scope (_SB) { Scope (PCI0) { Name (BSEL, Zero) Device (S18) { Name (_SUN, 0x03) // _SUN: Slot User Number Name (_ADR, 0x00030000) // _ADR: Address Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device { PCEJ (BSEL, _SUN) } } Method (DVNT, 2, NotSerialized) { If (And (Arg0, 0x08)) { Notify (S18, Arg1) } } Method (PCNT, 0, NotSerialized) { Store (Zero, BNUM) DVNT (PCIU, One) DVNT (PCID, 0x03) ^S20.PCNT () } Device (S20) { Name (_SUN, 0x04) // _SUN: Slot User Number Name (_ADR, 0x00040000) // _ADR: Address Name (BSEL, One) Method (PCNT, 0, NotSerialized) { Store (One, BNUM) } } } } } <---- Compilation error: Intel ACPI Component Architecture ASL Optimizing Compiler version 20130823-32 [Aug 28 2013] Copyright (c) 2000 - 2013 Intel Corporation SSDT.dsl 130: Scope (PCI0) Error 6117 - ^ Existing object has invalid type for Scope operator (PCI0 [Untyped]) If you compane the original and the disassebled result, you see the issue: DefinitionBlock ("SSDT.aml", "SSDT", 1, "BOCHS ", "BXPCSSDT", 0x00000001) { - External (_SB_.PCI0, DeviceObj) External (_SB_.PCI0.ISA_, DeviceObj) External (BNUM, FieldUnitObj) External (CPEJ, MethodObj) // 2 Arguments External (CPMA, MethodObj) // 1 Arguments External (CPST, MethodObj) // 1 Arguments External (PCEJ, MethodObj) // 2 Arguments + External (PCI0, DeviceObj) External (PCID, FieldUnitObj) External (PCIU, FieldUnitObj) So External (_SB_.PCI0.ISA_, DeviceObj) implicitly defines PCI0 as an untyped object, Scope (PCI0) is then taken to refer to that (since it's in the correct namespace). Also, External (PCI0, DeviceObj) is produced in the wrong namespace. To reproduce you will need a DSDT (for disassembler), see DSDT.dsl below: /* * Intel ACPI Component Architecture * AML Disassembler version 20130823-32 [Aug 28 2013] * Copyright (c) 2000 - 2013 Intel Corporation * * Disassembly of DSDT, Mon Oct 7 09:58:06 2013 * * Original Table Header: * Signature "DSDT" * Length 0x00001158 (4440) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support * Checksum 0xC6 * OEM ID "BXPC" * OEM Table ID "BXDSDT" * OEM Revision 0x00000001 (1) * Compiler ID "INTL" * Compiler Version 0x20130823 (538118179) */ DefinitionBlock ("DSDT.aml", "DSDT", 1, "BXPC", "BXDSDT", 0x00000001) { External (_SB_.PCI0.PCNT, MethodObj) External (NTFY, MethodObj) External (CPON) External (P0E_, IntObj) External (P0S_, IntObj) External (P1E_, IntObj) External (P1L_, IntObj) External (P1S_, IntObj) External (P1V_) Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } Method (DBUG, 1, NotSerialized) { ToHexString (Arg0, Local0) ToBuffer (Local0, Local0) Subtract (SizeOf (Local0), One, Local1) Store (Zero, Local2) While (LLess (Local2, Local1)) { Store (DerefOf (Index (Local0, Local2)), DBGB) Increment (Local2) } Store (0x0A, DBGB) } } Scope (_SB) { Device (PCI0) { Name (_HID, EisaId ("PNP0A03")) // _HID: Hardware ID Name (_ADR, Zero) // _ADR: Address Name (_UID, One) // _UID: Unique ID } } Scope (_SB.PCI0) { Device (ISA) { Name (_ADR, 0x00010000) // _ADR: Address OperationRegion (P40C, PCI_Config, 0x60, 0x04) Name (FDEN, One) } } Scope (_SB.PCI0) { OperationRegion (PCST, SystemIO, 0xAE00, 0x08) Field (PCST, DWordAcc, NoLock, WriteAsZeros) { PCIU, 32, PCID, 32 } OperationRegion (SEJ, SystemIO, 0xAE08, 0x04) Field (SEJ, DWordAcc, NoLock, WriteAsZeros) { B0EJ, 32 } OperationRegion (BNMR, SystemIO, 0xAE10, 0x04) Field (BNMR, DWordAcc, NoLock, WriteAsZeros) { BNUM, 32 } Mutex (BLCK, 0x00) Method (PCEJ, 2, NotSerialized) { Acquire (BLCK, 0xFFFF) Store (Arg0, BNUM) Store (ShiftLeft (One, Arg1), B0EJ) Release (BLCK) Return (Zero) } } Scope (_GPE) { Name (_HID, "ACPI0006") // _HID: Hardware ID Method (_L00, 0, NotSerialized) // _Lxx: Level-Triggered GPE { } Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE { Acquire (\_SB.PCI0.BLCK, 0xFFFF) \_SB.PCI0.PCNT () Release (\_SB.PCI0.BLCK) } } }

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Re: [coreboot] The OS of open source solution
by Patrick Georgi 08 Oct '13

08 Oct '13

Am 2013-10-08 04:48, schrieb David Hendricks: > Win7 has been booted successfully, along with > others: http://www.coreboot.org/SeaBIOS#Windows [1] Also Windows XP, Windows 2003 Server, Windows 2008 Server and Windows 8. Some of the Windows enabling happens in the board support, so things may look different on each board. However there's nothing in coreboot or SeaBIOS that prevents it (as shown by my tests). Patrick

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The OS of open source solution
by jstkf2012＠126.com 08 Oct '13

08 Oct '13

Hi Maillinglist, I’m now trying to boot OS with open source solution (Coreboot + SeaBIOS), but have some questions. For example, 1.Which OS can be supported by this kind of solution? For example, is Win7 or Win8 supported? 2.How to build/create or customize the OS images? Thanks, TankTang

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Re: [coreboot] VIA C7 on BCom Winnet P680 - L1/L2 cache very slow
by Aaron Durbin 07 Oct '13

07 Oct '13

On Sun, Oct 6, 2013 at 1:43 AM, Corey Osgood <corey.osgood(a)gmail.com> wrote: > After sending the last message, I've done a little more debugging and dumped > cr0, and also checked the C7 FCR, everything indicates the cache is properly > enabled and not in NoWriteThrough mode, although I have very little C7 > specific information and none of it relating to cache. > > So, I'm now looking elsewhere, and at the moment I'm looking at MTRRs. All > the fixed MTRRs, under coreboot, are 0'd out, and variable are all type 6 > (WB?), as can be seen in the attached boot log. Here's the way the stock > BIOS sets them up: MTRR: Physical address space: 0x0000000000000000 - 0x0000000004000000 size 0x04000000 type 0 0x0000000004000000 - 0x000000003e000000 size 0x3a000000 type 6 0x000000003e000000 - 0x00000000fff80000 size 0xc1f80000 type 0 0x00000000fff80000 - 0x0000000100000000 size 0x00080000 type 5 0->64MiB is uncacheable 64MiB->992MiB is cacheable 992MiB-> -512KiB is uncacheable -512KiB->4GiB is write-protect The fixed MTRRs cover the first 1MiB so it's not surprising those are zero'd out. The only odd thing I see in the variable MTRRs is the ROM not being marked as WP, but I suspect that is from CONFIG_CACHE_ROM not being enabled. Looking through your resources I don't see anything that covers memory during read resources (flags field): #define IORESOURCE_MEM 0x00000200 #define IORESOURCE_CACHEABLE 0x00004000 Any flags with the bits 0x4200 should be cacheable memory. DOMAIN: 0000 resource base c0000 size 3df40000 align 0 gran 0 limit 0 flags e0004200 index b The above shows up ding assign resources. The MTRR code has a 64MiB min alignment which makes me think that is where the 64MiB->992MiB comes from. I would do two things: 1. Add all ram resources during the read_resources() step. That way the IO hole can be properly picked. 2. Ensure all the memory you know exist are added to the resource list, including 0 -> 64MiB. Hope that helps. -Aaron

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Re: [coreboot] VIA C7 on BCom Winnet P680 - L1/L2 cache very slow
by Corey Osgood 06 Oct '13

06 Oct '13

After sending the last message, I've done a little more debugging and dumped cr0, and also checked the C7 FCR, everything indicates the cache is properly enabled and not in NoWriteThrough mode, although I have very little C7 specific information and none of it relating to cache. So, I'm now looking elsewhere, and at the moment I'm looking at MTRRs. All the fixed MTRRs, under coreboot, are 0'd out, and variable are all type 6 (WB?), as can be seen in the attached boot log. Here's the way the stock BIOS sets them up: # IA32_MTRR_FIX64K_00000 0x00000250 = 0x0606060606060606 # IA32_MTRR_FIX16K_80000 0x00000258 = 0x0606060606060606 # IA32_MTRR_FIX16K_A0000 0x00000259 = 0x0000000000000000 # IA32_MTRR_FIX4K_C0000 0x00000268 = 0x0505050505050505 # IA32_MTRR_FIX4K_C8000 0x00000269 = 0x0000000505050505 # IA32_MTRR_FIX4K_D0000 0x0000026a = 0x0000000000000000 # IA32_MTRR_FIX4K_D8000 0x0000026b = 0x0000000000000000 # IA32_MTRR_FIX4K_E0000 0x0000026c = 0x0000000000000000 # IA32_MTRR_FIX4K_E8000 0x0000026d = 0x0000000000000000 # IA32_MTRR_FIX4K_F0000 0x0000026e = 0x0404040404040404 # IA32_MTRR_FIX4K_F8000 0x0000026f = 0x0404040404040400 root@khan:~/coreboot/util/msrtool# cat /proc/mtrr reg00: base=0x000000000 ( 0MB), size= 1024MB, count=1: write-back reg01: base=0x03e000000 ( 992MB), size= 32MB, count=1: uncachable reg02: base=0x0f8000000 ( 3968MB), size= 32MB, count=2: write-combining reg03: base=0x03df00000 ( 991MB), size= 1MB, count=1: uncachable reg04: base=0x0f4000000 ( 3904MB), size= 32MB, count=1: write-combining I'm frankly not sure if I'm on the right track or not, I've done some work porting chipsets but very little with the CPU itself. Any help would be greatly appreciated, I was hoping this project was "just" writing IRQ and ACPI tables. Thanks, Corey On Sat, Oct 5, 2013 at 6:03 AM, Corey Osgood <corey.osgood(a)gmail.com> wrote: > I'm working on fixing up the BCom WinNet P680 port, which is a Via C7 CPU > and CN700/VT8237R chipset. I've got it running enough to boot a Memtest86 > payload, but it's very slow. The L1 and L2 cache are reported as running at > 11-12MB/s by Memtest, which is much slower then they're reported as running > in the stock BIOS. This makes any further testing impractical, as it takes > ages load a kernel+initrd. Any suggestions on how to fix this, or where to > look? > > Thanks, > Corey >

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VIA C7 on BCom Winnet P680 - L1/L2 cache very slow
by Corey Osgood 05 Oct '13

05 Oct '13

I'm working on fixing up the BCom WinNet P680 port, which is a Via C7 CPU and CN700/VT8237R chipset. I've got it running enough to boot a Memtest86 payload, but it's very slow. The L1 and L2 cache are reported as running at 11-12MB/s by Memtest, which is much slower then they're reported as running in the stock BIOS. This makes any further testing impractical, as it takes ages load a kernel+initrd. Any suggestions on how to fix this, or where to look? Thanks, Corey

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Please test change in coreboot[master]: cpu/x86/mtrr/mtrr.c: Remove superfluous assignment to `type_...
by Paul Menzel 04 Oct '13

04 Oct '13

Dear coreboot folks, could somebody please test commit »cpu/x86/mtrr/mtrr.c: Remove superfluous assignment to `type_index`« [1] as today I broke my ASRock E350M1 board booting with coreboot including this patch. I am not sure though as I also changed the SeaBIOS payload applying the patch series »Convert AHCI driver to run entirely in 32bit mode« [2]. Kevin O'Connor (6): Rearrange stack_hop_back() call in wait_irq, check_irqs, and _farcall16. Minor - move call16 assembler in romlayout.S. Make __call16 use C calling convention and support two passed parameters. Update _farcall16() to pass segment of callregs explicitly. Support call16() calls after entering 32bit mode from call32(). Run ahci code entirely in 32bit mode. Makefile | 4 +- src/block.c | 13 ++++-- src/hw/ahci.c | 15 ++----- src/hw/blockcmd.c | 5 ++- src/romlayout.S | 132 ++++++++++++++++++++++++++++++++---------------------- src/stacks.c | 78 +++++++++++++++++++------------- 6 files changed, 145 insertions(+), 102 deletions(-) coreboot runs through just fine and then SeaBIOS halts at `mtrr init` when build with serial console and debug level 8. Using the SeaBIOS payload built with no serial console, it seems, that the board just reset and just hang. Bot logs captured with `readserial.py` are attached. Thanks, Paul [1] http://review.coreboot.org/3953 [2] http://www.coreboot.org/pipermail/seabios/2013-October/007040.html

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coreboot October 2013