2013/10/29 Idwer Vollering <vidwer(a)gmail.com>:
> 2013/10/29 Haywood-Evans Matthew <MAHEVANS(a)qinetiq.com>:
>> Hi,
>>
>> I am presently looking at trying to get Coreboot up and running on an
>> ASUS F2A85-M system. I am however running into some issues.
>>
>> Using a bus pirate and flashrom I first backed up the original bios,
>> then erased the chip and restored the bios to ensure I had the basic
>> read/write capability working and this all worked correctly.
>
> My board came with AMI (U)EFI v5018.
>
> I was able to erase, and write to, every part of the flash chip with
> that particular version while leaving the chip in its socket.
> v6404 wasn't that permissive anymore.
>
>>
>> Then I proceeded to build a standard coreboot image using seabios as a
>> payload (using an external VGA card), leaving all the settings as
>> default apart from selecting the motherboard, upon writing this to the
>> flash and rebooting the machine I had no output from the VGA adapter and
>> nothing from the serial port.
>
> SeaBIOS should run the optionrom that is present on/for the offboard GPU.
>
>>
>> Next I removed the external VGA and followed the instructions at
>> http://www.coreboot.org/ASUS_F2A85-M taking a local copy of the VGA
>> bios and embedding that into the coreboot image, rebuilt and re-flashed
>> to get the same result as previous.
>
> The APU's PCI ID ofcourse varies, these lines are there (in dmesg and
> lspci -nn) when booting linux:
>
> [ 0.047202] smpboot: CPU0: AMD A8-5500 APU with Radeon(tm) HD
> Graphics (fam: 15, model: 10, stepping: 01)
>
> 00:01.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc.
> [AMD/ATI] Trinity [Radeon HD 7560D] [1002:9904]
>
>>
>> After some investigation I created a serial ice image and loaded that,
>> this worked giving me a serial ice prompt on the COM port. Using this,
>> and the QEMU provided, I proceeded to try and run the bios files created
>> in the last two stages, in the serial ice I see a lot of reads (takes
>> about 20 mins) before it exits with Bad memory pointer and core dumps.
>>
>> I have been building the coreboot images on a different machine to the
>> target (Core i7) but have rebuilt them with the crossgcc in case issues
>> with the development PC where causing the issue, however I got the same
>> results.
>>
>> I am now at a loss of where to go next to get this working and would
>> appreciate any insight.
>>
>> The target system I am working on is
>> F2A85-M
>> 4GB Corsair Ram
>
> What's the full name of that memory module? More important: what's its
> working voltage?
> One can confirm from coreboot's menu: mainboard -> DDR3 memory voltage
>
>> AMD A10 6800K FM2 CPU
>
> Assuming that the PCI ID of the abovementioned APU is 1002:990c, *and
> the sha1sum of the with dd from memory extracted VGA optionrom (while
> the AMI software is booted) is
> e8fd60fd8746ab7f1a997897807d3fdbd119bf7e*, I can provide a working
> image: http://ra.openbios.org/~idwer/f2a85-m/coreboot_1002_990c.rom
I almost forgot to mention that this is built for 1,5V memory.
>
> See http://pci-ids.ucw.cz/read/PC/1002/990c
>
>>
>> Thanks
>> Matt
>
> HTH,
>
> Idwer
2013/10/29 Haywood-Evans Matthew <MAHEVANS(a)qinetiq.com>:
> Hi,
>
> I am presently looking at trying to get Coreboot up and running on an
> ASUS F2A85-M system. I am however running into some issues.
>
> Using a bus pirate and flashrom I first backed up the original bios,
> then erased the chip and restored the bios to ensure I had the basic
> read/write capability working and this all worked correctly.
My board came with AMI (U)EFI v5018.
I was able to erase, and write to, every part of the flash chip with
that particular version while leaving the chip in its socket.
v6404 wasn't that permissive anymore.
>
> Then I proceeded to build a standard coreboot image using seabios as a
> payload (using an external VGA card), leaving all the settings as
> default apart from selecting the motherboard, upon writing this to the
> flash and rebooting the machine I had no output from the VGA adapter and
> nothing from the serial port.
SeaBIOS should run the optionrom that is present on/for the offboard GPU.
>
> Next I removed the external VGA and followed the instructions at
> http://www.coreboot.org/ASUS_F2A85-M taking a local copy of the VGA
> bios and embedding that into the coreboot image, rebuilt and re-flashed
> to get the same result as previous.
The APU's PCI ID ofcourse varies, these lines are there (in dmesg and
lspci -nn) when booting linux:
[ 0.047202] smpboot: CPU0: AMD A8-5500 APU with Radeon(tm) HD
Graphics (fam: 15, model: 10, stepping: 01)
00:01.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc.
[AMD/ATI] Trinity [Radeon HD 7560D] [1002:9904]
>
> After some investigation I created a serial ice image and loaded that,
> this worked giving me a serial ice prompt on the COM port. Using this,
> and the QEMU provided, I proceeded to try and run the bios files created
> in the last two stages, in the serial ice I see a lot of reads (takes
> about 20 mins) before it exits with Bad memory pointer and core dumps.
>
> I have been building the coreboot images on a different machine to the
> target (Core i7) but have rebuilt them with the crossgcc in case issues
> with the development PC where causing the issue, however I got the same
> results.
>
> I am now at a loss of where to go next to get this working and would
> appreciate any insight.
>
> The target system I am working on is
> F2A85-M
> 4GB Corsair Ram
What's the full name of that memory module? More important: what's its
working voltage?
One can confirm from coreboot's menu: mainboard -> DDR3 memory voltage
> AMD A10 6800K FM2 CPU
Assuming that the PCI ID of the abovementioned APU is 1002:990c, *and
the sha1sum of the with dd from memory extracted VGA optionrom (while
the AMI software is booted) is
e8fd60fd8746ab7f1a997897807d3fdbd119bf7e*, I can provide a working
image: http://ra.openbios.org/~idwer/f2a85-m/coreboot_1002_990c.rom
See http://pci-ids.ucw.cz/read/PC/1002/990c
>
> Thanks
> Matt
HTH,
Idwer
Matt,
Could you put your coreboot .config file somewhere for us to look at?
The PCI ID of the graphics device (BDF 0:1.0) must match CONFIG_VGA_BIOS_ID
in order for the vga option rom to get loaded. The alternative is to put
the vga rom
in the CBFS vgaroms/ directory with any name you want (e.g.
vgaroms/matts_vga.rom)
Seabios will then load it.
You can disable CONFIG_VGA_ROM_RUN with this method. Also make sure you
are building your seabios for coreboot.
This would be clearer if your serial console was working. You will want
CONFIG_EARLY_CONSOLE=y
CONFIG_CONSOLE_SERIAL=y
CONFIG_CONSOLE_SERIAL_COM1=y
CONFIG_CONSOLE_SERIAL_115200=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
Thanks,
Dave
On Tue, Oct 29, 2013 at 8:29 AM, Haywood-Evans Matthew <MAHEVANS(a)qinetiq.com
> wrote:
> Hi,
>
> I am presently looking at trying to get Coreboot up and running on an
> ASUS F2A85-M system. I am however running into some issues.
>
> Using a bus pirate and flashrom I first backed up the original bios,
> then erased the chip and restored the bios to ensure I had the basic
> read/write capability working and this all worked correctly.
>
> Then I proceeded to build a standard coreboot image using seabios as a
> payload (using an external VGA card), leaving all the settings as
> default apart from selecting the motherboard, upon writing this to the
> flash and rebooting the machine I had no output from the VGA adapter and
> nothing from the serial port.
>
> Next I removed the external VGA and followed the instructions at
> http://www.coreboot.org/ASUS_F2A85-M taking a local copy of the VGA
> bios and embedding that into the coreboot image, rebuilt and re-flashed
> to get the same result as previous.
>
> After some investigation I created a serial ice image and loaded that,
> this worked giving me a serial ice prompt on the COM port. Using this,
> and the QEMU provided, I proceeded to try and run the bios files created
> in the last two stages, in the serial ice I see a lot of reads (takes
> about 20 mins) before it exits with Bad memory pointer and core dumps.
>
> I have been building the coreboot images on a different machine to the
> target (Core i7) but have rebuilt them with the crossgcc in case issues
> with the development PC where causing the issue, however I got the same
> results.
>
> I am now at a loss of where to go next to get this working and would
> appreciate any insight.
>
> The target system I am working on is
> F2A85-M
> 4GB Corsair Ram
> AMD A10 6800K FM2 CPU
>
> Thanks
> Matt
>
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>
Hi,
I am presently looking at trying to get Coreboot up and running on an
ASUS F2A85-M system. I am however running into some issues.
Using a bus pirate and flashrom I first backed up the original bios,
then erased the chip and restored the bios to ensure I had the basic
read/write capability working and this all worked correctly.
Then I proceeded to build a standard coreboot image using seabios as a
payload (using an external VGA card), leaving all the settings as
default apart from selecting the motherboard, upon writing this to the
flash and rebooting the machine I had no output from the VGA adapter and
nothing from the serial port.
Next I removed the external VGA and followed the instructions at
http://www.coreboot.org/ASUS_F2A85-M taking a local copy of the VGA
bios and embedding that into the coreboot image, rebuilt and re-flashed
to get the same result as previous.
After some investigation I created a serial ice image and loaded that,
this worked giving me a serial ice prompt on the COM port. Using this,
and the QEMU provided, I proceeded to try and run the bios files created
in the last two stages, in the serial ice I see a lot of reads (takes
about 20 mins) before it exits with Bad memory pointer and core dumps.
I have been building the coreboot images on a different machine to the
target (Core i7) but have rebuilt them with the crossgcc in case issues
with the development PC where causing the issue, however I got the same
results.
I am now at a loss of where to go next to get this working and would
appreciate any insight.
The target system I am working on is
F2A85-M
4GB Corsair Ram
AMD A10 6800K FM2 CPU
Thanks
Matt
This email and any attachments to it may be confidential and are
intended solely for the use of the individual to whom it is
addressed. If you are not the intended recipient of this email,
you must neither take any action based upon its contents, nor
copy or show it to anyone. Please contact the sender if you
believe you have received this email in error. QinetiQ may
monitor email traffic data and also the content of email for
the purposes of security. QinetiQ Limited (Registered in England
& Wales: Company Number: 3796233) Registered office: Cody Technology
Park, Ively Road, Farnborough, Hampshire, GU14 0LX http://www.qinetiq.com.
Dear Andrew,
let’s move the discussion of [1] to the list.
Am Mittwoch, den 23.10.2013, 13:43 +0200 schrieb gerrit code review:
> Change subject: dmp/vortex86ex: Initialize I2C controller base address/IRQ
> ......................................................................
>
>
> Patch Set 5:
>
> Do you mean allocating I2C I/O space range dynamically, instead of
> using fixed address? It makes sense, but :
>
> (A) I don't know if coreboot has an API for I/O space
> allocation/reservation. If yes, could you tell me the function names
> so I can check it.
>
> (B) Some legacy applications for our CPU maybe use fixed I/O addresses
> for these devices, because these I/O addresses are fixed in old BIOS.
hopefully, some of the other developers can answer this.
Thanks,
Paul
[1] http://review.coreboot.org/3976
Dear coreboot community,
I'm trying to use coreboot on my second PC and I think I need your help.
I have an ASUS A8V-E Deluxe with coreboot which does work with a single
1GB ECC module, but not with a second identical one. It hangs at jumping
from romstage to coreboot_ram (I hope that's correct). It's last words
are "Jumping to image", then nothing.
I'm attaching two logs from serial console, one with 1x1GB RAM installed
which works, one with 2x1GB which hangs, and also the diff.
Looking at the diff I noticed that in the 2x1GB log there are some
missing lines between
"Copying data from cache to RAM -- switching to use RAM as stack..." and
"Clearing initial memory region: Done".
What should happen in between seems to be omitted, which doesn't make
sense to me, looking at src/cpu/amd/car/post_cache_as_ram.c . With my
little experience I can't figure out what's wrong..
Anything I can do to debug? Do you have an idea?
Some notes:
- 2x1GB starts up with the vendor BIOS but randomly hangs at booting
linux (kernel panic or so)
- 1x1GB works with coreboot and vendor BIOS
- Replacing those 1GB ECC modules (Corsair/Samsung chips) with 512MB ECC
modules (HP/Samsung or MDT/???) leads to the same results (2 modules
fail with coreboot; vendor BIOS unknown)
- 2x512MB non-ECC works!
Why are only 2 modules with ECC failing to boot, but not 2 non-ECC? I
tried commenting out the contents of hw_enable_ecc() in
src/northbridge/amd/amdk8/raminit.c but that didn't change anything.
memtest86+ even still detected ECC (with only one module).
Apart from that I got a little success story: the VIA K8T890 chipset on
this mainboard had a bug in it's first revision, making it incompatible
with dual-core CPUs. I was curious if coreboot also had this limitation,
so I bought a cheap dual-core Opteron 180 and tested it. Vendor BIOS:
one core detected in linux. coreboot: two cores!!
I'm not sure if it's stable because I had two hang-ups last weekend, but
that was probably because I forgot to put in the GPU fan plug.. :)
If anyone knows the details of this chipset bug I'd be very interested.
By the way, the RAM issue is the same with a single-core Athlon 64.
Thanks,
Michael
Andrew DeAngelis wrote:
> Is there anyone out there who has experience with Coreboot on
> Kabini and may be able to answer questions about unexpected
> resets when using the AMD Catalyst graphics driver?
I think you'll have to do more debugging on your own, before someone
will be able to help. My only idea would be either power supplies or
signal integrity issues.
> We're booting Ubuntu and Windows 7 right now with a barely modified
> mainboard code brought over from Olivehill,
I think you should focus on the hardware modifications you've made.
> but I'm sure there must be some things we are doing wrong, esp. ACPI.
ACPI doesn't usually cause sporadic resets when exercising the graphics.
> Also, are there any candidates who may be interested in trading our
> potentially buggy hardware system for some expert help with the
> board port? Please let me know!
What would be in it for them? There are contractors available in the
coreboot community with plenty of relevant experience, but I can't
imagine that would be fixing "our board resets when we use graphics"
in return for an instance of the hardware..
//Peter
On Sun, Oct 20, 2013 at 11:39:48AM +0530, Anthony Ross wrote:
> Hello Coreboot Team,
>
> Well Im very sorry that i forgot to mention in my previous email (Require
> help to boot coreboot with seabios' s floppy mechanism ) that the bootup of
> coreboot was initialized under qemu-kvm. I was able to perform this despite
> having no virtualization support.
> I have delayed a lot in responding and sorry for that too.Well I have begun
> a new thread and as suggested earlier by the coreboot team here is the
> output of `cbfstool build/coreboot.rom print`.
Your log did not include the seabios output. How did you compile
seabios? Make sure it is compiled for coreboot, that serial debugging
is enabled, and set the debug level to 8.
-Kevin
Hi, Andrew
coreboot + seabios work well with AMD Catalyst graphics driver on OliveHill.
If you think it was an acpi issue, maybe you can check
src/mainboard/amd/olivehill/acpi/routing.asl
On Tue, Oct 1, 2013 at 6:16 AM, Andrew DeAngelis <andrew(a)cogcomp.com> wrote:
>
> Hello all,
> I am a computer engineer from Cogent Computer Systems. I'm bringing
> up Coreboot on our new CSB1890t10/CSB1801t10 system which is based largely
> on the AMD Olivehill platform. Is there anyone out there who has experience
> with Coreboot on Kabini and may be able to answer questions about unexpected
> resets when using the AMD Catalyst graphics driver? We're booting Ubuntu
> and Windows 7 right now with a barely modified mainboard code brought over
> from Olivehill, but I'm sure there must be some things we are doing wrong,
> esp. ACPI.
>
> Also, are there any candidates who may be interested in trading our
> potentially buggy hardware system for some expert help with the board port?
> Please let me know!
>
>
> Andrew DeAngelis
> Design Engineer
> Cogent Computer Systems
> 17 Industrial Drive
> Smithfield, RI 02917
> tel: 401-349-3999
> fax: 401-349-3998
> E-mail: andrew(a)cogcomp.com
>
> --
> coreboot mailing list: coreboot(a)coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
--
Yours sincerely,
WANG Siyuan
