Hello Mario,
I am novice to Coreboot too. But. Not the first time learning experience, adds to the cause. I decided to "push" a bit Intel structures faster in time, contributing to Coreboot as Intel-er. ;-)
About Coreboot for BYT. If you'll wait a bit more, it'll come in the theatre near you. The present Coreboot from git is not adopted: [1]to FSPs; [2]to INTEL BYT boards; [3] No vbios for BYT.
[1] It is coming;
[2] if [1] completed, the [2] should be added ASAP;
[3] If [2] done, you need to add specific BYT vbios for VGA support in Coreboot snapshot you were using. I do know how to find vbios-es for Core, but not for ATOM. I've checked my Bayley Bay CRB with VLV2 stepping B0 in the lab, and here is what I am getting for VGA PCIe:
Bus 00, Device 02, Function 00 Display Controller VGA/8514 Controller
Vendor 0x8086, Device 0x0F31
So, what you need to do is to place BYT vbios (supposed to be 64K) in the directory src/.
CONFIG_VGA_ROM_RUN=y
CONFIG_VGA_BIOS=y
CONFIG_VGA_BIOS_ID="8086,0F31"
CONFIG_VGA_BIOS_FILE="./src/vbios.bin"
About "How to create a make menuconfig for the BYT FSP that not there is in the MAINBOARD VENDOR?" you need to do it by example (here is how it is done for IVB Emerald Lake 2):
[zoran@localhost emeraldlake2]$ pwd
/home/zoran/projects/coreboot/coreboot-v4.0-4709/src/mainboard/intel/emeraldlake2
[zoran@localhost emeraldlake2]$ cat Kconfig
if BOARD_INTEL_EMERALDLAKE2
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE
select SOUTHBRIDGE_INTEL_C216
select SUPERIO_SMSC_SIO1007
select BOARD_ROMSIZE_KB_8192
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select GFXUMA
#select CHROMEOS
config MAINBOARD_DIR
string
default intel/emeraldlake2
config MAINBOARD_PART_NUMBER
string
default "EMERALD LAKE 2"
config MMCONF_BASE_ADDRESS
hex
default 0xf0000000
config IRQ_SLOT_COUNT
int
default 18
config MAX_CPUS
int
default 16
config VGA_BIOS_FILE
string
default "pci8086,0166.rom"
endif # BOARD_INTEL_EMERALDLAKE2
[zoran@localhost emeraldlake2]$
I'll find out about [1] and [2].
Stay tuned,
Zoran
_______
Most of The Time you should be "intel inside" to be capable to think "out of the box".
From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Mário Wilson
Sent: Friday, October 25, 2013 12:56 AM
To: Stojsavljevic, Zoran
Cc: ron minnich; Joshua Kim; coreboot(a)coreboot.org
Subject: Re: [coreboot] Coreboot supports intel baytrail processor?
Hello Zoran,
Thanks for the reply, I checked the INTEL reference document.
Can you answer other questions, I am very new in Coreboot world!
My local Intel representative will inform to me in the documentation as I add specific network and video drivers in the coreboot image?
How to create a make menuconfig for the BYT FSP that not there is in the MAINBOARD VENDOR?
Best Regards.
Mário Wilson
Development Engineer
LESC
Computer Systems Engineer Laboratory
www.lesc.ufc.br
e-mail: mario(a)lesc.ufc.br
Campus do Pici s/n. Bloco 723, zip:60440-970, Fortaleza-Ceará-Brazil
Phone:+55 (85) 3366 9608 extension:232
"Se não puder destacar-se pelo talento, vença pelo esforço"
2013/10/22 Stojsavljevic, Zoran <zoran.stojsavljevic(a)intel.com>
Hello Mario,
Please, could you download INTEL public document: http://www.intel.com/content/dam/www/public/us/en/documents/presentation/... ?
There, on page 11 you can see what in nutshell BYT/any other FSP looks like: it is nothing more than SEC and PEI phases of EFI/UEFI BIOS (does initialization of the processor, chipset, memory - mrc). Tailored for the specific purposes. Coreboot comes on the top of this to initialize ACPI (PM), e1000 (net), VGA (video) etc. (more than outlined). And then passes control to its payload.
For BYT FSP you should go to your local INTEL Point of Contact, and request access to the restricted documents considering BYT FSP. I know that these are intensive INTEL activities to release Proof of Concept for BYT FSP with Coreboot. More I cannot reveal. All these you should ask your local INTEL representative. Policy of the company. Sorry...
Zoran
_______
Most of The Time you should be "intel inside" to be capable to think "out of the box".
From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Mário Wilson
Sent: Monday, October 21, 2013 5:13 PM
To: ron minnich
Cc: Stojsavljevic, Zoran; Joshua Kim; coreboot(a)coreboot.org
Subject: Re: [coreboot] Coreboot supports intel baytrail processor?
Good day,
I'm also looking for information on the FSP to use it in the Bay Trail platform.
Done reading the documentation and wanted to know if you can answer the following questions:
- If the FSP does initialization processor, chipset, memory and Coreboot also does this, how to integrate the binary FSP within the structure of the Coreboot?
thank you,
Mário Wilson
Development Engineer
LESC
Computer Systems Engineer Laboratory
www.lesc.ufc.br
e-mail: mario(a)lesc.ufc.br
Campus do Pici s/n. Bloco 723, zip:60440-970, Fortaleza-Ceará-Brazil
Phone:+55 (85) 3366 9608 extension:232
"Se não puder destacar-se pelo talento, vença pelo esforço"
2013/9/4 ron minnich <rminnich(a)gmail.com>
On Wed, Sep 4, 2013 at 12:53 AM, Stojsavljevic, Zoran
<zoran.stojsavljevic(a)intel.com> wrote:
> Hello Ron,
>
> Yes, Baytrail FSP Beta release is already for 4 weeks available in EDS (External Design Specifications), but you must be registered with INTEL to get Baytrail FSP and it documents. Also, as I stated before, you need OTM (Coreboot will come later as part of this picture).
I'm on the web site and hunting around and it seems, at present, to be
incomplete. Also, saying FSP is available in beta as an EDS (a spec)
makes no sense to me. Where's the FSP binary itself?
For instance, after passing through many links and looking at many
docs, I am here:
https://www-ssl.intel.com/content/www/us/en/intelligent-systems/intel-fir...
But all I can are documents, nice looking people, and links that have
nothing to do with FSP. Where do I go?
What are the redistribution rights on FSP? I assume we'll be able to
host the binary at coreboot.org as well as intel.com.
ron
--
coreboot mailing list: coreboot(a)coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Intel GmbH
Dornacher Strasse 1
85622 Feldkirchen/Muenchen, Deutschland
Sitz der Gesellschaft: Feldkirchen bei Muenchen
Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk
Registergericht: Muenchen HRB 47456
Ust.-IdNr./VAT Registration No.: DE129385895
Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052
Intel GmbH
Dornacher Strasse 1
85622 Feldkirchen/Muenchen, Deutschland
Sitz der Gesellschaft: Feldkirchen bei Muenchen
Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk
Registergericht: Muenchen HRB 47456
Ust.-IdNr./VAT Registration No.: DE129385895
Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052
Hello Zoran,
Thanks for the reply, I checked the INTEL reference document.
Can you answer other questions, I am very new in Coreboot world!
My local Intel representative will inform to me in the documentation as I
add specific network and video drivers in the coreboot image?
How to create a make menuconfig for the BYT FSP that not there is in the
MAINBOARD VENDOR?
Best Regards.
*Mário Wilson*
Development Engineer
LESC
Computer Systems Engineer Laboratory
www.lesc.ufc.br
e-mail: mario(a)lesc.ufc.br
Campus do Pici s/n. Bloco 723, zip:60440-970, Fortaleza-Ceará-Brazil
Phone:+55 (85) 3366 9608 extension:232*
*
*
*
*
*
*"Se não puder destacar-se pelo talento, vença pelo esforço"*
2013/10/22 Stojsavljevic, Zoran <zoran.stojsavljevic(a)intel.com>
> Hello Mario,
>
> Please, could you download INTEL public document:
> http://www.intel.com/content/dam/www/public/us/en/documents/presentation/...
>
> There, on page 11 you can see what in nutshell BYT/any other FSP looks
> like: it is nothing more than SEC and PEI phases of EFI/UEFI BIOS (does
> initialization of the processor, chipset, memory - mrc). Tailored for the
> specific purposes. Coreboot comes on the top of this to initialize ACPI
> (PM), e1000 (net), VGA (video) etc. (more than outlined). And then passes
> control to its payload.
>
> For BYT FSP you should go to your local INTEL Point of Contact, and
> request access to the restricted documents considering BYT FSP. I know that
> these are intensive INTEL activities to release Proof of Concept for BYT
> FSP with Coreboot. More I cannot reveal. All these you should ask your
> local INTEL representative. Policy of the company. Sorry...
>
> Zoran
> _______
> Most of The Time you should be "intel inside" to be capable to think "out
> of the box".
>
> From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org]
> On Behalf Of Mário Wilson
> Sent: Monday, October 21, 2013 5:13 PM
> To: ron minnich
> Cc: Stojsavljevic, Zoran; Joshua Kim; coreboot(a)coreboot.org
> Subject: Re: [coreboot] Coreboot supports intel baytrail processor?
>
> Good day,
>
> I'm also looking for information on the FSP to use it in the Bay Trail
> platform.
>
> Done reading the documentation and wanted to know if you can answer the
> following questions:
>
> - If the FSP does initialization processor, chipset, memory and Coreboot
> also does this, how to integrate the binary FSP within the structure of the
> Coreboot?
>
> thank you,
>
>
> Mário Wilson
>
> Development Engineer
> LESC
> Computer Systems Engineer Laboratory
> www.lesc.ufc.br
> e-mail: mario(a)lesc.ufc.br
> Campus do Pici s/n. Bloco 723, zip:60440-970, Fortaleza-Ceará-Brazil
> Phone:+55 (85) 3366 9608 extension:232
>
>
>
> "Se não puder destacar-se pelo talento, vença pelo esforço"
>
> 2013/9/4 ron minnich <rminnich(a)gmail.com>
> On Wed, Sep 4, 2013 at 12:53 AM, Stojsavljevic, Zoran
> <zoran.stojsavljevic(a)intel.com> wrote:
> > Hello Ron,
> >
> > Yes, Baytrail FSP Beta release is already for 4 weeks available in EDS
> (External Design Specifications), but you must be registered with INTEL to
> get Baytrail FSP and it documents. Also, as I stated before, you need OTM
> (Coreboot will come later as part of this picture).
> I'm on the web site and hunting around and it seems, at present, to be
> incomplete. Also, saying FSP is available in beta as an EDS (a spec)
> makes no sense to me. Where's the FSP binary itself?
>
> For instance, after passing through many links and looking at many
> docs, I am here:
>
> https://www-ssl.intel.com/content/www/us/en/intelligent-systems/intel-fir...
>
> But all I can are documents, nice looking people, and links that have
> nothing to do with FSP. Where do I go?
>
> What are the redistribution rights on FSP? I assume we'll be able to
> host the binary at coreboot.org as well as intel.com.
>
> ron
>
> --
> coreboot mailing list: coreboot(a)coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
> Intel GmbH
> Dornacher Strasse 1
> 85622 Feldkirchen/Muenchen, Deutschland
> Sitz der Gesellschaft: Feldkirchen bei Muenchen
> Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk
> Registergericht: Muenchen HRB 47456
> Ust.-IdNr./VAT Registration No.: DE129385895
> Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052
>
>
Am Mittwoch, den 23.10.2013, 19:30 +0530 schrieb Anthony Ross:
> I have also successfully built & booted the Coreboot Pkg IA32
> encapsulating it in the coreboot.rom and booting it under QEMU-kvm
> except for the X64 architectures I faced certain toolchain errors.
I think I fixed the toolchain error on X64 (now that I finally managed
to reproduce it) and pushed it on my github repo.
You'll need to rebuild the BaseTools:
$ cd BaseTools/Source/C
$ make
Afterwards, corebootPkg should build with the GCC46 toolchain (I used
GCC47) for X64, too.
Patrick
Hello
There has been no response to my thread [Help required to initialize
coreboot as Seabios (floppy mechanism for DUET) payload] since a long
time.I have eagerly waited but no solutions have turned up.
If Im mistaken in any way or the other please let know.
Regards....
Neo.
Hello again coreboot folks,
I am trying to get the subject working with coreboot, and I can't seem
to get any display, either with SeaBIOS or Grub2 payloads (although
Grub2 does switch backlight on). I have output from USB debug, but the
only obvious problem is not being able to write the MRC cache (which
also happens on Lumpy and doesn't stop it from booting). Additionally
there isn't any debug output from the payloads. How do I enable same,
and have you any other thoughts as to how to move things forward? Please
see attached.
Kind Regards,
John.
Hello Mario,
Please, could you download INTEL public document: http://www.intel.com/content/dam/www/public/us/en/documents/presentation/... ?
There, on page 11 you can see what in nutshell BYT/any other FSP looks like: it is nothing more than SEC and PEI phases of EFI/UEFI BIOS (does initialization of the processor, chipset, memory - mrc). Tailored for the specific purposes. Coreboot comes on the top of this to initialize ACPI (PM), e1000 (net), VGA (video) etc. (more than outlined). And then passes control to its payload.
For BYT FSP you should go to your local INTEL Point of Contact, and request access to the restricted documents considering BYT FSP. I know that these are intensive INTEL activities to release Proof of Concept for BYT FSP with Coreboot. More I cannot reveal. All these you should ask your local INTEL representative. Policy of the company. Sorry...
Zoran
_______
Most of The Time you should be "intel inside" to be capable to think "out of the box".
From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Mário Wilson
Sent: Monday, October 21, 2013 5:13 PM
To: ron minnich
Cc: Stojsavljevic, Zoran; Joshua Kim; coreboot(a)coreboot.org
Subject: Re: [coreboot] Coreboot supports intel baytrail processor?
Good day,
I'm also looking for information on the FSP to use it in the Bay Trail platform.
Done reading the documentation and wanted to know if you can answer the following questions:
- If the FSP does initialization processor, chipset, memory and Coreboot also does this, how to integrate the binary FSP within the structure of the Coreboot?
thank you,
Mário Wilson
Development Engineer
LESC
Computer Systems Engineer Laboratory
www.lesc.ufc.br
e-mail: mario(a)lesc.ufc.br
Campus do Pici s/n. Bloco 723, zip:60440-970, Fortaleza-Ceará-Brazil
Phone:+55 (85) 3366 9608 extension:232
"Se não puder destacar-se pelo talento, vença pelo esforço"
2013/9/4 ron minnich <rminnich(a)gmail.com>
On Wed, Sep 4, 2013 at 12:53 AM, Stojsavljevic, Zoran
<zoran.stojsavljevic(a)intel.com> wrote:
> Hello Ron,
>
> Yes, Baytrail FSP Beta release is already for 4 weeks available in EDS (External Design Specifications), but you must be registered with INTEL to get Baytrail FSP and it documents. Also, as I stated before, you need OTM (Coreboot will come later as part of this picture).
I'm on the web site and hunting around and it seems, at present, to be
incomplete. Also, saying FSP is available in beta as an EDS (a spec)
makes no sense to me. Where's the FSP binary itself?
For instance, after passing through many links and looking at many
docs, I am here:
https://www-ssl.intel.com/content/www/us/en/intelligent-systems/intel-fir...
But all I can are documents, nice looking people, and links that have
nothing to do with FSP. Where do I go?
What are the redistribution rights on FSP? I assume we'll be able to
host the binary at coreboot.org as well as intel.com.
ron
--
coreboot mailing list: coreboot(a)coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Intel GmbH
Dornacher Strasse 1
85622 Feldkirchen/Muenchen, Deutschland
Sitz der Gesellschaft: Feldkirchen bei Muenchen
Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk
Registergericht: Muenchen HRB 47456
Ust.-IdNr./VAT Registration No.: DE129385895
Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052
Hello Laurent,
I can give you my own tips for doing what you have asked. Few of them...
I don't understand why you need to modify BIOS? Instead, you can keep your SW on the USB mass storage. And go from there. The another approach is to boot to DOS 6.2 on USB and perform tests from there. DOS is a linear OS, does not have MMU engaged, does not have HW multithreading (my best understanding).
If you will use INTEL CPUs, you can go with FSP approach as well, and put Coreboot on the top of it, using your SW as Coreboot payload. One of the viable solutions, but you need also to have Management Engine (ME) SW added there (in single, or dual spi design, ME placed in spi0, BIOS in spi1).
If you would like to boot with less than 1 ms, you need to do shallow warm restart, so you need just to be able to free HW resources (since I think you'll use ONLY one HW thread, one core sans hyperthreading, all others while in BIOS are disabled), flush cashes, do memory garbage collection (if any?) and jump to the beginning of your test SW. Not sure while performing shallow warm restart if you need to do something with System Management Mode (SMM) and it structures. Topic to be investigated.
Please, do notice that BIOS and FSP, both do for you PCIe enumeration. For the boards, I'll advise you for INTEL to use IVB and later (HSW) based. This are the primary CPUs for INTEL to keep supporting 'em for long time (at least for 7 years from date of public release, 2012 for IVB, 2013 for HSW).
Now, specifically to your questions:
[1] YES, it is possible to modify BIOS to disable POST, and do certain configuration, you need to use Open Source (with incorporated binaries doing SEC and PEI) EDK2 package (UEFI BIOS) which has options for various configurations;
[2] YES;
[3 - 4] I don't know. I am using INTEL's CRBs, these are unlocked always. Not sure about commercial boards, and which are the best for such experiments.
Zoran
_______
Most of The Time you should be "intel inside" to be capable to think "out of the box".
-----Original Message-----
From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Laurent Lesage
Sent: Monday, October 21, 2013 6:15 PM
To: coreboot(a)coreboot.org
Subject: [coreboot] software hardening research project - request for advices to start
Hello all,
After having searched around me for some answers about BIOS and PC board "hacking", I want to ask directly to the "core" developers.
In short, I would like to run a test software without OS (say, like
"memtest") on a standard mainboard. This software will have to access a PCIe board, and may be some components of the mainboard. So we expect the software will not exceed a few hundred kilobytes. During this experiment, we want that a reset of the CPU does not lead to a reboot, but just restart our software immediately (only a cold start would redo all the usual "POST"), skipping all the usual hardware setups.
"immediately" means in one ms or so (the less, the best). More details about what I'm working on at the end of this post. To achieve this on standard mainboards, being able to modify the BIOS seems the only way.
My questions /request for comments and advices :
1.Is it feasible to modifiy the BIOS for such a reset (without POST and very quickly).
2.Is it possible to put our software on the BIOS chip, so that we do not need to access hard disk, and so that the code is protected (Read only) during the runs.
3. is it possible to flash the BIOS without locking the board, i.e., is it always possible to recover a working bios if flashing process failed, or experimental BIOS is not working as expected. In that sense, are there boards to avoid?
4.knowing we will have to access a PCIex8/16 extension board, and knowing the points 1, 2 and 3, which board would you advice to use? For example, I saw this one ( http://www.coreboot.org/ASUS_F2A85-M#Hardware_info ) for which PCIe support seems OK. Of course, the board must be easy to buy, so older ones are not a good choice if they are sold out.
I also saw that some boards offers bigger space to flash BIOS. Again, this would be a good criterion for our needs, if it is possible to flash our software in it using the remaining space.
What I wish is to start with a mainboard that has more than 90% of probability to meet our needs.
Some more details about the project.
I'm research engineer in UCLouvain (Belgium). Our topic is "software hardening for mission critical embedded software". Quickly said, we want to test our approach with COTS hardware (usually, testing is done on FPGA systems, or specific hardened hardware systems). So, we want to use a PC board to run a very specific software on it (that could be the "payload" coreboot can start). We intend to make this in two stages :
-first tests on a "naked" machine i.e. without OS. Our software is the payload. That is the subject of this post.
-later, run a software hardened version of Minix (I saw minix is not yet usable as such but if we come to this end, we will have some knowledge to go this way).
The CPU of our "naked machine" will at the end be irradiated to inject error in it, and see if it detects errors and stays working despite transient faults.
Regards
Laurent
board with special memory and FPGA on it
--
coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Intel GmbH
Dornacher Strasse 1
85622 Feldkirchen/Muenchen, Deutschland
Sitz der Gesellschaft: Feldkirchen bei Muenchen
Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk
Registergericht: Muenchen HRB 47456
Ust.-IdNr./VAT Registration No.: DE129385895
Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052
Dear coreboot folks,
adding reviewers in Gerrit, I noticed that for some users (like Björn
and Florian) only numbers and no email is shown. It works fine with
Rudolf for example. I’d blame the upgrade to Gerrit 2.7, but have no
idea.
Thanks,
Paul
Am 17.10.2013 11:13, schrieb Stojsavljevic, Zoran:
> You wrote: "do fresh Windows installs from BIOS (UEFI+CSM is enough),
> then use these for your coreboot experiments"... Do I need to change
> some CMOS option (UEFI Compatibility Support Module) in EFI BIOS
> installed on my another IVB CRB and adapt prior installing win7 and
> 8.1 32bit?
Sorry for the late answer. I wouldn't expect the need for any special
configuration except for enabling CSM (and booting the Windows installer
through it).
Regards,
Patrick
Good day,
I'm also looking for information on the FSP to use it in the Bay Trail
platform.
Done reading the documentation and wanted to know if you can answer the
following questions:
- If the FSP does initialization processor, chipset, memory and Coreboot
also does this, how to integrate the binary FSP within the structure of the
Coreboot?
thank you,
*Mário Wilson*
Development Engineer
LESC
Computer Systems Engineer Laboratory
www.lesc.ufc.br
e-mail: mario(a)lesc.ufc.br
Campus do Pici s/n. Bloco 723, zip:60440-970, Fortaleza-Ceará-Brazil
Phone:+55 (85) 3366 9608 extension:232*
*
*
*
*
*
*"Se não puder destacar-se pelo talento, vença pelo esforço"*
2013/9/4 ron minnich <rminnich(a)gmail.com>
> On Wed, Sep 4, 2013 at 12:53 AM, Stojsavljevic, Zoran
> <zoran.stojsavljevic(a)intel.com> wrote:
> > Hello Ron,
> >
> > Yes, Baytrail FSP Beta release is already for 4 weeks available in EDS
> (External Design Specifications), but you must be registered with INTEL to
> get Baytrail FSP and it documents. Also, as I stated before, you need OTM
> (Coreboot will come later as part of this picture).
>
> I'm on the web site and hunting around and it seems, at present, to be
> incomplete. Also, saying FSP is available in beta as an EDS (a spec)
> makes no sense to me. Where's the FSP binary itself?
>
> For instance, after passing through many links and looking at many
> docs, I am here:
>
> https://www-ssl.intel.com/content/www/us/en/intelligent-systems/intel-fir...
>
> But all I can are documents, nice looking people, and links that have
> nothing to do with FSP. Where do I go?
>
> What are the redistribution rights on FSP? I assume we'll be able to
> host the binary at coreboot.org as well as intel.com.
>
> ron
>
> --
> coreboot mailing list: coreboot(a)coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
