the following patch was just integrated into master:
commit 70f39871a92c065ee52be9d25aaf7a3e874fc1a3
Author: Olivier Langlois <olivier(a)olivierlanglois.net>
Date: Fri Jan 25 00:49:46 2013 -0500
inteltool: Add support for Atom N455 (0x106c0) in CPU MSRs dump
reference for Atom MSRs are from
Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 3C: System Programming Guide, Part 3
Order Number 326019, January 2013, Table 35-4, 35-5
Has been successfully tested on the targeted cpu.
Change-Id: If94279caeab27121c63ec43c258dc962c167ad51
Signed-off-by: Olivier Langlois <olivier(a)olivierlanglois.net>
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2192
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Build-Tested: build bot (Jenkins) at Fri Jan 25 14:21:53 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Jan 25 20:09:24 2013, giving +2
See http://review.coreboot.org/2192 for details.
-gerrit
the following patch was just integrated into master:
commit 658e4d3ea900c9925d1e5dbbc99f08a9a6fc0323
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Thu Jan 17 12:29:51 2013 -0800
libpayload: use $(DOTCONFIG) instead of .config
When overriding the DOTCONFIG variable, make install
will fail in libpayload.
Change-Id: I332be3a4ca2620a32a6f5fbe683e6c71f0d6a9e9
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: http://review.coreboot.org/2178
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Jan 25 20:06:45 2013, giving +2
See http://review.coreboot.org/2178 for details.
-gerrit
the following patch was just integrated into master:
commit 336b8b171289ef80d465e0726eb7674cafe78a31
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Wed Jan 23 18:10:04 2013 +0100
AGESA: Kconfig: Drop useless depends statement
`depends on FOO` in
if FOO
... depends on FOO
endif
is useless.
Introduced in
commit 4b508341bcf11687be98d20f8178b5cc542a0842
Author: efdesign98 <efdesign98(a)gmail.com>
Date: Wed Jul 13 17:16:13 2011 -0700
Add AMD Family 10 support to cpu folder
and probably copied later on in the following commit.
commit d3e990c6e5124f30b394f5dbd4902ea8bf341b07
Author: Kerry Sheh <shekairui(a)gmail.com>
Date: Tue Feb 7 20:31:35 2012 +0800
AGESA F15: AGESA family15 model 00-0fh cpu wrapper
Change-Id: I67cf231e3047a07cb6f0eeb5f77be368674a0603
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2186
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Hengelein <ilendir(a)gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/2186 for details.
-gerrit
Aladyshev Konstantin (kostr(a)list.ru) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2193
-gerrit
commit d9288f5757e3f1ab5d4b4e85ad8171502d137f87
Author: Konstantin Aladyshev <aladyshev(a)nicevt.ru>
Date: Fri Jan 25 19:20:51 2013 +0400
Supermicro H8QGI: Substract 1 from MMCONF range limit
MMCONF space is defined by two config parameters:
MMCONF_BASE_ADDRESS (0xF800 0000)
MMCONF_BUS_NUMBER (64)
Coreboot allocates 1MB per bus, so MMCONF limit should be:
0xF800 0000 + 64*(0x0010 0000) - 1 = 0xFBFF FFFF
Current code does not have (-1) component, this makes MMCONF limit
equal 0xFC00 FFFF. Add (-1) to correct this issue.
No functionality change has been experienced. The five times
slower RAM speed compared to the proprietary vendor BIOS still
remains.
Change-Id: I2c6494c28bb8d36e54ceb2aa7d8d965b0103cbe9
Signed-off-by: Konstantin Aladyshev <aladyshev(a)nicevt.ru>
---
src/mainboard/supermicro/h8qgi/agesawrapper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c
index 9720bed..517e136 100644
--- a/src/mainboard/supermicro/h8qgi/agesawrapper.c
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c
@@ -147,7 +147,7 @@ static UINT32 agesawrapper_amdinitcpuio(VOID)
* coreboot not implemente the range by range setting yet.
*/
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC);
- PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000);//1MB each bus
+ PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;//1MB each bus
PciData = (PciData >> 8) & 0xFFFFFF00;
PciData |= 0x80; //NP
PciData |= sblink << 4;
Dear coreboot Gerrit folks,
I did `git checkout` of Konstantin’s patch [1] and improved the commit
message. Wanting to push it, I get the following error.
$ git push
Counting objects: 49, done.
Delta compression using up to 2 threads.
Compressing objects: 100% (30/30), done.
Writing objects: 100% (30/30), 12.81 KiB, done.
Total 30 (delta 21), reused 0 (delta 0)
remote: Resolving deltas: 100% (21/21)
remote: Processing changes: refs: 1, done
To ssh://paulepanter@review.coreboot.org:29418/coreboot
! [remote rejected] HEAD -> refs/for/master (not Signed-off-by author/committer/uploader)
error: failed to push some refs to 'ssh://paulepanter@review.coreboot.org:29418/coreboot'
$ git show
commit 76852159e877b6f88a9da8378691ebae11c88e3d
Author: Konstantin Aladyshev <aladyshev(a)nicevt.ru>
Date: Fri Jan 25 19:20:51 2013 +0400
Supermicro H8QGI: Substract 1 from MMCONF range limit
MMCONF space is defined by two config parameters:
MMCONF_BASE_ADDRESS (0xF800 0000)
MMCONF_BUS_NUMBER (64)
coreboot allocates 1 MB per bus, so MMCONF limit should be:
0xF800 0000 + 64*(0x0010 0000) - 1 = 0xFBFF FFFF
Current code does not have (-1) component, this makes MMCONF limit
equal 0xFC00 FFFF. Add (-1) to correct this issue.
No functionality change has been experienced. The five times
slower RAM speed compared to the proprietary vendor BIOS still
remains.
Change-Id: I2c6494c28bb8d36e54ceb2aa7d8d965b0103cbe9
Signed-off-by: Konstantin Aladyshev <aladyshev(a)nicevt.ru>
Signed-off-by: Aladyshev Konstantin <aladyshev(a)nicevt.ru>
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c
index 9720bed..517e136 100644
--- a/src/mainboard/supermicro/h8qgi/agesawrapper.c
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c
@@ -147,7 +147,7 @@ static UINT32 agesawrapper_amdinitcpuio(VOID)
* coreboot not implemente the range by range setting yet.
*/
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC);
- PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000);//1MB each bus
+ PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;//1MB each bus
PciData = (PciData >> 8) & 0xFFFFFF00;
PciData |= 0x80; //NP
PciData |= sblink << 4;
Adding my Signed-off-by line did not help neither adding Konstantin’s
one with his first and family name reversed.
I guess it might be related to the switch of first and last name I asked
him to do.
Thanks,
Paul
[1] http://review.coreboot.org/#/c/2193/