Hi everyone,
My name is Nick Bowes and I'm looking to create a small (got to start
somewhere) Foss-only computer build and supply business. To make that viable,
I need a free bios implementation for one or two new mobos, and coreboot seems
to hold the most promise. I'm interested in doing this in the hope that I can
help the foss community get away from the emerging and likely pervasive UEFI
stupidness thats coming. As you probably know better then I do, creating
alternatives to the things that cause us all problems is the only way to
truely solve them.
Having heard recently that Google released coreboot updates for both Sandy
Bridge and Ivy Bridge chipsets, I thought now would be a good time to ask this
mailing list a few questions about the viability of funding some development.
As a future small distributor of foss-only computers and likely a one man band
to start with, I would need to keep things very simple. That means creating a
product line (if you can call it that) of perhaps only 3-5 different
desktops/laptops in total. Idealy I'd like to offer a range of 3 itx desktops,
Ivy Bridge i3 i5 i7, or, Trinity A6 A8 A10, and one or two laptops, one
budget, one highend.
So, if you don't mind, and this is the right place(if it isn't, please point
me in the right direction) I'd like to ask you all...
1. What do you all think the requirements will be for replacing UEFI on
future mobos. Will it likely be a case of switching out the bios chip or just
flashing it?
2. What % of flashes resulted in bricked mobos? Do most new boards come
with a backup chip which can restore life after a failure?
3. Can anyone reccomend a possible target ivy bridge or Trinity itx mobo
for coreboot development? Perhaps one that's already being worked on?
4. If we can identify a good itx mobo for the desktop line-up, would
someone here be able to asses how much time a fairly full featured and
reliable implementation of coreboot would take to develop?
note: to me "fairly full featured would be to have all the
fundamentals up and avaliable for the OS to pick up, such as pci-e usb 3.0,
hdmi, sata 3, wifi, and working reliably.
5. Is there any special requirement for getting amd/nvidia gfx cards
working with coreboot?
6. Which hardware have you found to be the simplist to fully implement
coreboot on, and which hardware (if any) should be considered a no go?
7. What type of computer would most on this list be interested to develop
coreboot for. As in, if you were going to buy a desktop or laptop today, or
in the near future, what combination of hardware would you go for?
8. What do you think about the viability of a kickstarter campaign to raise
development funds. Has anyone tried this yet?
I would truely love to distribute computers which run entirely on free
software. Unfortunately, I'm no developer so If funding some development is
the only way I can achieve this, I will find a way to do it.
I look forward to any insights you provide.
Thanks
Nick
2
2
Re: [coreboot] amd/persimmon does not scan behind bridge on sb800 southbridge
by shekairui 05 Jun '12
by shekairui 05 Jun '12
05 Jun '12
On 06/05/2012 03:42 AM, Andy Sharp wrote:
> Howdy,
>
> I've got an amd/persimmon board, and when I build the coreboot for it
> from the tree, it only finds the PCIe devices directly attached to the
> CPU, but not any of the ones hanging off the sb800 southbridge. Anyone
> have any clues for me?
I suggest to check the devicetree.cb first.
The sb800 PCIe ports were set off by default.
--snip--
device pci 15.0 off end # PCIe PortA
device pci 15.1 off end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
--snip--
Kerry
Thanks
> Thanks!
>
> coreboot console log:
>
>
>
> coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
> starting...
> POST: 0x34
> BSP Family_Model: 00500f20
> cpu_init_detectedx = 00000000
> POST: 0x35
> agesawrapper_amdinitmmio passed.
> POST: 0x37
> agesawrapper_amdinitreset passed.
> POST: 0x39
> agesawrapper_amdinitearly POST: 0x34
> BSP Family_Model: 00500f20
> cpu_init_detectedx = 00000001
> POST: 0x35
> agesawrapper_amdinitmmio passed.
> POST: 0x37
> agesawrapper_amdinitreset passed.
> POST: 0x39
> agesawrapper_amdinitearly passed.
> SLP_TYP type was 0
> POST: 0x40
> agesawrapper_amdinitpost
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
> SLP_TYP type was 0
> error level: 4
> POST: 0x42
> agesawrapper_amdinitenv SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> passed.
> POST: 0x43
> POST: 0x44
> POST: 0x50
> Loading image.
> CBFS: Looking for 'fallback/coreboot_ram'
> CBFS: found.
> CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes),
> entry @ 0x200000
> Jumping to image.
> POST: 0x80
> POST: 0x39
> coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
> booting...
> POST: 0x40
> Enumerating buses...
> Show all devs...Before device enumeration.
> Root Device: enabled 1
> APIC_CLUSTER: 0: enabled 1
> APIC: 00: enabled 1
> PCI_DOMAIN: 0000: enabled 1
> PCI: 00:00.0: enabled 1
> PCI: 00:01.0: enabled 1
> PCI: 00:01.1: enabled 1
> PCI: 00:04.0: enabled 1
> PCI: 00:05.0: enabled 0
> PCI: 00:06.0: enabled 0
> PCI: 00:07.0: enabled 0
> PCI: 00:08.0: enabled 0
> PCI: 00:11.0: enabled 1
> PCI: 00:12.0: enabled 1
> PCI: 00:12.1: enabled 1
> PCI: 00:12.2: enabled 1
> PCI: 00:13.0: enabled 1
> PCI: 00:13.1: enabled 1
> PCI: 00:13.2: enabled 1
> PCI: 00:14.0: enabled 1
> I2C: 00:50: enabled 1
> I2C: 00:51: enabled 1
> PCI: 00:14.1: enabled 1
> PCI: 00:14.2: enabled 1
> PCI: 00:14.3: enabled 1
> PNP: 004e.0: enabled 0
> PNP: 004e.3: enabled 0
> PNP: 004e.4: enabled 0
> PNP: 004e.5: enabled 1
> PNP: 004e.6: enabled 0
> PNP: 004e.a: enabled 0
> PNP: 004e.10: enabled 1
> PNP: 004e.11: enabled 0
> PCI: 00:14.4: enabled 1
> PCI: 00:14.5: enabled 1
> PCI: 00:15.0: enabled 0
> PCI: 00:15.1: enabled 0
> PCI: 00:15.2: enabled 0
> PCI: 00:15.3: enabled 0
> PCI: 00:16.0: enabled 0
> PCI: 00:16.2: enabled 0
> PCI: 00:18.0: enabled 1
> PCI: 00:18.1: enabled 1
> PCI: 00:18.2: enabled 1
> PCI: 00:18.3: enabled 1
> PCI: 00:18.4: enabled 1
> PCI: 00:18.5: enabled 1
> PCI: 00:18.6: enabled 1
> PCI: 00:18.7: enabled 1
> Compare with tree...
> Root Device: enabled 1
> APIC_CLUSTER: 0: enabled 1
> APIC: 00: enabled 1
> PCI_DOMAIN: 0000: enabled 1
> PCI: 00:00.0: enabled 1
> PCI: 00:01.0: enabled 1
> PCI: 00:01.1: enabled 1
> PCI: 00:04.0: enabled 1
> PCI: 00:05.0: enabled 0
> PCI: 00:06.0: enabled 0
> PCI: 00:07.0: enabled 0
> PCI: 00:08.0: enabled 0
> PCI: 00:11.0: enabled 1
> PCI: 00:12.0: enabled 1
> PCI: 00:12.1: enabled 1
> PCI: 00:12.2: enabled 1
> PCI: 00:13.0: enabled 1
> PCI: 00:13.1: enabled 1
> PCI: 00:13.2: enabled 1
> PCI: 00:14.0: enabled 1
> I2C: 00:50: enabled 1
> I2C: 00:51: enabled 1
> PCI: 00:14.1: enabled 1
> PCI: 00:14.2: enabled 1
> PCI: 00:14.3: enabled 1
> PNP: 004e.0: enabled 0
> PNP: 004e.3: enabled 0
> PNP: 004e.4: enabled 0
> PNP: 004e.5: enabled 1
> PNP: 004e.6: enabled 0
> PNP: 004e.a: enabled 0
> PNP: 004e.10: enabled 1
> PNP: 004e.11: enabled 0
> PCI: 00:14.4: enabled 1
> PCI: 00:14.5: enabled 1
> PCI: 00:15.0: enabled 0
> PCI: 00:15.1: enabled 0
> PCI: 00:15.2: enabled 0
> PCI: 00:15.3: enabled 0
> PCI: 00:16.0: enabled 0
> PCI: 00:16.2: enabled 0
> PCI: 00:18.0: enabled 1
> PCI: 00:18.1: enabled 1
> PCI: 00:18.2: enabled 1
> PCI: 00:18.3: enabled 1
> PCI: 00:18.4: enabled 1
> PCI: 00:18.5: enabled 1
> PCI: 00:18.6: enabled 1
> PCI: 00:18.7: enabled 1
> Mainboard Persimmon Enable.
> SLP_TYP type was 0
> persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000
> persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = 0x00000000
> persimmon_enable: uma size 0x18000000, memory start 0x67000000
> scan_static_bus for Root Device
> APIC_CLUSTER: 0 enabled
> PCI_DOMAIN: 0000 enabled
> APIC_CLUSTER: 0 scanning...
> AP siblings=1
> CPU: APIC: 00 enabled
> CPU: APIC: 01 enabled
> PCI_DOMAIN: 0000 scanning...
> PCI: pci_scan_bus for bus 00
> POST: 0x24
> PCI: 00:00.0 [1022/1510] ops
> PCI: 00:00.0 [1022/1510] enabled
> PCI: 00:01.0 [1002/9804] enabled
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> PCI: 00:04.0 subordinate bus PCI Express
> PCI: 00:04.0 [1022/1512] enabled
> sb800_enable() SLP_TYP type was 0
> PCI: 00:11.0 [1002/4393] ops
> PCI: 00:11.0 [1002/4393] enabled
> sb800_enable() PCI: 00:12.0 [1002/4397] ops
> PCI: 00:12.0 [1002/4397] enabled
> sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling it.
> sb800_enable() PCI: 00:12.2 [1002/4396] ops
> PCI: 00:12.2 [1002/4396] enabled
> sb800_enable() PCI: 00:13.0 [1002/4397] ops
> PCI: 00:13.0 [1002/4397] enabled
> sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling it.
> sb800_enable() PCI: 00:13.2 [1002/4396] ops
> PCI: 00:13.2 [1002/4396] enabled
> sb800_enable() sm_init().
> IOAPIC: Clearing IOAPIC at 0xfec00000
> IOAPIC: 23 interrupts
> IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
> IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
> IOAPIC: Initializing IOAPIC at 0xfec00000
> IOAPIC: Bootstrap Processor Local APIC = 0x00
> IOAPIC: ID = 0x02
> IOAPIC: 23 interrupts
> IOAPIC: Enabling interrupts on FSB
> IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
> IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
> IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
> PCI: 00:14.0 [1002/4385] enabled
> sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it.
> sb800_enable() hda enabled
> PCI: 00:14.2 [1002/4383] ops
> PCI: 00:14.2 [1002/4383] enabled
> sb800_enable() PCI: 00:14.3 [1002/439d] bus ops
> PCI: 00:14.3 [1002/439d] enabled
> sb800_enable() PCI: 00:14.4 [1002/4384] bus ops
> PCI: 00:14.4 [1002/4384] enabled
> sb800_enable() PCI: 00:14.5 [1002/4399] ops
> PCI: 00:14.5 [1002/4399] enabled
> sb800_enable() sb800_enable() sb800_enable() sb800_enable()
> sb800_enable() sb800_enable() PCI: 00:18.0 [1022/1700] enabled
> PCI: 00:18.1 [1022/1701] enabled
> PCI: 00:18.2 [1022/1702] enabled
> PCI: 00:18.3 [1022/1703] enabled
> PCI: 00:18.4 [1022/1704] enabled
> PCI: 00:18.5 [1022/1718] enabled
> PCI: 00:18.6 [1022/1716] enabled
> PCI: 00:18.7 [1022/1719] enabled
> POST: 0x25
> PCI: Left over static devices:
> PCI: 00:01.1
> PCI: Check your devicetree.cb.
> do_pci_scan_bridge for PCI: 00:04.0
> PCI: pci_scan_bus for bus 01
> POST: 0x24
> PCI: 01:00.0 [10ec/8168] enabled
> POST: 0x25
> PCI: pci_scan_bus returning with max=001
> POST: 0x55
> Capability: type 0x01 @ 0x40
> Capability: type 0x05 @ 0x50
> Capability: type 0x10 @ 0x70
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> do_pci_scan_bridge returns max 1
> scan_static_bus for PCI: 00:14.3
> PNP: 004e.0 disabled
> PNP: 004e.3 disabled
> PNP: 004e.4 disabled
> PNP: 004e.5 enabled
> PNP: 004e.6 disabled
> PNP: 004e.a disabled
> PNP: 004e.10 enabled
> PNP: 004e.11 disabled
> scan_static_bus for PCI: 00:14.3 done
> do_pci_scan_bridge for PCI: 00:14.4
> PCI: pci_scan_bus for bus 02
> POST: 0x24
> POST: 0x25
> PCI: pci_scan_bus returning with max=002
> POST: 0x55
> do_pci_scan_bridge returns max 2
> PCI: pci_scan_bus returning with max=002
> POST: 0x55
> scan_static_bus for Root Device done
> done
> POST: 0x66
> Setting up VGA for PCI: 00:01.0
> Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
> Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
> Allocating resources...
> Reading resources...
> Root Device read_resources bus 0 link: 0
>
> Fam14h - cpu_bus_read_resources.
> APIC_CLUSTER: 0 read_resources bus 0 link: 0
> APIC: 00 missing read_resources
> APIC: 01 missing read_resources
> APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
>
> Fam14h - domain_read_resources.
> PCI_DOMAIN: 0000 read_resources bus 0 link: 0
>
> Fam14h - read_resources.
> PCI: 00:04.0 read_resources bus 1 link: 0
> PCI: 00:04.0 read_resources bus 1 link: 0 done
> PCI: 00:14.0 read_resources bus 0 link: 0
> I2C: 00:50 missing read_resources
> I2C: 00:51 missing read_resources
> PCI: 00:14.0 read_resources bus 0 link: 0 done
> SB800 - Lpc.c - lpc_read_resources - Start.
> SB800 - Lpc.c - lpc_read_resources - End.
> PCI: 00:14.3 read_resources bus 0 link: 0
> PCI: 00:14.3 read_resources bus 0 link: 0 done
> PCI: 00:14.4 read_resources bus 2 link: 0
> PCI: 00:14.4 read_resources bus 2 link: 0 done
> PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
> Root Device read_resources bus 0 link: 0 done
> Done reading resources.
> Show resources in subtree (Root Device)...After reading.
> Root Device child on link 0 APIC_CLUSTER: 0
> APIC_CLUSTER: 0 child on link 0 APIC: 00
> APIC_CLUSTER: 0 resource base f8000000 size 1000000 align 0 gran 0
> limit 0 flags f0000200 index c0010058
> APIC: 00
> APIC: 01
> PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
> PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff
> flags 40040100 index 10000000
> PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff
> flags 40040200 index 10000100
> PCI: 00:00.0
> PCI: 00:01.0
> PCI: 00:01.0 resource base 0 size 10000000 align 28 gran 28 limit
> ffffffff flags 1200 index 10
> PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff
> flags 100 index 14
> PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit
> ffffffff flags 200 index 18
> PCI: 00:04.0 child on link 0 PCI: 01:00.0
> PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff
> flags 80102 index 1c
> PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit
> ffffffffffffffff flags 81202 index 24
> PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff
> flags 80202 index 20
> PCI: 01:00.0
> PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff
> flags 100 index 10
> PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit
> ffffffffffffffff flags 1201 index 18
> PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit
> ffffffffffffffff flags 1201 index 20
> PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit
> ffffffff flags 2200 index 30
> PCI: 00:05.0
> PCI: 00:06.0
> PCI: 00:07.0
> PCI: 00:08.0
> PCI: 00:11.0
> PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags
> 100 index 10
> PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags
> 100 index 14
> PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags
> 100 index 18
> PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags
> 100 index 1c
> PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags
> 100 index 20
> PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit
> ffffffff flags 200 index 24
> PCI: 00:12.0
> PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit
> ffffffff flags 200 index 10
> PCI: 00:12.1
> PCI: 00:12.2
> PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff
> flags 200 index 10
> PCI: 00:13.0
> PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit
> ffffffff flags 200 index 10
> PCI: 00:13.1
> PCI: 00:13.2
> PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff
> flags 200 index 10
> PCI: 00:14.0 child on link 0 I2C: 00:50
> I2C: 00:50
> I2C: 00:51
> PCI: 00:14.1
> PCI: 00:14.2
> PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit
> ffffffffffffffff flags 201 index 10
> PCI: 00:14.3 child on link 0 PNP: 004e.0
> PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffff
> flags 200 index a0
> PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags
> c0040100 index 10000000
> PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit
> 0 flags c0040200 index 10000100
> PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0
> flags c0000200 index 3
> PNP: 004e.0
> PNP: 004e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags
> c0000100 index 60
> PNP: 004e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags
> c0000400 index 70
> PNP: 004e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags
> c0000800 index 74
> PNP: 004e.3
> PNP: 004e.3 resource base 0 size 8 align 3 gran 3 limit 7ff flags
> 100 index 60
> PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
> index 70
> PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
> index 74
> PNP: 004e.4
> PNP: 004e.4 resource base 0 size 8 align 3 gran 3 limit fff flags
> 100 index 60
> PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
> index 70
> PNP: 004e.5
> PNP: 004e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff
> flags c0000100 index 60
> PNP: 004e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags
> c0000100 index 62
> PNP: 004e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags
> c0000400 index 70
> PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
> index 72
> PNP: 004e.6
> PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
> index 70
> PNP: 004e.a
> PNP: 004e.10
> PNP: 004e.10 resource base 3f8 size 8 align 3 gran 3 limit 7ff
> flags c0000100 index 60
> PNP: 004e.10 resource base 4 size 1 align 0 gran 0 limit 0 flags
> c0000400 index 70
> PNP: 004e.11
> PNP: 004e.11 resource base 2f8 size 8 align 3 gran 3 limit 7ff
> flags c0000100 index 60
> PNP: 004e.11 resource base 3 size 1 align 0 gran 0 limit 0 flags
> c0000400 index 70
> PCI: 00:14.4
> PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff
> flags 80102 index 1c
> PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff
> flags 81202 index 24
> PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff
> flags 80202 index 20
> PCI: 00:14.5
> PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit
> ffffffff flags 200 index 10
> PCI: 00:15.0
> PCI: 00:15.1
> PCI: 00:15.2
> PCI: 00:15.3
> PCI: 00:16.0
> PCI: 00:16.2
> PCI: 00:18.0
> PCI: 00:18.1
> PCI: 00:18.2
> PCI: 00:18.3
> PCI: 00:18.4
> PCI: 00:18.5
> PCI: 00:18.6
> PCI: 00:18.7
> PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0
> limit: ffff
> PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
> limit: ffffffff
> PCI: 01:00.0 10 * [0x0 - 0xff] io
> PCI: 00:04.0 compute_resources_io: base: 100 size: 1000 align: 12 gran:
> 12 limit: ffff done
> PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
> limit: ffff
> PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
> limit: ffff done
> PCI: 00:04.0 1c * [0x0 - 0xfff] io
> PCI: 00:01.0 14 * [0x1000 - 0x10ff] io
> PCI: 00:11.0 20 * [0x1400 - 0x140f] io
> PCI: 00:11.0 10 * [0x1410 - 0x1417] io
> PCI: 00:11.0 18 * [0x1418 - 0x141f] io
> PCI: 00:11.0 14 * [0x1420 - 0x1423] io
> PCI: 00:11.0 1c * [0x1424 - 0x1427] io
> PCI_DOMAIN: 0000 compute_resources_io: base: 1428 size: 1428 align: 12
> gran: 0 limit: ffff done
> PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0
> limit: ffffffff
> PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran:
> 20 limit: ffffffffffffffff
> PCI: 01:00.0 20 * [0x0 - 0x3fff] prefmem
> PCI: 01:00.0 18 * [0x4000 - 0x4fff] prefmem
> PCI: 00:04.0 compute_resources_prefmem: base: 5000 size: 100000 align:
> 20 gran: 20 limit: ffffffffffffffff done
> PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
> limit: ffffffff
> PCI: 01:00.0 30 * [0x0 - 0x1ffff] mem
> PCI: 00:04.0 compute_resources_mem: base: 20000 size: 100000 align: 20
> gran: 20 limit: ffffffff done
> PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran:
> 20 limit: ffffffff
> PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran:
> 20 limit: ffffffff done
> PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
> limit: ffffffff
> PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
> limit: ffffffff done
> PCI: 00:01.0 10 * [0x0 - 0xfffffff] prefmem
> PCI: 00:04.0 24 * [0x10000000 - 0x100fffff] prefmem
> PCI: 00:04.0 20 * [0x10100000 - 0x101fffff] mem
> PCI: 00:01.0 18 * [0x10200000 - 0x1023ffff] mem
> PCI: 00:14.2 10 * [0x10240000 - 0x10243fff] mem
> PCI: 00:12.0 10 * [0x10244000 - 0x10244fff] mem
> PCI: 00:13.0 10 * [0x10245000 - 0x10245fff] mem
> PCI: 00:14.5 10 * [0x10246000 - 0x10246fff] mem
> PCI: 00:11.0 24 * [0x10247000 - 0x102473ff] mem
> PCI: 00:12.2 10 * [0x10247400 - 0x102474ff] mem
> PCI: 00:13.2 10 * [0x10247500 - 0x102475ff] mem
> PCI: 00:14.3 a0 * [0x10247600 - 0x10247600] mem
> PCI_DOMAIN: 0000 compute_resources_mem: base: 10247601 size: 10247601
> align: 28 gran: 0 limit: ffffffff done
> avoid_fixed_resources: PCI_DOMAIN: 0000
> avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
> avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
> constrain_resources: PCI_DOMAIN: 0000
> constrain_resources: PCI: 00:00.0
> constrain_resources: PCI: 00:01.0
> constrain_resources: PCI: 00:04.0
> constrain_resources: PCI: 01:00.0
> constrain_resources: PCI: 00:11.0
> constrain_resources: PCI: 00:12.0
> constrain_resources: PCI: 00:12.2
> constrain_resources: PCI: 00:13.0
> constrain_resources: PCI: 00:13.2
> constrain_resources: PCI: 00:14.0
> constrain_resources: I2C: 00:50
> constrain_resources: I2C: 00:51
> constrain_resources: PCI: 00:14.2
> constrain_resources: PCI: 00:14.3
> constrain_resources: PNP: 004e.5
> skipping PNP: 004e.5@62 fixed resource, size=0!
> constrain_resources: PNP: 004e.10
> constrain_resources: PCI: 00:14.4
> constrain_resources: PCI: 00:14.5
> constrain_resources: PCI: 00:18.0
> constrain_resources: PCI: 00:18.1
> constrain_resources: PCI: 00:18.2
> constrain_resources: PCI: 00:18.3
> constrain_resources: PCI: 00:18.4
> constrain_resources: PCI: 00:18.5
> constrain_resources: PCI: 00:18.6
> constrain_resources: PCI: 00:18.7
> avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff
> lim->base 00001000 lim->limit 0000ffff
> avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff
> lim->base 00000000 lim->limit febfffff
> Setting resources...
> PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:1428 align:12
> gran:0 limit:ffff
> Assigned: PCI: 00:04.0 1c * [0x1000 - 0x1fff] io
> Assigned: PCI: 00:01.0 14 * [0x2000 - 0x20ff] io
> Assigned: PCI: 00:11.0 20 * [0x2400 - 0x240f] io
> Assigned: PCI: 00:11.0 10 * [0x2410 - 0x2417] io
> Assigned: PCI: 00:11.0 18 * [0x2418 - 0x241f] io
> Assigned: PCI: 00:11.0 14 * [0x2420 - 0x2423] io
> Assigned: PCI: 00:11.0 1c * [0x2424 - 0x2427] io
> PCI_DOMAIN: 0000 allocate_resources_io: next_base: 2428 size: 1428
> align: 12 gran: 0 done
> PCI: 00:04.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12
> limit:ffff
> Assigned: PCI: 01:00.0 10 * [0x1000 - 0x10ff] io
> PCI: 00:04.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12
> gran: 12 done
> PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12
> limit:ffff
> PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12
> gran: 12 done
> PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10247601
> align:28 gran:0 limit:febfffff
> Assigned: PCI: 00:01.0 10 * [0xe0000000 - 0xefffffff] prefmem
> Assigned: PCI: 00:04.0 24 * [0xf0000000 - 0xf00fffff] prefmem
> Assigned: PCI: 00:04.0 20 * [0xf0100000 - 0xf01fffff] mem
> Assigned: PCI: 00:01.0 18 * [0xf0200000 - 0xf023ffff] mem
> Assigned: PCI: 00:14.2 10 * [0xf0240000 - 0xf0243fff] mem
> Assigned: PCI: 00:12.0 10 * [0xf0244000 - 0xf0244fff] mem
> Assigned: PCI: 00:13.0 10 * [0xf0245000 - 0xf0245fff] mem
> Assigned: PCI: 00:14.5 10 * [0xf0246000 - 0xf0246fff] mem
> Assigned: PCI: 00:11.0 24 * [0xf0247000 - 0xf02473ff] mem
> Assigned: PCI: 00:12.2 10 * [0xf0247400 - 0xf02474ff] mem
> Assigned: PCI: 00:13.2 10 * [0xf0247500 - 0xf02475ff] mem
> Assigned: PCI: 00:14.3 a0 * [0xf0247600 - 0xf0247600] mem
> PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f0247601 size:
> 10247601 align: 28 gran: 0 done
> PCI: 00:04.0 allocate_resources_prefmem: base:f0000000 size:100000
> align:20 gran:20 limit:febfffff
> Assigned: PCI: 01:00.0 20 * [0xf0000000 - 0xf0003fff] prefmem
> Assigned: PCI: 01:00.0 18 * [0xf0004000 - 0xf0004fff] prefmem
> PCI: 00:04.0 allocate_resources_prefmem: next_base: f0005000 size:
> 100000 align: 20 gran: 20 done
> PCI: 00:04.0 allocate_resources_mem: base:f0100000 size:100000 align:20
> gran:20 limit:febfffff
> Assigned: PCI: 01:00.0 30 * [0xf0100000 - 0xf011ffff] mem
> PCI: 00:04.0 allocate_resources_mem: next_base: f0120000 size: 100000
> align: 20 gran: 20 done
> PCI: 00:14.4 allocate_resources_prefmem: base:febfffff size:0 align:20
> gran:20 limit:febfffff
> PCI: 00:14.4 allocate_resources_prefmem: next_base: febfffff size: 0
> align: 20 gran: 20 done
> PCI: 00:14.4 allocate_resources_mem: base:febfffff size:0 align:20
> gran:20 limit:febfffff
> PCI: 00:14.4 allocate_resources_mem: next_base: febfffff size: 0 align:
> 20 gran: 20 done
> Root Device assign_resources, bus 0 link: 0
>
> Fam14h - cpu_bus_set_resources.
> APIC_CLUSTER: 0 c0010058 <- [0x00f8000000 - 0x00f8ffffff] size
> 0x01000000 gran 0x00 mem <mmconfig>
> APIC_CLUSTER: 0 assign_resources, bus 0 link: 0
> APIC_CLUSTER: 0 assign_resources, bus 0 link: 0
>
> Fam14h - domain_set_resources.
> amsr - incoming dev = 00272248
> adsr: (before) basek = 0, limitk = 7effffff.
> adsr: (after) basek = 0, limitk = 1fbfff, sizek = 1fc000.
> adsr - 0xa0000 to 0xbffff resource.
> adsr: mmio_basek=00380000, basek=00000300, limitk=001fbfff
> 0: mmio_basek=00380000, basek=00000300, limitk=001fbfff
> adsr - uma_memory_base = 67000000.
> adsr - mmio_basek = 380000.
> adsr - high_tables_size = e91000.
> adsr - adding uma resource.
>
> Fam14h - Adding UMA memory.
> PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
> PCI: 00:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran
> 0x1c prefmem
> PCI: 00:01.0 14 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran
> 0x08 io
> PCI: 00:01.0 18 <- [0x00f0200000 - 0x00f023ffff] size 0x00040000 gran
> 0x12 mem
> PCI: 00:04.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran
> 0x0c bus 01 io
> PCI: 00:04.0 24 <- [0x00f0000000 - 0x00f00fffff] size 0x00100000 gran
> 0x14 bus 01 prefmem
> PCI: 00:04.0 20 <- [0x00f0100000 - 0x00f01fffff] size 0x00100000 gran
> 0x14 bus 01 mem
> PCI: 00:04.0 assign_resources, bus 1 link: 0
> PCI: 01:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran
> 0x08 io
> PCI: 01:00.0 18 <- [0x00f0004000 - 0x00f0004fff] size 0x00001000 gran
> 0x0c prefmem64
> PCI: 01:00.0 20 <- [0x00f0000000 - 0x00f0003fff] size 0x00004000 gran
> 0x0e prefmem64
> PCI: 01:00.0 30 <- [0x00f0100000 - 0x00f011ffff] size 0x00020000 gran
> 0x11 romem
> PCI: 00:04.0 assign_resources, bus 1 link: 0
> PCI: 00:11.0 10 <- [0x0000002410 - 0x0000002417] size 0x00000008 gran
> 0x03 io
> PCI: 00:11.0 14 <- [0x0000002420 - 0x0000002423] size 0x00000004 gran
> 0x02 io
> PCI: 00:11.0 18 <- [0x0000002418 - 0x000000241f] size 0x00000008 gran
> 0x03 io
> PCI: 00:11.0 1c <- [0x0000002424 - 0x0000002427] size 0x00000004 gran
> 0x02 io
> PCI: 00:11.0 20 <- [0x0000002400 - 0x000000240f] size 0x00000010 gran
> 0x04 io
> PCI: 00:11.0 24 <- [0x00f0247000 - 0x00f02473ff] size 0x00000400 gran
> 0x0a mem
> PCI: 00:12.0 10 <- [0x00f0244000 - 0x00f0244fff] size 0x00001000 gran
> 0x0c mem
> PCI: 00:12.2 10 <- [0x00f0247400 - 0x00f02474ff] size 0x00000100 gran
> 0x08 mem
> PCI: 00:13.0 10 <- [0x00f0245000 - 0x00f0245fff] size 0x00001000 gran
> 0x0c mem
> PCI: 00:13.2 10 <- [0x00f0247500 - 0x00f02475ff] size 0x00000100 gran
> 0x08 mem
> PCI: 00:14.2 10 <- [0x00f0240000 - 0x00f0243fff] size 0x00004000 gran
> 0x0e mem64
> SB800 - Lpc.c - lpc_set_resources - Start.
> PCI: 00:14.3 a0 <- [0x00f0247600 - 0x00f0247600] size 0x00000001 gran
> 0x00 mem
> PCI: 00:14.3 assign_resources, bus 0 link: 0
> PNP: 004e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
> PNP: 004e.5 62 <- [0x0000000064 - 0x0000000063] size 0x00000000 gran 0x00 io
> PNP: 004e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran
> 0x00 irq
> ERROR: PNP: 004e.5 72 irq size: 0x0000000001 not assigned
> PNP: 004e.10 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran
> 0x03 io
> PNP: 004e.10 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran
> 0x00 irq
> PCI: 00:14.3 assign_resources, bus 0 link: 0
> SB800 - Lpc.c - lpc_set_resources - End.
> PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran
> 0x0c bus 02 io
> PCI: 00:14.4 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran
> 0x14 bus 02 prefmem
> PCI: 00:14.4 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran
> 0x14 bus 02 mem
> PCI: 00:14.5 10 <- [0x00f0246000 - 0x00f0246fff] size 0x00001000 gran
> 0x0c mem
> PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
> adsr - leaving this lovely routine.
> Root Device assign_resources, bus 0 link: 0
> Done setting resources.
> Show resources in subtree (Root Device)...After assigning values.
> Root Device child on link 0 APIC_CLUSTER: 0
> APIC_CLUSTER: 0 child on link 0 APIC: 00
> APIC_CLUSTER: 0 resource base f8000000 size 1000000 align 0 gran 0
> limit 0 flags f0000200 index c0010058
> APIC: 00
> APIC: 01
> PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
> PCI_DOMAIN: 0000 resource base 1000 size 1428 align 12 gran 0 limit
> ffff flags 40040100 index 10000000
> PCI_DOMAIN: 0000 resource base e0000000 size 10247601 align 28 gran 0
> limit febfffff flags 40040200 index 10000100
> PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0
> flags e0004200 index 10
> PCI_DOMAIN: 0000 resource base c0000 size 7ef3fc00 align 0 gran 0
> limit 0 flags e0004200 index 20
> PCI_DOMAIN: 0000 resource base 67000000 size 18000000 align 0 gran 0
> limit 0 flags f0000200 index 7
> PCI: 00:00.0
> PCI: 00:01.0
> PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 28
> limit febfffff flags 60001200 index 10
> PCI: 00:01.0 resource base 2000 size 100 align 8 gran 8 limit ffff
> flags 60000100 index 14
> PCI: 00:01.0 resource base f0200000 size 40000 align 18 gran 18
> limit febfffff flags 60000200 index 18
> PCI: 00:04.0 child on link 0 PCI: 01:00.0
> PCI: 00:04.0 resource base 1000 size 1000 align 12 gran 12 limit
> ffff flags 60080102 index 1c
> PCI: 00:04.0 resource base f0000000 size 100000 align 20 gran 20
> limit febfffff flags 60081202 index 24
> PCI: 00:04.0 resource base f0100000 size 100000 align 20 gran 20
> limit febfffff flags 60080202 index 20
> PCI: 01:00.0
> PCI: 01:00.0 resource base 1000 size 100 align 8 gran 8 limit ffff
> flags 60000100 index 10
> PCI: 01:00.0 resource base f0004000 size 1000 align 12 gran 12
> limit febfffff flags 60001201 index 18
> PCI: 01:00.0 resource base f0000000 size 4000 align 14 gran 14
> limit febfffff flags 60001201 index 20
> PCI: 01:00.0 resource base f0100000 size 20000 align 17 gran 17
> limit febfffff flags 60002200 index 30
> PCI: 00:05.0
> PCI: 00:06.0
> PCI: 00:07.0
> PCI: 00:08.0
> PCI: 00:11.0
> PCI: 00:11.0 resource base 2410 size 8 align 3 gran 3 limit ffff
> flags 60000100 index 10
> PCI: 00:11.0 resource base 2420 size 4 align 2 gran 2 limit ffff
> flags 60000100 index 14
> PCI: 00:11.0 resource base 2418 size 8 align 3 gran 3 limit ffff
> flags 60000100 index 18
> PCI: 00:11.0 resource base 2424 size 4 align 2 gran 2 limit ffff
> flags 60000100 index 1c
> PCI: 00:11.0 resource base 2400 size 10 align 4 gran 4 limit ffff
> flags 60000100 index 20
> PCI: 00:11.0 resource base f0247000 size 400 align 10 gran 10 limit
> febfffff flags 60000200 index 24
> PCI: 00:12.0
> PCI: 00:12.0 resource base f0244000 size 1000 align 12 gran 12 limit
> febfffff flags 60000200 index 10
> PCI: 00:12.1
> PCI: 00:12.2
> PCI: 00:12.2 resource base f0247400 size 100 align 8 gran 8 limit
> febfffff flags 60000200 index 10
> PCI: 00:13.0
> PCI: 00:13.0 resource base f0245000 size 1000 align 12 gran 12 limit
> febfffff flags 60000200 index 10
> PCI: 00:13.1
> PCI: 00:13.2
> PCI: 00:13.2 resource base f0247500 size 100 align 8 gran 8 limit
> febfffff flags 60000200 index 10
> PCI: 00:14.0 child on link 0 I2C: 00:50
> I2C: 00:50
> I2C: 00:51
> PCI: 00:14.1
> PCI: 00:14.2
> PCI: 00:14.2 resource base f0240000 size 4000 align 14 gran 14 limit
> febfffff flags 60000201 index 10
> PCI: 00:14.3 child on link 0 PNP: 004e.0
> PCI: 00:14.3 resource base f0247600 size 1 align 0 gran 0 limit
> febfffff flags 60000200 index a0
> PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags
> c0040100 index 10000000
> PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit
> 0 flags c0040200 index 10000100
> PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0
> flags c0000200 index 3
> PNP: 004e.0
> PNP: 004e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags
> c0000100 index 60
> PNP: 004e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags
> c0000400 index 70
> PNP: 004e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags
> c0000800 index 74
> PNP: 004e.3
> PNP: 004e.3 resource base 0 size 8 align 3 gran 3 limit 7ff flags
> 100 index 60
> PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
> index 70
> PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
> index 74
> PNP: 004e.4
> PNP: 004e.4 resource base 0 size 8 align 3 gran 3 limit fff flags
> 100 index 60
> PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
> index 70
> PNP: 004e.5
> PNP: 004e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff
> flags e0000100 index 60
> PNP: 004e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags
> e0000100 index 62
> PNP: 004e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags
> e0000400 index 70
> PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
> index 72
> PNP: 004e.6
> PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
> index 70
> PNP: 004e.a
> PNP: 004e.10
> PNP: 004e.10 resource base 3f8 size 8 align 3 gran 3 limit 7ff
> flags e0000100 index 60
> PNP: 004e.10 resource base 4 size 1 align 0 gran 0 limit 0 flags
> e0000400 index 70
> PNP: 004e.11
> PNP: 004e.11 resource base 2f8 size 8 align 3 gran 3 limit 7ff
> flags c0000100 index 60
> PNP: 004e.11 resource base 3 size 1 align 0 gran 0 limit 0 flags
> c0000400 index 70
> PCI: 00:14.4
> PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff
> flags 60080102 index 1c
> PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit
> febfffff flags 60081202 index 24
> PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit
> febfffff flags 60080202 index 20
> PCI: 00:14.5
> PCI: 00:14.5 resource base f0246000 size 1000 align 12 gran 12 limit
> febfffff flags 60000200 index 10
> PCI: 00:15.0
> PCI: 00:15.1
> PCI: 00:15.2
> PCI: 00:15.3
> PCI: 00:16.0
> PCI: 00:16.2
> PCI: 00:18.0
> PCI: 00:18.1
> PCI: 00:18.2
> PCI: 00:18.3
> PCI: 00:18.4
> PCI: 00:18.5
> PCI: 00:18.6
> PCI: 00:18.7
> Done allocating resources.
> POST: 0x88
> Enabling resources...
>
> Fam14h - domain_enable_resources: AmdInitMid.
> agesawrapper_amdinitmid SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> passed.
> ader - leaving domain_enable_resources.
> PCI: 00:00.0 cmd <- 06
> PCI: 00:01.0 subsystem <- 1022/1510
> PCI: 00:01.0 cmd <- 07
> PCI: 00:04.0 bridge ctrl <- 0003
> PCI: 00:04.0 cmd <- 07
> PCI: 00:11.0 subsystem <- 1022/1510
> PCI: 00:11.0 cmd <- 03
> PCI: 00:12.0 subsystem <- 1022/1510
> PCI: 00:12.0 cmd <- 02
> PCI: 00:12.2 subsystem <- 1022/1510
> PCI: 00:12.2 cmd <- 02
> PCI: 00:13.0 subsystem <- 1022/1510
> PCI: 00:13.0 cmd <- 02
> PCI: 00:13.2 subsystem <- 1022/1510
> PCI: 00:13.2 cmd <- 02
> PCI: 00:14.0 subsystem <- 1022/1510
> PCI: 00:14.0 cmd <- 403
> PCI: 00:14.2 subsystem <- 1022/1510
> PCI: 00:14.2 cmd <- 02
> PCI: 00:14.3 subsystem <- 1022/1510
> PCI: 00:14.3 cmd <- 0f
> PCI: 00:14.4 bridge ctrl <- 0003
> PCI: 00:14.4 subsystem <- 1022/1510
> PCI: 00:14.4 cmd <- 21
> PCI: 00:14.5 subsystem <- 1022/1510
> PCI: 00:14.5 cmd <- 02
> PCI: 00:18.0 subsystem <- 1022/1510
> PCI: 00:18.0 cmd <- 00
> PCI: 00:18.1 subsystem <- 1022/1510
> PCI: 00:18.1 cmd <- 00
> PCI: 00:18.2 subsystem <- 1022/1510
> PCI: 00:18.2 cmd <- 00
> PCI: 00:18.3 subsystem <- 1022/1510
> PCI: 00:18.3 cmd <- 00
> PCI: 00:18.4 subsystem <- 1022/1510
> PCI: 00:18.4 cmd <- 00
> PCI: 00:18.5 subsystem <- 1022/1510
> PCI: 00:18.5 cmd <- 00
> PCI: 00:18.6 subsystem <- 1022/1510
> PCI: 00:18.6 cmd <- 00
> PCI: 00:18.7 subsystem <- 1022/1510
> PCI: 00:18.7 cmd <- 00
> PCI: 01:00.0 cmd <- 03
> done.
> Initializing devices...
> Root Device init
> APIC_CLUSTER: 0 init
> start_eip=0x00006000, offset=0x00200000, code_size=0x0000005b
> Initializing CPU #0
> CPU: vendor AMD device 500f20
> CPU: family 14, model 02, stepping 00
> Model 14 Init.
>
> MTRR check
> Fixed MTRRs : Enabled
> Variable MTRRs: Enabled
>
> POST: 0x93
> POST: 0x60
> Enabling cache
> Setting up local apic... apic_id: 0x00 done.
> POST: 0x9b
> model_14_init done.
> CPU #0 initialized
> Asserting INIT.
> Waiting for send to finish...
> +Deasserting INIT.
> Waiting for send to finish...
> +#startup loops: 2.
> Sending STARTUP #1 to 1.
> After apic_write.
> Startup point 1.
> Waiting for send to finish...
> +Sending STARTUP #2 to 1.
> After apic_write.
> Startup point 1.
> Waiting for send to finish...
> +After Startup.
> Initializing CPU #1
> Waiting for 1 CPUS to stop
> CPU: vendor AMD device 500f20
> CPU: family 14, model 02, stepping 00
> Model 14 Init.
>
> MTRR check
> Fixed MTRRs : Enabled
> Variable MTRRs: Enabled
>
> POST: 0x93
> POST: 0x60
> Enabling cache
> Setting up local apic... apic_id: 0x01 done.
> POST: 0x9b
> model_14_init done.
> CPU #1 initialized
> All AP CPUs stopped (5043 loops)
> PCI: 00:00.0 init
> Northbridge init
> PCI: 00:01.0 init
> CBFS: Looking for 'pci1002,9804.rom'
> CBFS: found.
> In CBFS, ROM address for PCI: 00:01.0 = ffe00778
> PCI expansion ROM, signature 0xaa55, INIT size 0xe200, data ptr 0x01b0
> PCI ROM image, vendor ID 1002, device ID 9804,
> PCI ROM image, Class Code 030000, Code Type 00
> Copying VGA ROM Image from ffe00778 to 0xc0000, 0xe200 bytes
> Real mode stub @00000600: 867 bytes
> Calling Option ROM...
> ... Option ROM returned.
> Getting information about VESA mode 4117
> framebuffer: e0000000
> Setting VESA mode 4117
> PCI: 00:11.0 init
> AHCI controller IOMEM base: 0xF0247000, IRQ: 0x0
> Number of Ports: 0x6, Port implemented(bit map): 0x3f
> AHCI/RAID controller initialized
> PCI: 00:14.0 init
> CBFS: Looking for 'pci1002,4385.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1002,4385.rom'.
> PCI: 00:14.4 init
> PCI: 00:18.0 init
> CBFS: Looking for 'pci1022,1700.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1022,1700.rom'.
> PCI: 00:18.1 init
> CBFS: Looking for 'pci1022,1701.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1022,1701.rom'.
> PCI: 00:18.2 init
> CBFS: Looking for 'pci1022,1702.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1022,1702.rom'.
> PCI: 00:18.3 init
> CBFS: Looking for 'pci1022,1703.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1022,1703.rom'.
> PCI: 00:18.4 init
> CBFS: Looking for 'pci1022,1704.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1022,1704.rom'.
> PCI: 00:18.5 init
> CBFS: Looking for 'pci1022,1718.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1022,1718.rom'.
> PCI: 00:18.6 init
> CBFS: Looking for 'pci1022,1716.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1022,1716.rom'.
> PCI: 00:18.7 init
> CBFS: Looking for 'pci1022,1719.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1022,1719.rom'.
> PCI: 01:00.0 init
> CBFS: Looking for 'pci10ec,8168.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci10ec,8168.rom'.
> Option ROM address for PCI: 01:00.0 = f0100000
> PCI expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000
> Incorrect expansion ROM header signature 0000
> PNP: 004e.5 init
> Keyboard init...
> No PS/2 keyboard detected.
> PNP: 004e.10 init
> Devices initialized
> Show all devs...After init.
> Root Device: enabled 1
> APIC_CLUSTER: 0: enabled 1
> APIC: 00: enabled 1
> PCI_DOMAIN: 0000: enabled 1
> PCI: 00:00.0: enabled 1
> PCI: 00:01.0: enabled 1
> PCI: 00:01.1: enabled 1
> PCI: 00:04.0: enabled 1
> PCI: 00:05.0: enabled 0
> PCI: 00:06.0: enabled 0
> PCI: 00:07.0: enabled 0
> PCI: 00:08.0: enabled 0
> PCI: 00:11.0: enabled 1
> PCI: 00:12.0: enabled 1
> PCI: 00:12.1: enabled 0
> PCI: 00:12.2: enabled 1
> PCI: 00:13.0: enabled 1
> PCI: 00:13.1: enabled 0
> PCI: 00:13.2: enabled 1
> PCI: 00:14.0: enabled 1
> I2C: 00:50: enabled 1
> I2C: 00:51: enabled 1
> PCI: 00:14.1: enabled 0
> PCI: 00:14.2: enabled 1
> PCI: 00:14.3: enabled 1
> PNP: 004e.0: enabled 0
> PNP: 004e.3: enabled 0
> PNP: 004e.4: enabled 0
> PNP: 004e.5: enabled 1
> PNP: 004e.6: enabled 0
> PNP: 004e.a: enabled 0
> PNP: 004e.10: enabled 1
> PNP: 004e.11: enabled 0
> PCI: 00:14.4: enabled 1
> PCI: 00:14.5: enabled 1
> PCI: 00:15.0: enabled 0
> PCI: 00:15.1: enabled 0
> PCI: 00:15.2: enabled 0
> PCI: 00:15.3: enabled 0
> PCI: 00:16.0: enabled 0
> PCI: 00:16.2: enabled 0
> PCI: 00:18.0: enabled 1
> PCI: 00:18.1: enabled 1
> PCI: 00:18.2: enabled 1
> PCI: 00:18.3: enabled 1
> PCI: 00:18.4: enabled 1
> PCI: 00:18.5: enabled 1
> PCI: 00:18.6: enabled 1
> PCI: 00:18.7: enabled 1
> APIC: 01: enabled 1
> PCI: 01:00.0: enabled 1
> POST: 0x89
> Re-Initializing CBMEM area to 0x6616f000
> Initializing CBMEM area to 0x6616f000 (15273984 bytes)
> dword=6616f000
> nvram_pos=f8, dword>>(8*i)=0
> nvram_pos=f9, dword>>(8*i)=f0
> nvram_pos=fa, dword>>(8*i)=16
> nvram_pos=fb, dword>>(8*i)=66
> Adding CBMEM entry as no. 1
> Moving GDT to 6616f200...ok
> POST: 0x8a
> High Tables Base is 6616f000.
> POST: 0x9a
> SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> agesawrapper_amdinitlate: AmdLateParamsPtr = 220B2
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> In agesawrapper_amdinitlate, AGESA generated ACPI tables:
> DmiTable:00000000
> AcpiPstate: 00022165
> AcpiSrat:00000000
> AcpiSlit:00000000
> Mce:00022621
> Cmc:000226c7
> Alib:00022765
> SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> mid=0, did=0
> mid=0, did=0
> mid=0, did=0
> mid=c2, did=14
> mid=0, did=0
> mid=0, did=0
> mid=0, did=0
> mid=c2, did=14
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
> Adding CBMEM entry as no. 2
> Writing IRQ routing tables to 0x6616f400...write_pirq_routing_table done.
> PIRQ table: 48 bytes.
> POST: 0x9b
> Wrote the mp table end at: 000f0410 - 000f0514
> Adding CBMEM entry as no. 3
> Wrote the mp table end at: 66170410 - 66170514
> MP table: 276 bytes.
> POST: 0x9c
> Adding CBMEM entry as no. 4
> ACPI: Writing ACPI tables at 66171400...
> ACPI: * DSDT at 661714c8
> ACPI: * DSDT @ 661714c8 Length 28cd
> ACPI: * FACS at 66173d98
> ACPI: * FADT at 66173dd8
> ACPI_BLK_BASE: 0x0800
> ACPI: added table 1/32, length now 40
> ACPI: * HPET at 66173ed0
> ACPI: added table 2/32, length now 44
> ACPI: * MADT at 66173f08
> ACPI: added table 3/32, length now 48
> ACPI: added table 4/32, length now 52
> ACPI: * SRAT at 66174100
> AGESA SRAT table NULL. Skipping.
> ACPI: * SLIT at 66174100
> AGESA SLIT table NULL. Skipping.
> ACPI: * AGESA ALIB SSDT at 66174100
> ACPI: added table 5/32, length now 56
> ACPI: * AGESA SSDT Pstate at 66175790
> ACPI: added table 6/32, length now 60
> ACPI: * coreboot TOM SSDT2 at 66175aa0
> ACPI: added table 7/32, length now 64
> ACPI: done.
> ACPI tables: 18149 bytes.
> Adding CBMEM entry as no. 5
> smbios_write_tables: 6617c800
> Root Device (AMD Persimmon Mainboard)
> APIC_CLUSTER: 0 (AMD Family 14h Root Complex)
> APIC: 00 (AMD CPU Family 14h)
> PCI_DOMAIN: 0000 (AMD Family 14h Root Complex)
> PCI: 00:00.0 (AMD Family 14h Northbridge)
> PCI: 00:01.0 (AMD Family 14h Northbridge)
> PCI: 00:01.1 (AMD Family 14h Northbridge)
> PCI: 00:04.0 (AMD Family 14h Northbridge)
> PCI: 00:05.0 (AMD Family 14h Northbridge)
> PCI: 00:06.0 (AMD Family 14h Northbridge)
> PCI: 00:07.0 (AMD Family 14h Northbridge)
> PCI: 00:08.0 (AMD Family 14h Northbridge)
> PCI: 00:11.0 (ATI SB800)
> PCI: 00:12.0 (ATI SB800)
> PCI: 00:12.1 (ATI SB800)
> PCI: 00:12.2 (ATI SB800)
> PCI: 00:13.0 (ATI SB800)
> PCI: 00:13.1 (ATI SB800)
> PCI: 00:13.2 (ATI SB800)
> PCI: 00:14.0 (ATI SB800)
> I2C: 00:50 ()
> I2C: 00:51 ()
> PCI: 00:14.1 (ATI SB800)
> PCI: 00:14.2 (ATI SB800)
> PCI: 00:14.3 (ATI SB800)
> PNP: 004e.0 (Fintek F81865F Super I/O)
> PNP: 004e.3 (Fintek F81865F Super I/O)
> PNP: 004e.4 (Fintek F81865F Super I/O)
> PNP: 004e.5 (Fintek F81865F Super I/O)
> PNP: 004e.6 (Fintek F81865F Super I/O)
> PNP: 004e.a (Fintek F81865F Super I/O)
> PNP: 004e.10 (Fintek F81865F Super I/O)
> PNP: 004e.11 (Fintek F81865F Super I/O)
> PCI: 00:14.4 (ATI SB800)
> PCI: 00:14.5 (ATI SB800)
> PCI: 00:15.0 (ATI SB800)
> PCI: 00:15.1 (ATI SB800)
> PCI: 00:15.2 (ATI SB800)
> PCI: 00:15.3 (ATI SB800)
> PCI: 00:16.0 (ATI SB800)
> PCI: 00:16.2 (ATI SB800)
> PCI: 00:18.0 (AMD Family 14h Northbridge)
> PCI: 00:18.1 (AMD Family 14h Northbridge)
> PCI: 00:18.2 (AMD Family 14h Northbridge)
> PCI: 00:18.3 (AMD Family 14h Northbridge)
> PCI: 00:18.4 (AMD Family 14h Northbridge)
> PCI: 00:18.5 (AMD Family 14h Northbridge)
> PCI: 00:18.6 (AMD Family 14h Northbridge)
> PCI: 00:18.7 (AMD Family 14h Northbridge)
> APIC: 01 ()
> PCI: 01:00.0 ()
> SMBIOS tables: 287 bytes.
> POST: 0x9d
> Adding CBMEM entry as no. 6
> Writing high table forward entry at 0x00000500
> Wrote coreboot table at: 00000500, 0x10 bytes, checksum c9c6
> New low_table_end: 0x00000528
> Now going to write high coreboot table at 0x6617d000
> rom_table_end = 0x6617d000
> Adjust low_table_end from 0x00000528 to 0x00001000
> Adjust rom_table_end from 0x6617d000 to 0x66180000
> Adding high table area
> uma_memory_start=0x67000000, uma_memory_size=0x18000000
> coreboot memory table:
> 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
> 1. 0000000000001000-000000000009ffff: RAM
> 2. 00000000000c0000-000000006616efff: RAM
> 3. 000000006616f000-0000000066ffffff: CONFIGURATION TABLES
> 4. 0000000067000000-000000007effffff: RESERVED
> 5. 00000000f8000000-00000000f8ffffff: RESERVED
> Wrote coreboot table at: 6617d000, 0x1fc bytes, checksum 18f
> coreboot table: 532 bytes.
> POST: 0x9e
> Adding CBMEM entry as no. 7
> Adding CBMEM entry as no. 8
> POST: 0x9d
> Multiboot Information structure has been written.
> 0. FREE SPACE 66ff6000 0000a000
> 1. GDT 6616f200 00000200
> 2. IRQ TABLE 6616f400 00001000
> 3. SMP TABLE 66170400 00001000
> 4. ACPI 66171400 0000b400
> 5. SMBIOS 6617c800 00000800
> 6. COREBOOT 6617d000 00008000
> 7. ACPI RESUME66185000 00e00000
> 8. ACPISCRATCH66f85000 00071000
> CBFS: Looking for 'fallback/payload'
> CBFS: found.
> Got a payload
> Loading segment from rom address 0xffee35f8
> code (compression=0)
> New segment dstaddr 0xe74a0 memsize 0x18b60 srcaddr 0xffee3630
> filesize 0x18b60
> (cleaned up) New segment addr 0xe74a0 size 0x18b60 offset 0xffee3630
> filesize 0x18b60
> Loading segment from rom address 0xffee3614
> Entry Point 0x00000000
> Loading Segment: addr: 0x00000000000e74a0 memsz: 0x0000000000018b60
> filesz: 0x0000000000018b60
> lb: [0x0000000000200000, 0x0000000000360000)
> Post relocation: addr: 0x00000000000e74a0 memsz: 0x0000000000018b60
> filesz: 0x0000000000018b60
> it's not compressed!
> [ 0x000e74a0, 00100000, 0x00100000) <- ffee3630
> dest 000e74a0, end 00100000, bouncebuffer 65eaf000
> Loaded segments
> Jumping to boot code at fc855
> POST: 0xf8
> entry = 0x000fc855
> lb_start = 0x00200000
> lb_size = 0x00160000
> adjust = 0x65e0f000
> buffer = 0x65eaf000
> elf_boot_notes = 0x00272e18
> adjusted_boot_notes = 0x66081e18
> Start bios (version rel-1.7.0-0-ga026308-20120523_124912-leaky)
> Found mainboard AMD Persimmon
> Found CBFS header at 0xfffffbf0
> Ram Size=0x6616f000 (0x0000000000000000 high)
> Relocating init from 0x000e7b40 to 0x66154ae0 (size 41976)
> CPU Mhz=1001
> Found 22 PCI devices (max PCI bus is 02)
> Found 2 cpu(s) max supported 2 cpu(s)
> Copying PIR from 0x6616f400 to 0x000fdbc0
> Copying MPTABLE from 0x66170400/66170410 to 0x000fdaa0
> Copying ACPI RSDP from 0x66171400 to 0x000fda80
> Copying SMBIOS entry point from 0x6617c800 to 0x000fda60
> Scan for VGA option rom
> Found option rom with bad checksum: loc=0x000c0000 len=57856 sum=b
> EHCI init on dev 00:12.2 (regs=0xf0247420)
> EHCI init on dev 00:13.2 (regs=0xf0247520)
> OHCI init on dev 00:14.5 (regs=0xf0246000)
> Found 0 lpt ports
> Found 3 serial ports
> ebda moved from 9fc00 to 9f400
> AHCI controller at 11.0, iobase f0247000, irq 0
> OHCI init on dev 00:12.0 (regs=0xf0244000)
> Searching bootorder for: /pci@i0cf8/*@11/drive@3/disk@0
> ebda moved from 9f400 to 9f000
> ebda moved from 9f000 to 9ec00
> AHCI/3: registering: "AHCI/3: KINGSTON SV100S264G ATA-8 Hard-Disk (61057
> MiBytes)"
> Got ps2 nak (status=51)
> USB keyboard initialized
> All threads complete.
> Scan for option roms
> Press F12 for boot menu.
>
> drive 0x000fda00: PCHS=16383/16/63 translation=lba LCHS=1024/255/63
> s=125045424
> Returned 57344 bytes of ZoneHigh
> e820 map has 6 items:
> 0: 0000000000000000 - 000000000009ec00 = 1 RAM
> 1: 000000000009ec00 - 00000000000a0000 = 2 RESERVED
> 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
> 3: 0000000000100000 - 000000006616d000 = 1 RAM
> 4: 000000006616d000 - 000000007f000000 = 2 RESERVED
> 5: 00000000f8000000 - 00000000f9000000 = 2 RESERVED
> enter handle_19:
> NULL
> Booting from Hard Disk...
> Booting from 0000:7c00
>
1
0
Hi all,
I had this long in mind, now it works, coreboot can be run as Linux process and
IO is done through a serialICE. This is handy for debugging and valgrinding, or
maybe handy for zillions of other reasons.
How it works:
ruik@ruik:~/coreboot$ gdb ./build/cbfs/fallback/coreboot_ram.elf
(gdb) run
Starting program: /home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf
POST: 0x80
IO WRITE: [00000080] 00000080 size 1
SerialICE not ready yet (ignoring)
POST: 0x39
IO WRITE: [00000080] 00000039 size 1
SerialICE not ready yet (ignoring)
coreboot-4.0-2408-gad422c0-dirty Tue Jun 5 00:04:52 CEST 2012 booting...
POST: 0x40
IO WRITE: [00000080] 00000040 size 1
SerialICE not ready yet (ignoring)
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
PCI_DOMAIN: 0000: enabled 1
....
Or when it crashes:
Root Device init
APIC_CLUSTER: 0 init
MSR WRITE: [0000001b] 00000000fee00900
MSR READ: [0000001b] 00000000fee00900
MEM READ: [fee00020] 00000000 size 4
==13541== Invalid read of size 1
==13541== at 0x106C0E: ??? (in
/home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf)
==13541== by 0x10991B: ??? (in
/home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf)
==13541== by 0x10AD0B: ??? (in
/home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf)
==13541== by 0x10BA3F: ??? (in
/home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf)
==13541== by 0x10C232: ??? (in
/home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf)
==13541== by 0x106F99: ??? (in
/home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf)
==13541== by 0x10003D: ??? (in
/home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf)
==13541== by 0x127347: ??? (in
/home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf)
==13541== Address 0xa000 is not stack'd, malloc'd or (recently) free'd
==13541==
==13541==
==13541== Process terminating with default action of signal 11 (SIGSEGV)
==13541== Access not within mapped region at address 0xA000
Please note that valgrind is confused with our debug symbols, but gdb works fine.
In general, the real coreboot jumps to hacked version of serial ICE and waits.
The userspace program is run as any process and hacked version serialICE host
from qemu talks normally to linux kernel (this is done via custom 0x80 calls)
no libc is used, even the memory layout is same. The only memory mapped is what
ELF has and also highmem/lowmem bits (check ulinux_mmap calls).
It is still very experimental but works fine. I put together quickly some
patches which may be found here:
emote: New Changes:
remote: http://review.coreboot.org/1089
remote: http://review.coreboot.org/1090
remote: http://review.coreboot.org/1091
remote: http://review.coreboot.org/1092
remote: http://review.coreboot.org/1093
remote: http://review.coreboot.org/1094
remote: http://review.coreboot.org/1095
remote: http://review.coreboot.org/1096
remote: http://review.coreboot.org/1097
Thanks
Rudolf
1
0
New patch to review for coreboot: 2551459 Random VIA fixups to make it faster or non-crashing
by Rudolf Marek 05 Jun '12
by Rudolf Marek 05 Jun '12
05 Jun '12
Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1097
-gerrit
commit 255145949fe31a194c8e47b0af0d73b6775907c3
Author: Rudolf Marek <r.marek(a)assembler.cz>
Date: Tue Jun 5 00:31:09 2012 +0200
Random VIA fixups to make it faster or non-crashing
IOAPIC uses now read32/write32 which is redirected, possibly even better is to use common IOAPIC setup
ditch out the dump of PCI space, it takes way a lot time with serialICE.
Change-Id: I029091973cee3dafc39a8d4b18aae4d8c6d10127
Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz>
---
src/southbridge/via/k8t890/pcie.c | 7 ++++++-
src/southbridge/via/k8t890/traf_ctrl.c | 14 +++++++-------
src/southbridge/via/vt8237r/vt8237r.c | 2 ++
3 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/src/southbridge/via/k8t890/pcie.c b/src/southbridge/via/k8t890/pcie.c
index 2840bf3..6ec1c41 100644
--- a/src/southbridge/via/k8t890/pcie.c
+++ b/src/southbridge/via/k8t890/pcie.c
@@ -35,6 +35,11 @@ static void pcie_common_init(struct device *dev)
{
u8 reg;
int i, up;
+#if CONFIG_ULINUX
+ int loops = 2;
+#else
+ int loops = 1000;
+#endif
/* Disable downstream read cycle retry,
* otherwise the bus scan will hang if no device is plugged in. */
@@ -64,7 +69,7 @@ static void pcie_common_init(struct device *dev)
/* Wait up to 100ms for link to come up */
up = 0;
- for (i=0; i<1000; i++) {
+ for (i=0; i<loops; i++) {
if (pci_read_config16(dev, 0x52) & (1<<13)) {
up = 1;
break;
diff --git a/src/southbridge/via/k8t890/traf_ctrl.c b/src/southbridge/via/k8t890/traf_ctrl.c
index d3ed1e7..c55052c 100644
--- a/src/southbridge/via/k8t890/traf_ctrl.c
+++ b/src/southbridge/via/k8t890/traf_ctrl.c
@@ -21,6 +21,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <console/console.h>
+#include <arch/io.h>
#include "k8t890.h"
extern unsigned long log2(unsigned long x);
@@ -96,14 +97,13 @@ static void traf_ctrl_enable_generic(struct device *dev)
apic = (u32 *)K8T890_APIC_BASE;
/* Set APIC to FSB transported messages. */
- apic[0] = 3;
- data = apic[4];
- apic[4] = (data & 0xFFFFFE) | 1;
-
+ write32(K8T890_APIC_BASE, 3);
+ data = read32(K8T890_APIC_BASE + 0x10);
+ write32(K8T890_APIC_BASE + 0x10, (data & 0xFFFFFE) | 1);
/* Set APIC ID. */
- apic[0] = 0;
- data = apic[4];
- apic[4] = (data & 0xF0FFFF) | (K8T890_APIC_ID << 24);
+ write32(K8T890_APIC_BASE, 0);
+ data = read32(K8T890_APIC_BASE + 0x10);
+ write32(K8T890_APIC_BASE + 0x10, (data & 0xF0FFFF) | (K8T890_APIC_ID << 24));
}
static void traf_ctrl_enable_k8m890(struct device *dev)
diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c
index 586df66..c8eaca1 100644
--- a/src/southbridge/via/vt8237r/vt8237r.c
+++ b/src/southbridge/via/vt8237r/vt8237r.c
@@ -54,6 +54,7 @@ void writeback(struct device *dev, u16 where, u8 what)
void dump_south(device_t dev)
{
+#if CONFIG_ULINUX == 0
int i, j;
for (i = 0; i < 256; i += 16) {
@@ -62,6 +63,7 @@ void dump_south(device_t dev)
printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i + j));
printk(BIOS_DEBUG, "\n");
}
+#endif
}
static void vt8237r_enable(struct device *dev)
1
0
New patch to review for coreboot: 2eea342 Hack in the target part of serialICE this needs to be done in more sane way.
by Rudolf Marek 05 Jun '12
by Rudolf Marek 05 Jun '12
05 Jun '12
Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1096
-gerrit
commit 2eea3421b95a5b1127805ac623ea5a16cfae2e83
Author: Rudolf Marek <r.marek(a)assembler.cz>
Date: Tue Jun 5 00:29:45 2012 +0200
Hack in the target part of serialICE this needs to be done in more sane way.
Just some quick and dirty way of using real serialICE.
Change-Id: I4b39eba9526bdd21e99044bc5f67106176d26e2b
Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz>
---
src/arch/x86/lib/cbfs_and_run.c | 5 +-
src/lib/Makefile.inc | 1 +
src/lib/serialice/serial.c | 196 ++++++++++++++++++++++++++++++
src/lib/serialice/serialice.c | 256 +++++++++++++++++++++++++++++++++++++++
src/lib/serialice/serialice.h | 31 +++++
5 files changed, 487 insertions(+), 2 deletions(-)
diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c
index 62b2789..a63e50d 100644
--- a/src/arch/x86/lib/cbfs_and_run.c
+++ b/src/arch/x86/lib/cbfs_and_run.c
@@ -25,7 +25,6 @@
static void cbfs_and_run_core(const char *filename, unsigned ebp)
{
u8 *dst;
-
timestamp_add_now(TS_START_COPYRAM);
print_debug("Loading image.\n");
dst = cbfs_load_stage(filename);
@@ -40,13 +39,15 @@ static void cbfs_and_run_core(const char *filename, unsigned ebp)
:: "a"(ebp), "D"(dst)
);
}
-
+void serialice_main(void);
void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset)
{
// FIXME fix input parameters instead normalizing them here.
if (cpu_reset == 1) cpu_reset = -1;
else cpu_reset = 0;
+ serialice_main();
+
cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset);
}
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 3bd7f99..e6ae8b6 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -21,6 +21,7 @@ romstage-$(CONFIG_USBDEBUG) += usbdebug.c
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
romstage-y += compute_ip_checksum.c
romstage-y += memmove.c
+romstage-y += serialice/serialice.c
ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
ramstage-y += memset.c
diff --git a/src/lib/serialice/serial.c b/src/lib/serialice/serial.c
new file mode 100644
index 0000000..529009c
--- /dev/null
+++ b/src/lib/serialice/serial.c
@@ -0,0 +1,196 @@
+/*
+ * SerialICE
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+
+/* SIO functions */
+
+static void sio_init(void)
+{
+#if SIO_SPEED > 115200
+ /* "high speed" serial requires special chip setup
+ * (to be done in superio_init), and special divisor
+ * values (implement superio_serial_divisor() for that).
+ * Maybe it requires even more, but so far that seems
+ * to be enough.
+ */
+ int divisor = superio_serial_divisor(SIO_SPEED);
+#else
+ int divisor = 115200 / SIO_SPEED;
+#endif
+ int lcs = 3;
+ outb(0x00, SIO_PORT + UART_IER);
+ outb(0x01, SIO_PORT + UART_FCR);
+ outb(0x03, SIO_PORT + UART_MCR);
+ outb(0x80 | lcs, SIO_PORT + UART_LCR);
+ outb(divisor & 0xff, SIO_PORT + UART_DLL);
+ outb((divisor >> 8) & 0xff, SIO_PORT + UART_DLM);
+ outb(lcs, SIO_PORT + UART_LCR);
+}
+
+static void sio_putc(u8 data)
+{
+ while (!(inb(SIO_PORT + UART_LSR) & 0x20)) ;
+ outb(data, SIO_PORT + UART_TBR);
+ while (!(inb(SIO_PORT + UART_LSR) & 0x40)) ;
+}
+
+static u8 sio_getc(void)
+{
+ u8 val;
+ while (!(inb(SIO_PORT + UART_LSR) & 0x01)) ;
+
+ val = inb(SIO_PORT + UART_RBR);
+
+#if ECHO_MODE
+ sio_putc(val);
+#endif
+ return val;
+}
+
+/* SIO helpers */
+
+static void sio_putstring(const char *string)
+{
+ /* Very simple, no %d, %x etc. */
+ while (*string) {
+ if (*string == '\n')
+ sio_putc('\r');
+ sio_putc(*string);
+ string++;
+ }
+}
+
+#define sio_put_nibble(nibble) \
+ if (nibble > 9) \
+ nibble += ('a' - 10); \
+ else \
+ nibble += '0'; \
+ sio_putc(nibble)
+
+static void sio_put8(u8 data)
+{
+ u8 c;
+
+ c = (data >> 4) & 0xf;
+ sio_put_nibble(c);
+
+ c = data & 0xf;
+ sio_put_nibble(c);
+}
+
+static void sio_put16(u16 data)
+{
+ int i;
+ for (i=12; i >= 0; i -= 4) {
+ u8 c = (data >> i) & 0xf;
+ sio_put_nibble(c);
+ }
+}
+
+static void sio_put32(u32 data)
+{
+ int i;
+ for (i=28; i >= 0; i -= 4) {
+ u8 c = (data >> i) & 0xf;
+ sio_put_nibble(c);
+ }
+}
+
+static u8 sio_get_nibble(void)
+{
+ u8 ret = 0;
+ u8 nibble = sio_getc();
+
+ if (nibble >= '0' && nibble <= '9') {
+ ret = (nibble - '0');
+ } else if (nibble >= 'a' && nibble <= 'f') {
+ ret = (nibble - 'a') + 0xa;
+ } else if (nibble >= 'A' && nibble <= 'F') {
+ ret = (nibble - 'A') + 0xa;
+ } else {
+ sio_putstring("ERROR: parsing number\n");
+ }
+ return ret;
+}
+
+static u8 sio_get8(void)
+{
+ u8 data;
+ data = sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ return data;
+}
+
+static u16 sio_get16(void)
+{
+ u16 data;
+
+ data = sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+
+ return data;
+}
+
+static u32 sio_get32(void)
+{
+ u32 data;
+
+ data = sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+
+ return data;
+}
+
+
diff --git a/src/lib/serialice/serialice.c b/src/lib/serialice/serialice.c
new file mode 100644
index 0000000..0a5a8e0
--- /dev/null
+++ b/src/lib/serialice/serialice.c
@@ -0,0 +1,256 @@
+/*
+ * SerialICE
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "serialice.h"
+#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <arch/cpu.h>
+
+const char boardname[33]="infinite improbability board ";
+
+
+/* Hardware specific functions */
+
+/* SIO functions */
+#include "serial.c"
+
+/* Accessor functions */
+
+static void serialice_read_memory(void)
+{
+ u8 width;
+ u32 addr;
+
+ // Format:
+ // *rm00000000.w
+ addr = sio_get32();
+ sio_getc(); // skip .
+ width = sio_getc();
+
+ sio_putc('\r'); sio_putc('\n');
+
+ switch (width) {
+ case 'b': sio_put8(read8(addr)); break;
+ case 'w': sio_put16(read16(addr)); break;
+ case 'l': sio_put32(read32(addr)); break;
+ }
+}
+
+static void serialice_write_memory(void)
+{
+ u8 width;
+ u32 addr;
+ u32 data;
+
+ // Format:
+ // *wm00000000.w=0000
+ addr = sio_get32();
+ sio_getc(); // skip .
+ width = sio_getc();
+ sio_getc(); // skip =
+
+ switch (width) {
+ case 'b': data = sio_get8(); write8(addr, (u8)data); break;
+ case 'w': data = sio_get16(); write16(addr, (u16)data); break;
+ case 'l': data = sio_get32(); write32(addr, (u32)data); break;
+ }
+}
+
+static void serialice_read_io(void)
+{
+ u8 width;
+ u16 port;
+
+ // Format:
+ // *ri0000.w
+ port = sio_get16();
+ sio_getc(); // skip .
+ width = sio_getc();
+
+ sio_putc('\r'); sio_putc('\n');
+
+ switch (width) {
+ case 'b': sio_put8(inb(port)); break;
+ case 'w': sio_put16(inw(port)); break;
+ case 'l': sio_put32(inl(port)); break;
+ }
+}
+
+static void serialice_write_io(void)
+{
+ u8 width;
+ u16 port;
+ u32 data;
+
+ // Format:
+ // *wi0000.w=0000
+ port = sio_get16();
+ sio_getc(); // skip .
+ width = sio_getc();
+ sio_getc(); // skip =
+
+ switch (width) {
+ case 'b': data = sio_get8(); outb((u8)data, port); break;
+ case 'w': data = sio_get16(); outw((u16)data, port); break;
+ case 'l': data = sio_get32(); outl((u32)data, port); break;
+ }
+}
+
+static void serialice_read_msr(void)
+{
+ u32 addr, key;
+ msr_t msr;
+
+ // Format:
+ // *rc00000000.9c5a203a
+ addr = sio_get32();
+ sio_getc(); // skip .
+ key = sio_get32(); // key in %edi
+
+ sio_putc('\r'); sio_putc('\n');
+
+ msr = rdmsr(addr);
+ sio_put32(msr.hi);
+ sio_putc('.');
+ sio_put32(msr.lo);
+}
+
+static void serialice_write_msr(void)
+{
+ u32 addr, key;
+ msr_t msr;
+
+ // Format:
+ // *wc00000000.9c5a203a=00000000.00000000
+ addr = sio_get32();
+ sio_getc(); // skip .
+ key = sio_get32(); // read key in %edi
+ sio_getc(); // skip =
+ msr.hi = sio_get32();
+ sio_getc(); // skip .
+ msr.lo = sio_get32();
+
+#ifdef __ROMCC__
+ /* Cheat to avoid register outage */
+ wrmsr(addr, msr, 0x9c5a203a);
+#else
+ wrmsr(addr, msr);
+#endif
+}
+
+static void serialice_cpuinfo(void)
+{
+ u32 eax, ecx;
+ u32 reg32 = 0xdeadbeef;
+
+ // Format:
+ // --EAX--- --ECX---
+ // *ci00000000.00000000
+ eax = sio_get32();
+ sio_getc(); // skip .
+ ecx = sio_get32();
+
+ sio_putc('\r'); sio_putc('\n');
+
+ /* This code looks quite crappy but this way we don't
+ * have to worry about running out of registers if we
+ * occupy eax, ebx, ecx, edx at the same time
+ */
+// reg32 = cpuid_eax(eax, ecx);
+ sio_put32(reg32);
+ sio_putc('.');
+
+// reg32 = cpuid_ebx(eax, ecx);
+ sio_put32(reg32);
+ sio_putc('.');
+
+// reg32 = cpuid_ecx(eax, ecx);
+ sio_put32(reg32);
+ sio_putc('.');
+
+// reg32 = cpuid_edx(eax, ecx);
+ sio_put32(reg32);
+}
+
+static void serialice_mainboard(void)
+{
+ sio_putc('\r'); sio_putc('\n');
+
+ /* must be defined in mainboard/<boardname>.c */
+ sio_putstring(boardname);
+}
+
+static void serialice_version(void)
+{
+ sio_putstring("\nSerialICE v" VERSION " (" __DATE__ ")\n");
+}
+void serialice_main(void);
+
+void serialice_main(void)
+{
+ sio_init();
+ serialice_version();
+
+ while(1) {
+ u16 c;
+ sio_putstring("\n> ");
+
+ c = sio_getc();
+ if (c != '*')
+ continue;
+
+ c = sio_getc() << 8;
+ c |= sio_getc();
+
+ switch(c) {
+ case (('r' << 8)|'m'): // Read Memory *rm
+ serialice_read_memory();
+ break;
+ case (('w' << 8)|'m'): // Write Memory *wm
+ serialice_write_memory();
+ break;
+ case (('r' << 8)|'i'): // Read IO *ri
+ serialice_read_io();
+ break;
+ case (('w' << 8)|'i'): // Write IO *wi
+ serialice_write_io();
+ break;
+ case (('r' << 8)|'c'): // Read CPU MSR *rc
+ serialice_read_msr();
+ break;
+ case (('w' << 8)|'c'): // Write CPU MSR *wc
+ serialice_write_msr();
+ break;
+ case (('c' << 8)|'i'): // Read CPUID *ci
+ serialice_cpuinfo();
+ break;
+ case (('m' << 8)|'b'): // Read mainboard type *mb
+ serialice_mainboard();
+ break;
+ case (('v' << 8)|'i'): // Read version info *vi
+ serialice_version();
+ break;
+ default:
+ sio_putstring("ERROR\n");
+ break;
+ }
+ }
+
+ // Never get here:
+}
diff --git a/src/lib/serialice/serialice.h b/src/lib/serialice/serialice.h
new file mode 100644
index 0000000..1d01849
--- /dev/null
+++ b/src/lib/serialice/serialice.h
@@ -0,0 +1,31 @@
+/*
+ * SerialICE
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SERIALICE_H
+#define SERIALICE_H
+
+#include "config.h"
+
+#define ECHO_MODE 1
+
+#define VERSION "42"
+#define SIO_SPEED 115200
+#define SIO_PORT 0x3f8
+
+#endif
1
0
05 Jun '12
Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1095
-gerrit
commit dd11f547bb130790fbe1d0f8b17591be50faf6ec
Author: Rudolf Marek <r.marek(a)assembler.cz>
Date: Tue Jun 5 00:27:54 2012 +0200
Add MSR support for serialICE.
Adds MSR support forwarding, no password key yet, cpuid is missing.
Change-Id: Ib33f91839d2a1b07314dc4b0f6aead00c47f1b08
Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz>
---
src/include/cpu/x86/msr.h | 15 ++++++++++++++-
1 files changed, 14 insertions(+), 1 deletions(-)
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 40926df..0ba3910 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -16,7 +16,7 @@ static void wrmsr(unsigned long index, msr_t msr)
}
#else
-
+#include <serialice_host.h>
typedef struct msr_struct
{
unsigned lo;
@@ -42,21 +42,34 @@ typedef struct msrinit_struct
static inline __attribute__((always_inline)) msr_t rdmsr(unsigned index)
{
msr_t result;
+#if defined(__PRE_RAM__)
__asm__ __volatile__ (
"rdmsr"
: "=a" (result.lo), "=d" (result.hi)
: "c" (index)
);
return result;
+
+#else
+ int64_t ret = serialice_rdmsr(index, 0);
+ result.lo = ret & 0xffffffff;
+ result.hi = (ret >> 32) & 0xffffffff;
+ return result;
+#endif
}
static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t msr)
{
+
+#if defined(__PRE_RAM__) || CONFIG_ULINUX == 0
__asm__ __volatile__ (
"wrmsr"
: /* No outputs */
: "c" (index), "a" (msr.lo), "d" (msr.hi)
);
+#else
+ serialice_wrmsr ((((uint64_t) msr.hi) << 32) | msr.lo, index, 0);
+#endif
}
#endif /* __ROMCC__ */
1
0
New patch to review for coreboot: d602fc7 Add host side of serialICE which uses ulinux.
by Rudolf Marek 05 Jun '12
by Rudolf Marek 05 Jun '12
05 Jun '12
Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1094
-gerrit
commit d602fc79e963057e4db00a4e2dca38d48ad6b484
Author: Rudolf Marek <r.marek(a)assembler.cz>
Date: Tue Jun 5 00:26:06 2012 +0200
Add host side of serialICE which uses ulinux.
This is copied from serialICE qemu and strtoul is from libpayload. this must be fixed
maybe into string.h?
Change-Id: If71737e6866c5c4dd62b9c26c676686ebfd20bcc
Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz>
---
src/include/serialice_host.h | 66 ++++
src/lib/serialice_host.c | 676 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 742 insertions(+), 0 deletions(-)
diff --git a/src/include/serialice_host.h b/src/include/serialice_host.h
new file mode 100644
index 0000000..f099325
--- /dev/null
+++ b/src/include/serialice_host.h
@@ -0,0 +1,66 @@
+/*
+ * QEMU PC System Emulator
+ *
+ * Copyright (c) 2009 coresystems GmbH
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef SERIALICE_HH
+#define SERIALICE_HH
+#include <stdint.h>
+extern const char *serialice_device;
+extern int serialice_active;
+
+void serialice_init(void);
+void serialice_exit(void);
+const char *serialice_lua_execute(const char *cmd);
+
+uint8_t serialice_inb(uint16_t port);
+uint16_t serialice_inw(uint16_t port);
+uint32_t serialice_inl(uint16_t port);
+
+void serialice_outb(uint8_t data, uint16_t port);
+void serialice_outw(uint16_t data, uint16_t port);
+void serialice_outl(uint32_t data, uint16_t port);
+
+uint8_t serialice_readb(uint32_t addr);
+uint16_t serialice_readw(uint32_t addr);
+uint32_t serialice_readl(uint32_t addr);
+
+void serialice_writeb(uint8_t data, uint32_t addr);
+void serialice_writew(uint16_t data, uint32_t addr);
+void serialice_writel(uint32_t data, uint32_t addr);
+
+uint64_t serialice_rdmsr(uint32_t addr, uint32_t key);
+void serialice_wrmsr(uint64_t data, uint32_t addr, uint32_t key);
+
+typedef struct {
+ uint32_t eax, ebx, ecx, edx;
+} cpuid_regs_t;
+
+cpuid_regs_t serialice_cpuid(uint32_t eax, uint32_t ecx);
+
+int serialice_handle_load(uint32_t addr, uint32_t * result,
+ unsigned int data_size);
+void serialice_log_load(int caught, uint32_t addr, uint32_t result,
+ unsigned int data_size);
+int serialice_handle_store(uint32_t addr, uint32_t val, unsigned int data_size);
+
+#endif
diff --git a/src/lib/serialice_host.c b/src/lib/serialice_host.c
new file mode 100644
index 0000000..4d318b2
--- /dev/null
+++ b/src/lib/serialice_host.c
@@ -0,0 +1,676 @@
+/*
+ * QEMU PC System Emulator
+ *
+ * Copyright (c) 2009 coresystems GmbH
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* Indented with:
+ * gnuindent -npro -kr -i4 -nut -bap -sob -l80 -ss -ncs serialice.*
+ */
+
+/* System includes */
+#include <stdlib.h>
+#include <stdint.h>
+
+#include <string.h>
+#ifdef WIN32
+#include <windows.h>
+#include <conio.h>
+#else
+#include <termios.h>
+#endif
+
+#include <console/console.h>
+#include <serialice_host.h>
+#include <ulinux.h>
+
+const char *serialice_device = CONFIG_SERIALICE_HOST_DEV;
+
+/* Check that a character is in the valid range for the
+ given base
+*/
+
+//#warning "move this to string.h? got it from libpayload"
+
+#define UINT32_MAX 0xffffffffU
+static int _valid(char ch, int base)
+{
+ char end = (base > 9) ? '9' : '0' + (base - 1);
+
+ /* all bases will be some subset of the 0-9 range */
+
+ if (ch >= '0' && ch <= end)
+ return 1;
+
+ /* Bases > 11 will also have to match in the a-z range */
+
+ if (base > 11) {
+ if (tolower(ch) >= 'a' &&
+ tolower(ch) <= 'a' + (base - 11))
+ return 1;
+ }
+
+ return 0;
+}
+
+/* Return the "value" of the character in the given base */
+
+static int _offset(char ch, int base)
+{
+ if (ch >= '0' && ch <= '9')
+ return ch - '0';
+ else
+ return 10 + tolower(ch) - 'a';
+}
+
+/**
+ * Convert the initial portion of a string into an unsigned int
+ * @param ptr A pointer to the string to convert
+ * @param endptr A pointer to the unconverted part of the string
+ * @param base The base of the number to convert, or 0 for auto
+ * @return An unsigned integer representation of the string
+ */
+
+static unsigned long long strtoull(const char *ptr, char **endptr, unsigned int base)
+{
+ unsigned long long ret = 0;
+
+ if (endptr != NULL)
+ *endptr = (char *) ptr;
+
+ /* Purge whitespace */
+
+ for( ; *ptr && isspace(*ptr); ptr++);
+
+ if (!*ptr)
+ return 0;
+
+ /* Determine the base */
+
+ if (base == 0) {
+ if (ptr[0] == '0' && (ptr[1] == 'x' || ptr[1] == 'X'))
+ base = 16;
+ else if (ptr[0] == '0') {
+ base = 8;
+ ptr++;
+ }
+ else
+ base = 10;
+ }
+
+ /* Base 16 allows the 0x on front - so skip over it */
+
+ if (base == 16) {
+ if (ptr[0] == '0' && (ptr[1] == 'x' || ptr[1] == 'X'))
+ ptr += 2;
+ }
+
+ /* If the first character isn't valid, then don't
+ * bother */
+
+ if (!*ptr || !_valid(*ptr, base))
+ return 0;
+
+ for( ; *ptr && _valid(*ptr, base); ptr++)
+ ret = (ret * base) + _offset(*ptr, base);
+
+ if (endptr != NULL)
+ *endptr = (char *) ptr;
+
+ return ret;
+}
+
+static unsigned long strtoul(const char *ptr, char **endptr, unsigned int base)
+{
+ unsigned long long val = strtoull(ptr, endptr, base);
+ if (val > UINT32_MAX) return UINT32_MAX;
+ return val;
+}
+
+#define SERIALICE_DEBUG 3
+#define BUFFER_SIZE 1024
+typedef struct {
+#ifdef WIN32
+ HANDLE fd;
+#else
+ int fd;
+#endif
+ char *buffer;
+ char *command;
+} SerialICEState;
+
+/* Make it static, so it works from start */
+static char bb[BUFFER_SIZE];
+static char cc[BUFFER_SIZE];
+
+static SerialICEState ss = {
+ .buffer = bb,
+ .command = cc,
+ };
+
+static SerialICEState *s = &ss;
+int serialice_active = 0;
+
+#ifndef WIN32
+static struct termios options;
+#endif
+
+/* SerialICE output loggers */
+
+#define LOG_IO 0
+#define LOG_MEMORY 1
+#define LOG_READ 0
+#define LOG_WRITE 2
+// these two are separate
+#define LOG_QEMU 4
+#define LOG_TARGET 8
+
+static void serialice_log(int flags, uint32_t data, uint32_t addr, int size)
+{
+ if ((flags & LOG_WRITE) && (flags & LOG_MEMORY)) {
+ printk(BIOS_INFO, "MEM WRITE: [%08x] %08x size %d\n", addr, data, size);
+ } else if (!(flags & LOG_WRITE) && (flags & LOG_MEMORY)) {
+ printk(BIOS_INFO, "MEM READ: [%08x] %08x size %d\n", addr, data, size);
+ } else if ((flags & LOG_WRITE) && !(flags & LOG_MEMORY)) {
+ printk(BIOS_INFO, "IO WRITE: [%08x] %08x size %d\n", addr, data, size);
+ } else { // if (!(flags & LOG_WRITE) && !(flags & LOG_MEMORY))
+ printk(BIOS_INFO, "IO READ: [%08x] %08x size %d\n", addr, data, size);
+ }
+
+}
+
+static void serialice_msr_log(int flags, uint32_t addr, uint32_t hi,
+ uint32_t lo, int filtered)
+{
+
+ if (flags & LOG_WRITE) {
+ printk(BIOS_INFO, "MSR READ: [%08x] %08x%08x\n", addr,hi,lo);
+ } else { // if (!(flags & LOG_WRITE))
+ printk(BIOS_INFO, "MSR WRITE: [%08x] %08x%08x\n", addr,hi,lo);
+ }
+
+}
+
+static void serialice_cpuid_log(uint32_t eax, uint32_t ecx, cpuid_regs_t res,
+ int filtered)
+{
+
+ printk(BIOS_INFO, "CPUID todo\n");
+}
+
+// **************************************************************************
+// low level communication with the SerialICE shell (serial communication)
+
+static int serialice_read(SerialICEState * state, void *buf, size_t nbyte)
+{
+ int bytes_read = 0;
+
+ while (1) {
+#ifdef WIN32
+ int ret = 0;
+ ReadFile(state->fd, buf, nbyte - bytes_read, &ret, NULL);
+ if (!ret) {
+ break;
+ }
+#else
+ int ret = ulinux_read(state->fd, buf, nbyte - bytes_read);
+
+ if (ret == -1 && ulinux_errno == EINTR) {
+ continue;
+ }
+
+ if (ret == -1) {
+ break;
+ }
+#endif
+
+ bytes_read += ret;
+ buf += ret;
+
+ if (bytes_read >= (int)nbyte) {
+ break;
+ }
+ }
+
+ return bytes_read;
+}
+
+static int handshake_mode = 0;
+
+static int serialice_write(SerialICEState * state, const void *buf,
+ size_t nbyte)
+{
+ char *buffer = (char *)buf;
+ char c;
+ int i;
+ for (i = 0; i < (int)nbyte; i++) {
+#ifdef WIN32
+ int ret = 0;
+ while (ret == 0) {
+ WriteFile(state->fd, buffer + i, 1, &ret, NULL);
+ }
+ ret = 0;
+ while (ret == 0) {
+ ReadFile(state->fd, &c, 1, &ret, NULL);
+ }
+#else
+ while (ulinux_write(state->fd, buffer + i, 1) != 1) ;
+ while (ulinux_read(state->fd, &c, 1) != 1) ;
+#endif
+ if (c != buffer[i] && !handshake_mode) {
+ printk(BIOS_ERR, "Readback error! %x/%x\n", c, buffer[i]);
+ }
+ }
+
+ return nbyte;
+}
+
+static int serialice_wait_prompt(void)
+{
+ char buf[3];
+ int l;
+
+ l = serialice_read(s, buf, 3);
+
+ if (l == -1) {
+ perror("SerialICE: Could not read from target");
+ ulinux_exit(1);
+ }
+
+ while (buf[0] != '\n' || buf[1] != '>' || buf[2] != ' ') {
+ buf[0] = buf[1];
+ buf[1] = buf[2];
+ l = serialice_read(s, buf + 2, 1);
+ if (l == -1) {
+ perror("SerialICE: Could not read from target");
+ ulinux_exit(1);
+ }
+ }
+
+ return 0;
+}
+
+static void serialice_command(const char *command, int reply_len)
+{
+#if SERIALICE_DEBUG > 5
+ int i;
+#endif
+ int l;
+
+ if (!serialice_active) {
+ printk(BIOS_ERR, "SerialICE not ready yet (ignoring)\n");
+ return;
+ }
+
+ serialice_wait_prompt();
+
+ serialice_write(s, command, strlen(command));
+
+ memset(s->buffer, 0, reply_len + 1); // clear enough of the buffer
+
+ l = serialice_read(s, s->buffer, reply_len);
+
+ if (l == -1) {
+ perror("SerialICE: Could not read from target");
+ ulinux_exit(1);
+ }
+ // compensate for CR on the wire. Needed on Win32
+ if (s->buffer[0] == '\r') {
+ memmove(s->buffer, s->buffer + 1, reply_len);
+ serialice_read(s, s->buffer + reply_len - 1, 1);
+ }
+
+ if (l != reply_len) {
+ printk(BIOS_ERR, "SerialICE: command was not answered sufficiently: "
+ "(%d/%d bytes)\n'%s'\n", l, reply_len, s->buffer);
+ ulinux_exit(1);
+ }
+#if SERIALICE_DEBUG > 5
+ for (i = 0; i < reply_len; i++) {
+ printk(BIOS_ERR, "%02x ", s->buffer[i]);
+ }
+ printk(BIOS_ERR, "\n");
+#endif
+}
+
+// **************************************************************************
+// high level communication with the SerialICE shell
+
+static void serialice_get_version(void)
+{
+ int len = 0;
+ printk(BIOS_INFO, "SerialICE: Version.....: ");
+ serialice_command("*vi", 0);
+
+ memset(s->buffer, 0, BUFFER_SIZE);
+ serialice_read(s, s->buffer, 1);
+ serialice_read(s, s->buffer, 1);
+ while (s->buffer[len++] != '\n') {
+ serialice_read(s, s->buffer + len, 1);
+ }
+ s->buffer[len - 1] = '\0';
+
+ printk(BIOS_INFO, "%s\n", s->buffer);
+}
+
+static void serialice_get_mainboard(void)
+{
+}
+
+uint8_t serialice_inb(uint16_t port)
+{
+ uint8_t ret;
+
+ sprintf(s->command, "*ri%04x.b", port);
+ // command read back: "\n00" (3 characters)
+ serialice_command(s->command, 3);
+ ret = (uint8_t) strtoul(s->buffer + 1, (char **)NULL, 16);
+
+ serialice_log(LOG_READ | LOG_IO, ret, port, 1);
+
+ return ret;
+}
+
+uint16_t serialice_inw(uint16_t port)
+{
+ uint16_t ret;
+
+ sprintf(s->command, "*ri%04x.w", port);
+ // command read back: "\n0000" (5 characters)
+ serialice_command(s->command, 5);
+ ret = (uint16_t) strtoul(s->buffer + 1, (char **)NULL, 16);
+
+ serialice_log(LOG_READ | LOG_IO, ret, port, 2);
+
+ return ret;
+}
+
+uint32_t serialice_inl(uint16_t port)
+{
+ uint32_t ret;
+
+ sprintf(s->command, "*ri%04x.l", port);
+ // command read back: "\n00000000" (9 characters)
+ serialice_command(s->command, 9);
+ ret = (uint32_t) strtoul(s->buffer + 1, (char **)NULL, 16);
+
+ serialice_log(LOG_READ | LOG_IO, ret, port, 4);
+
+ return ret;
+}
+
+void serialice_outb(uint8_t data, uint16_t port)
+{
+ serialice_log(LOG_WRITE | LOG_IO, data, port, 1);
+
+ sprintf(s->command, "*wi%04x.b=%02x", port, data);
+ serialice_command(s->command, 0);
+}
+
+void serialice_outw(uint16_t data, uint16_t port)
+{
+ serialice_log(LOG_WRITE | LOG_IO, data, port, 2);
+
+ sprintf(s->command, "*wi%04x.w=%04x", port, data);
+ serialice_command(s->command, 0);
+}
+
+void serialice_outl(uint32_t data, uint16_t port)
+{
+ serialice_log(LOG_WRITE | LOG_IO, data, port, 4);
+
+ sprintf(s->command, "*wi%04x.l=%08x", port, data);
+ serialice_command(s->command, 0);
+}
+
+uint8_t serialice_readb(uint32_t addr)
+{
+ uint8_t ret;
+ sprintf(s->command, "*rm%08x.b", addr);
+ // command read back: "\n00" (3 characters)
+ serialice_command(s->command, 3);
+ ret = (uint8_t) strtoul(s->buffer + 1, (char **)NULL, 16);
+ serialice_log(LOG_READ | LOG_MEMORY, ret, addr, 1);
+
+ return ret;
+}
+
+uint16_t serialice_readw(uint32_t addr)
+{
+ uint16_t ret;
+ sprintf(s->command, "*rm%08x.w", addr);
+ // command read back: "\n0000" (5 characters)
+ serialice_command(s->command, 5);
+ ret = (uint16_t) strtoul(s->buffer + 1, (char **)NULL, 16);
+ serialice_log(LOG_READ | LOG_MEMORY, ret, addr, 2);
+
+ return ret;
+}
+
+uint32_t serialice_readl(uint32_t addr)
+{
+ uint32_t ret;
+ sprintf(s->command, "*rm%08x.l", addr);
+ // command read back: "\n00000000" (9 characters)
+ serialice_command(s->command, 9);
+ ret = (uint32_t) strtoul(s->buffer + 1, (char **)NULL, 16);
+ serialice_log(LOG_READ | LOG_MEMORY, ret, addr, 4);
+
+ return ret;
+}
+
+void serialice_writeb(uint8_t data, uint32_t addr)
+{
+ serialice_log(LOG_WRITE | LOG_MEMORY, data, addr, 1);
+ sprintf(s->command, "*wm%08x.b=%02x", addr, data);
+ serialice_command(s->command, 0);
+}
+
+void serialice_writew(uint16_t data, uint32_t addr)
+{
+ serialice_log(LOG_WRITE | LOG_MEMORY, data, addr, 2);
+ sprintf(s->command, "*wm%08x.w=%04x", addr, data);
+ serialice_command(s->command, 0);
+}
+
+void serialice_writel(uint32_t data, uint32_t addr)
+{
+ serialice_log(LOG_WRITE | LOG_MEMORY, data, addr, 4);
+ sprintf(s->command, "*wm%08x.l=%08x", addr, data);
+ serialice_command(s->command, 0);
+}
+
+uint64_t serialice_rdmsr(uint32_t addr, uint32_t key)
+{
+ uint32_t hi, lo;
+ uint64_t ret;
+ int filtered = 0;
+
+ sprintf(s->command, "*rc%08x.%08x", addr, key);
+
+ // command read back: "\n00000000.00000000" (18 characters)
+ serialice_command(s->command, 18);
+
+ s->buffer[9] = 0; // . -> \0
+ hi = (uint32_t) strtoul(s->buffer + 1, (char **)NULL, 16);
+ lo = (uint32_t) strtoul(s->buffer + 10, (char **)NULL, 16);
+
+ ret = hi;
+ ret <<= 32;
+ ret |= lo;
+
+ serialice_msr_log(LOG_READ, addr, hi, lo, filtered);
+
+ return ret;
+}
+
+void serialice_wrmsr(uint64_t data, uint32_t addr, uint32_t key)
+{
+ uint32_t hi, lo;
+ int filtered = 0;
+
+ hi = (data >> 32);
+ lo = (data & 0xffffffff);
+
+ if (!filtered) {
+ sprintf(s->command, "*wc%08x.%08x=%08x.%08x", addr, key, hi, lo);
+ serialice_command(s->command, 0);
+ }
+
+ serialice_msr_log(LOG_WRITE, addr, hi, lo, filtered);
+}
+
+cpuid_regs_t serialice_cpuid(uint32_t eax, uint32_t ecx)
+{
+ cpuid_regs_t ret;
+
+ ret.eax = eax;
+ ret.ebx = 0; // either set by filter or by target
+ ret.ecx = ecx;
+ ret.edx = 0; // either set by filter or by target
+
+ sprintf(s->command, "*ci%08x.%08x", eax, ecx);
+
+ // command read back: "\n000006f2.00000000.00001234.12340324"
+ // (36 characters)
+ serialice_command(s->command, 36);
+
+ s->buffer[9] = 0; // . -> \0
+ s->buffer[18] = 0; // . -> \0
+ s->buffer[27] = 0; // . -> \0
+ ret.eax = (uint32_t) strtoul(s->buffer + 1, (char **)NULL, 16);
+ ret.ebx = (uint32_t) strtoul(s->buffer + 10, (char **)NULL, 16);
+ ret.ecx = (uint32_t) strtoul(s->buffer + 19, (char **)NULL, 16);
+ ret.edx = (uint32_t) strtoul(s->buffer + 28, (char **)NULL, 16);
+
+ serialice_cpuid_log(eax, ecx, ret, 0);
+
+ return ret;
+}
+
+// **************************************************************************
+// initialization and exit
+
+void serialice_init(void)
+{
+ printk(BIOS_INFO, "SerialICE: Open connection to target hardware...\n");
+
+ if (serialice_device == NULL) {
+ printk(BIOS_INFO, "You need to specify a serial device to use SerialICE.\n");
+ ulinux_exit(1);
+ }
+#ifdef WIN32
+ s->fd = CreateFile(serialice_device, GENERIC_READ | GENERIC_WRITE,
+ 0, NULL, OPEN_EXISTING, 0, NULL);
+
+ if (s->fd == INVALID_HANDLE_VALUE) {
+ perror("SerialICE: Could not connect to target TTY");
+ ulinux_exit(1);
+ }
+
+ DCB dcb;
+ if (!GetCommState(s->fd, &dcb)) {
+ perror("SerialICE: Could not load config for target TTY");
+ ulinux_exit(1);
+ }
+
+ dcb.BaudRate = CBR_115200;
+ dcb.ByteSize = 8;
+ dcb.Parity = NOPARITY;
+ dcb.StopBits = ONESTOPBIT;
+
+ if (!SetCommState(s->fd, &dcb)) {
+ perror("SerialICE: Could not store config for target TTY");
+ ulinux_exit(1);
+ }
+#else
+ s->fd = ulinux_open(serialice_device, O_RDWR | O_NOCTTY | O_NONBLOCK);
+
+ if (s->fd == -1) {
+ perror("SerialICE: Could not connect to target TTY");
+ ulinux_exit(1);
+ }
+
+ if (ulinux_ioctl(s->fd, TIOCEXCL) == -1) {
+ perror("SerialICE: TTY not exclusively available");
+ ulinux_exit(1);
+ }
+
+ if (ulinux_fcntl(s->fd, F_SETFL, 0) == -1) {
+ perror("SerialICE: Could not switch to blocking I/O");
+ ulinux_exit(1);
+ }
+
+ if (ulinux_tcgetattr(s->fd, &options) == -1) {
+ perror("SerialICE: Could not get TTY attributes");
+ ulinux_exit(1);
+ }
+
+ ulinux_cfsetispeed(&options, B115200);
+ ulinux_cfsetospeed(&options, B115200);
+
+ /* set raw input, 1 second timeout */
+ options.c_cflag |= (CLOCAL | CREAD);
+ options.c_lflag &= ~(ICANON | ECHO | ECHOE | ISIG);
+ options.c_oflag &= ~OPOST;
+ options.c_iflag |= IGNCR;
+ options.c_cc[VMIN] = 0;
+ options.c_cc[VTIME] = 100;
+
+ ulinux_tcsetattr(s->fd, TCSANOW, &options);
+
+ ulinux_tcflush(s->fd, TCIOFLUSH);
+#endif
+
+ s->buffer = bb;
+ s->command = cc;
+
+ printk(BIOS_INFO, "SerialICE: Waiting for handshake with target... ");
+
+ handshake_mode = 1; // Readback errors are to be expected in this phase.
+
+ /* Trigger a prompt */
+ serialice_write(s, "\n\n\n\n", 4);
+ serialice_write(s, "\n\n\n\n", 4);
+
+ /* ... and wait for it to appear */
+ if (serialice_wait_prompt() == 0) {
+ printk(BIOS_INFO, "target alive!\n");
+ serialice_active = 1;
+ } else {
+ printk(BIOS_INFO, "target not ok!\n");
+ ulinux_exit(1);
+ }
+
+ /* Each serialice_command() waits for a prompt, so trigger one for the
+ * first command, as we consumed the last one for the handshake
+ */
+ serialice_write(s, "@", 1);
+
+ handshake_mode = 0; // from now on, warn about readback errors.
+
+ serialice_get_version();
+
+ serialice_get_mainboard();
+
+ /* Let the rest of Qemu know we're alive */
+}
+
1
0
05 Jun '12
Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1093
-gerrit
commit a4e7fb13b611d5d3f14b3a21f34d19939e5e62ed
Author: Rudolf Marek <r.marek(a)assembler.cz>
Date: Tue Jun 5 00:24:14 2012 +0200
random hack in qemu target
Not for merge, just simple hack to use userspace coreboot even without serialice (comment out serialice_init).
if serialice_init is commented all IO will fail but one can test the memory access/workflow more faster.
Change-Id: I0c8f8619fa054af72cca76a0825fd00a4d301c3d
Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz>
---
src/mainboard/emulation/qemu-x86/northbridge.c | 8 ++++++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c
index f1669bb..d701b8c 100644
--- a/src/mainboard/emulation/qemu-x86/northbridge.c
+++ b/src/mainboard/emulation/qemu-x86/northbridge.c
@@ -11,6 +11,7 @@
#include "chip.h"
#include <delay.h>
#include <smbios.h>
+#include <ulinux.h>
#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
@@ -38,7 +39,8 @@ static void cpu_pci_domain_set_resources(device_t dev)
unsigned long tomk = 0, tolmk;
int idx;
- tomk = qemu_get_memory_size();
+// tomk = qemu_get_memory_size();
+ tomk = 16*1024;
printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n",
tomk, tomk / 1024);
@@ -58,8 +60,10 @@ static void cpu_pci_domain_set_resources(device_t dev)
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
+#if CONFIG_ULINUX
+ ulinux_mmap(high_tables_base, high_tables_size);
+#endif
#endif
-
assign_resources(dev->link_list);
}
1
0
05 Jun '12
Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1092
-gerrit
commit 922b3c627bd573513b26fcb47197b01e77bfee0b
Author: Rudolf Marek <r.marek(a)assembler.cz>
Date: Tue Jun 5 00:22:39 2012 +0200
leave frame pointers
Do not strip out frame pointer, handy for debugging (this needs to be somehow more polished
but one gets the idea).
Change-Id: I4f96ca321a175c941c55846fd2471ef5cc4897af
Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz>
---
Makefile.inc | 16 +++++++++++++++-
src/arch/x86/Makefile.inc | 5 +++++
2 files changed, 20 insertions(+), 1 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index 176ff67..f3e87cc 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -61,8 +61,15 @@ subdirs-y += site-local
# Add source classes and their build options
classes-y := ramstage romstage driver smm
-romstage-c-ccopts:=-D__PRE_RAM__
+
+ifeq ($(CONFIG_ULINUX),y)
+stack_opt := -fomit-frame-pointer
+ramstage-c-ccopts:= -fstack-protector-all
+endif
+
+romstage-c-ccopts:=-D__PRE_RAM__ $(stack_opt)
romstage-S-ccopts:=-D__PRE_RAM__
+
ifeq ($(CONFIG_TRACE),y)
ramstage-c-ccopts:= -finstrument-functions
endif
@@ -163,7 +170,14 @@ CFLAGS += -Wstrict-aliasing -Wshadow
ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y)
CFLAGS += -Werror
endif
+
+ifeq ($(CONFIG_ULINUX),n)
CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
+endif
+
+ifeq ($(CONFIG_ULINUX),y)
+CFLAGS += -fno-common -ffreestanding -fno-builtin
+endif
additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/options
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9739555..dc7a7a0 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -208,7 +208,12 @@ else
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
@printf " CC romstage.inc\n"
+ifeq ($(CONFIG_ULINUX),y)
+ $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -fomit-frame-pointer -I$(src) -I. -I$(obj) -c -S $< -o $@
+endif
+ifeq ($(CONFIG_ULINUX),n)
$(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
+endif
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
@printf " POST romstage.inc\n"
1
0
05 Jun '12
Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1091
-gerrit
commit f6bf6c4303d62ae75098433a395b65c34d31aba3
Author: Rudolf Marek <r.marek(a)assembler.cz>
Date: Tue Jun 5 00:21:10 2012 +0200
valgrind support for malloc()
Demo valgrind support, need some more work as the red zone regions overlap a bit
but it is capable of reporting errors even now. This needs to be fixed...
Change-Id: I4999b70e6617b5328792ddef5041800668dd2ae4
Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz>
---
src/include/memcheck.h | 287 ++++
src/include/valgrind.h | 4037 ++++++++++++++++++++++++++++++++++++++++++++++++
src/lib/malloc.c | 10 +-
3 files changed, 4331 insertions(+), 3 deletions(-)
diff --git a/src/include/memcheck.h b/src/include/memcheck.h
new file mode 100644
index 0000000..68474b4
--- /dev/null
+++ b/src/include/memcheck.h
@@ -0,0 +1,287 @@
+
+/*
+ ----------------------------------------------------------------
+
+ Notice that the following BSD-style license applies to this one
+ file (memcheck.h) only. The rest of Valgrind is licensed under the
+ terms of the GNU General Public License, version 2, unless
+ otherwise indicated. See the COPYING file in the source
+ distribution for details.
+
+ ----------------------------------------------------------------
+
+ This file is part of MemCheck, a heavyweight Valgrind tool for
+ detecting memory errors.
+
+ Copyright (C) 2000-2011 Julian Seward. All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. The origin of this software must not be misrepresented; you must
+ not claim that you wrote the original software. If you use this
+ software in a product, an acknowledgment in the product
+ documentation would be appreciated but is not required.
+
+ 3. Altered source versions must be plainly marked as such, and must
+ not be misrepresented as being the original software.
+
+ 4. The name of the author may not be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ ----------------------------------------------------------------
+
+ Notice that the above BSD-style license applies to this one file
+ (memcheck.h) only. The entire rest of Valgrind is licensed under
+ the terms of the GNU General Public License, version 2. See the
+ COPYING file in the source distribution for details.
+
+ ----------------------------------------------------------------
+*/
+
+
+#ifndef __MEMCHECK_H
+#define __MEMCHECK_H
+
+
+/* This file is for inclusion into client (your!) code.
+
+ You can use these macros to manipulate and query memory permissions
+ inside your own programs.
+
+ See comment near the top of valgrind.h on how to use them.
+*/
+
+#include "valgrind.h"
+
+/* !! ABIWARNING !! ABIWARNING !! ABIWARNING !! ABIWARNING !!
+ This enum comprises an ABI exported by Valgrind to programs
+ which use client requests. DO NOT CHANGE THE ORDER OF THESE
+ ENTRIES, NOR DELETE ANY -- add new ones at the end. */
+typedef
+ enum {
+ VG_USERREQ__MAKE_MEM_NOACCESS = VG_USERREQ_TOOL_BASE('M','C'),
+ VG_USERREQ__MAKE_MEM_UNDEFINED,
+ VG_USERREQ__MAKE_MEM_DEFINED,
+ VG_USERREQ__DISCARD,
+ VG_USERREQ__CHECK_MEM_IS_ADDRESSABLE,
+ VG_USERREQ__CHECK_MEM_IS_DEFINED,
+ VG_USERREQ__DO_LEAK_CHECK,
+ VG_USERREQ__COUNT_LEAKS,
+
+ VG_USERREQ__GET_VBITS,
+ VG_USERREQ__SET_VBITS,
+
+ VG_USERREQ__CREATE_BLOCK,
+
+ VG_USERREQ__MAKE_MEM_DEFINED_IF_ADDRESSABLE,
+
+ /* Not next to VG_USERREQ__COUNT_LEAKS because it was added later. */
+ VG_USERREQ__COUNT_LEAK_BLOCKS,
+
+ /* This is just for memcheck's internal use - don't use it */
+ _VG_USERREQ__MEMCHECK_RECORD_OVERLAP_ERROR
+ = VG_USERREQ_TOOL_BASE('M','C') + 256
+ } Vg_MemCheckClientRequest;
+
+
+
+/* Client-code macros to manipulate the state of memory. */
+
+/* Mark memory at _qzz_addr as unaddressable for _qzz_len bytes. */
+#define VALGRIND_MAKE_MEM_NOACCESS(_qzz_addr,_qzz_len) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \
+ VG_USERREQ__MAKE_MEM_NOACCESS, \
+ (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+/* Similarly, mark memory at _qzz_addr as addressable but undefined
+ for _qzz_len bytes. */
+#define VALGRIND_MAKE_MEM_UNDEFINED(_qzz_addr,_qzz_len) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \
+ VG_USERREQ__MAKE_MEM_UNDEFINED, \
+ (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+/* Similarly, mark memory at _qzz_addr as addressable and defined
+ for _qzz_len bytes. */
+#define VALGRIND_MAKE_MEM_DEFINED(_qzz_addr,_qzz_len) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \
+ VG_USERREQ__MAKE_MEM_DEFINED, \
+ (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+/* Similar to VALGRIND_MAKE_MEM_DEFINED except that addressability is
+ not altered: bytes which are addressable are marked as defined,
+ but those which are not addressable are left unchanged. */
+#define VALGRIND_MAKE_MEM_DEFINED_IF_ADDRESSABLE(_qzz_addr,_qzz_len) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \
+ VG_USERREQ__MAKE_MEM_DEFINED_IF_ADDRESSABLE, \
+ (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+/* Create a block-description handle. The description is an ascii
+ string which is included in any messages pertaining to addresses
+ within the specified memory range. Has no other effect on the
+ properties of the memory range. */
+#define VALGRIND_CREATE_BLOCK(_qzz_addr,_qzz_len, _qzz_desc) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \
+ VG_USERREQ__CREATE_BLOCK, \
+ (_qzz_addr), (_qzz_len), (_qzz_desc), \
+ 0, 0)
+
+/* Discard a block-description-handle. Returns 1 for an
+ invalid handle, 0 for a valid handle. */
+#define VALGRIND_DISCARD(_qzz_blkindex) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \
+ VG_USERREQ__DISCARD, \
+ 0, (_qzz_blkindex), 0, 0, 0)
+
+
+/* Client-code macros to check the state of memory. */
+
+/* Check that memory at _qzz_addr is addressable for _qzz_len bytes.
+ If suitable addressibility is not established, Valgrind prints an
+ error message and returns the address of the first offending byte.
+ Otherwise it returns zero. */
+#define VALGRIND_CHECK_MEM_IS_ADDRESSABLE(_qzz_addr,_qzz_len) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \
+ VG_USERREQ__CHECK_MEM_IS_ADDRESSABLE, \
+ (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+/* Check that memory at _qzz_addr is addressable and defined for
+ _qzz_len bytes. If suitable addressibility and definedness are not
+ established, Valgrind prints an error message and returns the
+ address of the first offending byte. Otherwise it returns zero. */
+#define VALGRIND_CHECK_MEM_IS_DEFINED(_qzz_addr,_qzz_len) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \
+ VG_USERREQ__CHECK_MEM_IS_DEFINED, \
+ (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+/* Use this macro to force the definedness and addressibility of an
+ lvalue to be checked. If suitable addressibility and definedness
+ are not established, Valgrind prints an error message and returns
+ the address of the first offending byte. Otherwise it returns
+ zero. */
+#define VALGRIND_CHECK_VALUE_IS_DEFINED(__lvalue) \
+ VALGRIND_CHECK_MEM_IS_DEFINED( \
+ (volatile unsigned char *)&(__lvalue), \
+ (unsigned long)(sizeof (__lvalue)))
+
+
+/* Do a full memory leak check (like --leak-check=full) mid-execution. */
+#define VALGRIND_DO_LEAK_CHECK \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DO_LEAK_CHECK, \
+ 0, 0, 0, 0, 0)
+
+/* Same as VALGRIND_DO_LEAK_CHECK but only showing the entries for
+ which there was an increase in leaked bytes or leaked nr of blocks
+ since the previous leak search. */
+#define VALGRIND_DO_ADDED_LEAK_CHECK \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DO_LEAK_CHECK, \
+ 0, 1, 0, 0, 0)
+
+/* Same as VALGRIND_DO_ADDED_LEAK_CHECK but showing entries with
+ increased or decreased leaked bytes/blocks since previous leak
+ search. */
+#define VALGRIND_DO_CHANGED_LEAK_CHECK \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DO_LEAK_CHECK, \
+ 0, 2, 0, 0, 0)
+
+/* Do a summary memory leak check (like --leak-check=summary) mid-execution. */
+#define VALGRIND_DO_QUICK_LEAK_CHECK \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DO_LEAK_CHECK, \
+ 1, 0, 0, 0, 0)
+
+/* Return number of leaked, dubious, reachable and suppressed bytes found by
+ all previous leak checks. They must be lvalues. */
+#define VALGRIND_COUNT_LEAKS(leaked, dubious, reachable, suppressed) \
+ /* For safety on 64-bit platforms we assign the results to private
+ unsigned long variables, then assign these to the lvalues the user
+ specified, which works no matter what type 'leaked', 'dubious', etc
+ are. We also initialise '_qzz_leaked', etc because
+ VG_USERREQ__COUNT_LEAKS doesn't mark the values returned as
+ defined. */ \
+ { \
+ unsigned long _qzz_leaked = 0, _qzz_dubious = 0; \
+ unsigned long _qzz_reachable = 0, _qzz_suppressed = 0; \
+ VALGRIND_DO_CLIENT_REQUEST_STMT( \
+ VG_USERREQ__COUNT_LEAKS, \
+ &_qzz_leaked, &_qzz_dubious, \
+ &_qzz_reachable, &_qzz_suppressed, 0); \
+ leaked = _qzz_leaked; \
+ dubious = _qzz_dubious; \
+ reachable = _qzz_reachable; \
+ suppressed = _qzz_suppressed; \
+ }
+
+/* Return number of leaked, dubious, reachable and suppressed bytes found by
+ all previous leak checks. They must be lvalues. */
+#define VALGRIND_COUNT_LEAK_BLOCKS(leaked, dubious, reachable, suppressed) \
+ /* For safety on 64-bit platforms we assign the results to private
+ unsigned long variables, then assign these to the lvalues the user
+ specified, which works no matter what type 'leaked', 'dubious', etc
+ are. We also initialise '_qzz_leaked', etc because
+ VG_USERREQ__COUNT_LEAKS doesn't mark the values returned as
+ defined. */ \
+ { \
+ unsigned long _qzz_leaked = 0, _qzz_dubious = 0; \
+ unsigned long _qzz_reachable = 0, _qzz_suppressed = 0; \
+ VALGRIND_DO_CLIENT_REQUEST_STMT( \
+ VG_USERREQ__COUNT_LEAK_BLOCKS, \
+ &_qzz_leaked, &_qzz_dubious, \
+ &_qzz_reachable, &_qzz_suppressed, 0); \
+ leaked = _qzz_leaked; \
+ dubious = _qzz_dubious; \
+ reachable = _qzz_reachable; \
+ suppressed = _qzz_suppressed; \
+ }
+
+
+/* Get the validity data for addresses [zza..zza+zznbytes-1] and copy it
+ into the provided zzvbits array. Return values:
+ 0 if not running on valgrind
+ 1 success
+ 2 [previously indicated unaligned arrays; these are now allowed]
+ 3 if any parts of zzsrc/zzvbits are not addressable.
+ The metadata is not copied in cases 0, 2 or 3 so it should be
+ impossible to segfault your system by using this call.
+*/
+#define VALGRIND_GET_VBITS(zza,zzvbits,zznbytes) \
+ (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \
+ VG_USERREQ__GET_VBITS, \
+ (const char*)(zza), \
+ (char*)(zzvbits), \
+ (zznbytes), 0, 0)
+
+/* Set the validity data for addresses [zza..zza+zznbytes-1], copying it
+ from the provided zzvbits array. Return values:
+ 0 if not running on valgrind
+ 1 success
+ 2 [previously indicated unaligned arrays; these are now allowed]
+ 3 if any parts of zza/zzvbits are not addressable.
+ The metadata is not copied in cases 0, 2 or 3 so it should be
+ impossible to segfault your system by using this call.
+*/
+#define VALGRIND_SET_VBITS(zza,zzvbits,zznbytes) \
+ (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \
+ VG_USERREQ__SET_VBITS, \
+ (const char*)(zza), \
+ (const char*)(zzvbits), \
+ (zznbytes), 0, 0 )
+
+#endif
+
diff --git a/src/include/valgrind.h b/src/include/valgrind.h
new file mode 100644
index 0000000..ed53273
--- /dev/null
+++ b/src/include/valgrind.h
@@ -0,0 +1,4037 @@
+/* -*- c -*-
+ ----------------------------------------------------------------
+
+ Notice that the following BSD-style license applies to this one
+ file (valgrind.h) only. The rest of Valgrind is licensed under the
+ terms of the GNU General Public License, version 2, unless
+ otherwise indicated. See the COPYING file in the source
+ distribution for details.
+
+ ----------------------------------------------------------------
+
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2000-2011 Julian Seward. All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. The origin of this software must not be misrepresented; you must
+ not claim that you wrote the original software. If you use this
+ software in a product, an acknowledgment in the product
+ documentation would be appreciated but is not required.
+
+ 3. Altered source versions must be plainly marked as such, and must
+ not be misrepresented as being the original software.
+
+ 4. The name of the author may not be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ ----------------------------------------------------------------
+
+ Notice that the above BSD-style license applies to this one file
+ (valgrind.h) only. The entire rest of Valgrind is licensed under
+ the terms of the GNU General Public License, version 2. See the
+ COPYING file in the source distribution for details.
+
+ ----------------------------------------------------------------
+*/
+
+
+/* This file is for inclusion into client (your!) code.
+
+ You can use these macros to manipulate and query Valgrind's
+ execution inside your own programs.
+
+ The resulting executables will still run without Valgrind, just a
+ little bit more slowly than they otherwise would, but otherwise
+ unchanged. When not running on valgrind, each client request
+ consumes very few (eg. 7) instructions, so the resulting performance
+ loss is negligible unless you plan to execute client requests
+ millions of times per second. Nevertheless, if that is still a
+ problem, you can compile with the NVALGRIND symbol defined (gcc
+ -DNVALGRIND) so that client requests are not even compiled in. */
+
+#ifndef __VALGRIND_H
+#define __VALGRIND_H
+
+
+/* ------------------------------------------------------------------ */
+/* VERSION NUMBER OF VALGRIND */
+/* ------------------------------------------------------------------ */
+
+/* Specify Valgrind's version number, so that user code can
+ conditionally compile based on our version number. Note that these
+ were introduced at version 3.6 and so do not exist in version 3.5
+ or earlier. The recommended way to use them to check for "version
+ X.Y or later" is (eg)
+
+#if defined(__VALGRIND_MAJOR__) && defined(__VALGRIND_MINOR__) \
+ && (__VALGRIND_MAJOR__ > 3 \
+ || (__VALGRIND_MAJOR__ == 3 && __VALGRIND_MINOR__ >= 6))
+*/
+#define __VALGRIND_MAJOR__ 3
+#define __VALGRIND_MINOR__ 6
+
+
+///#include <stdarg.h>
+
+/* Nb: this file might be included in a file compiled with -ansi. So
+ we can't use C++ style "//" comments nor the "asm" keyword (instead
+ use "__asm__"). */
+
+/* Derive some tags indicating what the target platform is. Note
+ that in this file we're using the compiler's CPP symbols for
+ identifying architectures, which are different to the ones we use
+ within the rest of Valgrind. Note, __powerpc__ is active for both
+ 32 and 64-bit PPC, whereas __powerpc64__ is only active for the
+ latter (on Linux, that is).
+
+ Misc note: how to find out what's predefined in gcc by default:
+ gcc -Wp,-dM somefile.c
+*/
+#undef PLAT_x86_darwin
+#undef PLAT_amd64_darwin
+#undef PLAT_x86_win32
+#define PLAT_x86_linux
+#undef PLAT_amd64_linux
+#undef PLAT_ppc32_linux
+#undef PLAT_ppc64_linux
+#undef PLAT_arm_linux
+#undef PLAT_s390x_linux
+
+#define va_start(v,l) __builtin_va_start(v,l)
+#define va_end(v) __builtin_va_end(v)
+#define va_arg(v,l) __builtin_va_arg(v,l)
+typedef __builtin_va_list va_list;
+
+
+/* ------------------------------------------------------------------ */
+/* ARCHITECTURE SPECIFICS for SPECIAL INSTRUCTIONS. There is nothing */
+/* in here of use to end-users -- skip to the next section. */
+/* ------------------------------------------------------------------ */
+
+/*
+ * VALGRIND_DO_CLIENT_REQUEST(): a statement that invokes a Valgrind client
+ * request. Accepts both pointers and integers as arguments.
+ *
+ * VALGRIND_DO_CLIENT_REQUEST_STMT(): a statement that invokes a Valgrind
+ * client request that does not return a value.
+
+ * VALGRIND_DO_CLIENT_REQUEST_EXPR(): a C expression that invokes a Valgrind
+ * client request and whose value equals the client request result. Accepts
+ * both pointers and integers as arguments. Note that such calls are not
+ * necessarily pure functions -- they may have side effects.
+ */
+
+#define VALGRIND_DO_CLIENT_REQUEST(_zzq_rlval, _zzq_default, \
+ _zzq_request, _zzq_arg1, _zzq_arg2, \
+ _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ do { (_zzq_rlval) = VALGRIND_DO_CLIENT_REQUEST_EXPR((_zzq_default), \
+ (_zzq_request), (_zzq_arg1), (_zzq_arg2), \
+ (_zzq_arg3), (_zzq_arg4), (_zzq_arg5)); } while (0)
+
+#define VALGRIND_DO_CLIENT_REQUEST_STMT(_zzq_request, _zzq_arg1, \
+ _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ do { (void) VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \
+ (_zzq_request), (_zzq_arg1), (_zzq_arg2), \
+ (_zzq_arg3), (_zzq_arg4), (_zzq_arg5)); } while (0)
+
+#if defined(NVALGRIND)
+
+/* Define NVALGRIND to completely remove the Valgrind magic sequence
+ from the compiled code (analogous to NDEBUG's effects on
+ assert()) */
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ (_zzq_default)
+
+#else /* ! NVALGRIND */
+
+/* The following defines the magic code sequences which the JITter
+ spots and handles magically. Don't look too closely at them as
+ they will rot your brain.
+
+ The assembly code sequences for all architectures is in this one
+ file. This is because this file must be stand-alone, and we don't
+ want to have multiple files.
+
+ For VALGRIND_DO_CLIENT_REQUEST, we must ensure that the default
+ value gets put in the return slot, so that everything works when
+ this is executed not under Valgrind. Args are passed in a memory
+ block, and so there's no intrinsic limit to the number that could
+ be passed, but it's currently five.
+
+ The macro args are:
+ _zzq_rlval result lvalue
+ _zzq_default default value (result returned when running on real CPU)
+ _zzq_request request code
+ _zzq_arg1..5 request params
+
+ The other two macros are used to support function wrapping, and are
+ a lot simpler. VALGRIND_GET_NR_CONTEXT returns the value of the
+ guest's NRADDR pseudo-register and whatever other information is
+ needed to safely run the call original from the wrapper: on
+ ppc64-linux, the R2 value at the divert point is also needed. This
+ information is abstracted into a user-visible type, OrigFn.
+
+ VALGRIND_CALL_NOREDIR_* behaves the same as the following on the
+ guest, but guarantees that the branch instruction will not be
+ redirected: x86: call *%eax, amd64: call *%rax, ppc32/ppc64:
+ branch-and-link-to-r11. VALGRIND_CALL_NOREDIR is just text, not a
+ complete inline asm, since it needs to be combined with more magic
+ inline asm stuff to be useful.
+*/
+
+/* ------------------------- x86-{linux,darwin} ---------------- */
+
+#if defined(PLAT_x86_linux) || defined(PLAT_x86_darwin) \
+ || (defined(PLAT_x86_win32) && defined(__GNUC__))
+
+typedef
+ struct {
+ unsigned int nraddr; /* where's the code? */
+ }
+ OrigFn;
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ "roll $3, %%edi ; roll $13, %%edi\n\t" \
+ "roll $29, %%edi ; roll $19, %%edi\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ __extension__ \
+ ({volatile unsigned int _zzq_args[6]; \
+ volatile unsigned int _zzq_result; \
+ _zzq_args[0] = (unsigned int)(_zzq_request); \
+ _zzq_args[1] = (unsigned int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned int)(_zzq_arg5); \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %EDX = client_request ( %EAX ) */ \
+ "xchgl %%ebx,%%ebx" \
+ : "=d" (_zzq_result) \
+ : "a" (&_zzq_args[0]), "0" (_zzq_default) \
+ : "cc", "memory" \
+ ); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ volatile unsigned int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %EAX = guest_NRADDR */ \
+ "xchgl %%ecx,%%ecx" \
+ : "=a" (__addr) \
+ : \
+ : "cc", "memory" \
+ ); \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+#define VALGRIND_CALL_NOREDIR_EAX \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* call-noredir *%EAX */ \
+ "xchgl %%edx,%%edx\n\t"
+#endif /* PLAT_x86_linux || PLAT_x86_darwin || (PLAT_x86_win32 && __GNUC__) */
+
+/* ------------------------- x86-Win32 ------------------------- */
+
+#if defined(PLAT_x86_win32) && !defined(__GNUC__)
+
+typedef
+ struct {
+ unsigned int nraddr; /* where's the code? */
+ }
+ OrigFn;
+
+#if defined(_MSC_VER)
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ __asm rol edi, 3 __asm rol edi, 13 \
+ __asm rol edi, 29 __asm rol edi, 19
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ valgrind_do_client_request_expr((uintptr_t)(_zzq_default), \
+ (uintptr_t)(_zzq_request), (uintptr_t)(_zzq_arg1), \
+ (uintptr_t)(_zzq_arg2), (uintptr_t)(_zzq_arg3), \
+ (uintptr_t)(_zzq_arg4), (uintptr_t)(_zzq_arg5))
+
+static __inline uintptr_t
+valgrind_do_client_request_expr(uintptr_t _zzq_default, uintptr_t _zzq_request,
+ uintptr_t _zzq_arg1, uintptr_t _zzq_arg2,
+ uintptr_t _zzq_arg3, uintptr_t _zzq_arg4,
+ uintptr_t _zzq_arg5)
+{
+ volatile uintptr_t _zzq_args[6];
+ volatile unsigned int _zzq_result;
+ _zzq_args[0] = (uintptr_t)(_zzq_request);
+ _zzq_args[1] = (uintptr_t)(_zzq_arg1);
+ _zzq_args[2] = (uintptr_t)(_zzq_arg2);
+ _zzq_args[3] = (uintptr_t)(_zzq_arg3);
+ _zzq_args[4] = (uintptr_t)(_zzq_arg4);
+ _zzq_args[5] = (uintptr_t)(_zzq_arg5);
+ __asm { __asm lea eax, _zzq_args __asm mov edx, _zzq_default
+ __SPECIAL_INSTRUCTION_PREAMBLE
+ /* %EDX = client_request ( %EAX ) */
+ __asm xchg ebx,ebx
+ __asm mov _zzq_result, edx
+ }
+ return _zzq_result;
+}
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ volatile unsigned int __addr; \
+ __asm { __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %EAX = guest_NRADDR */ \
+ __asm xchg ecx,ecx \
+ __asm mov __addr, eax \
+ } \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+#define VALGRIND_CALL_NOREDIR_EAX ERROR
+
+#else
+#error Unsupported compiler.
+#endif
+
+#endif /* PLAT_x86_win32 */
+
+/* ------------------------ amd64-{linux,darwin} --------------- */
+
+#if defined(PLAT_amd64_linux) || defined(PLAT_amd64_darwin)
+
+typedef
+ struct {
+ unsigned long long int nraddr; /* where's the code? */
+ }
+ OrigFn;
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ "rolq $3, %%rdi ; rolq $13, %%rdi\n\t" \
+ "rolq $61, %%rdi ; rolq $51, %%rdi\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ __extension__ \
+ ({ volatile unsigned long long int _zzq_args[6]; \
+ volatile unsigned long long int _zzq_result; \
+ _zzq_args[0] = (unsigned long long int)(_zzq_request); \
+ _zzq_args[1] = (unsigned long long int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned long long int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned long long int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned long long int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned long long int)(_zzq_arg5); \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %RDX = client_request ( %RAX ) */ \
+ "xchgq %%rbx,%%rbx" \
+ : "=d" (_zzq_result) \
+ : "a" (&_zzq_args[0]), "0" (_zzq_default) \
+ : "cc", "memory" \
+ ); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ volatile unsigned long long int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %RAX = guest_NRADDR */ \
+ "xchgq %%rcx,%%rcx" \
+ : "=a" (__addr) \
+ : \
+ : "cc", "memory" \
+ ); \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+#define VALGRIND_CALL_NOREDIR_RAX \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* call-noredir *%RAX */ \
+ "xchgq %%rdx,%%rdx\n\t"
+#endif /* PLAT_amd64_linux || PLAT_amd64_darwin */
+
+/* ------------------------ ppc32-linux ------------------------ */
+
+#if defined(PLAT_ppc32_linux)
+
+typedef
+ struct {
+ unsigned int nraddr; /* where's the code? */
+ }
+ OrigFn;
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ "rlwinm 0,0,3,0,0 ; rlwinm 0,0,13,0,0\n\t" \
+ "rlwinm 0,0,29,0,0 ; rlwinm 0,0,19,0,0\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ \
+ __extension__ \
+ ({ unsigned int _zzq_args[6]; \
+ unsigned int _zzq_result; \
+ unsigned int* _zzq_ptr; \
+ _zzq_args[0] = (unsigned int)(_zzq_request); \
+ _zzq_args[1] = (unsigned int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned int)(_zzq_arg5); \
+ _zzq_ptr = _zzq_args; \
+ __asm__ volatile("mr 3,%1\n\t" /*default*/ \
+ "mr 4,%2\n\t" /*ptr*/ \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %R3 = client_request ( %R4 ) */ \
+ "or 1,1,1\n\t" \
+ "mr %0,3" /*result*/ \
+ : "=b" (_zzq_result) \
+ : "b" (_zzq_default), "b" (_zzq_ptr) \
+ : "cc", "memory", "r3", "r4"); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ unsigned int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %R3 = guest_NRADDR */ \
+ "or 2,2,2\n\t" \
+ "mr %0,3" \
+ : "=b" (__addr) \
+ : \
+ : "cc", "memory", "r3" \
+ ); \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+#define VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* branch-and-link-to-noredir *%R11 */ \
+ "or 3,3,3\n\t"
+#endif /* PLAT_ppc32_linux */
+
+/* ------------------------ ppc64-linux ------------------------ */
+
+#if defined(PLAT_ppc64_linux)
+
+typedef
+ struct {
+ unsigned long long int nraddr; /* where's the code? */
+ unsigned long long int r2; /* what tocptr do we need? */
+ }
+ OrigFn;
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ "rotldi 0,0,3 ; rotldi 0,0,13\n\t" \
+ "rotldi 0,0,61 ; rotldi 0,0,51\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ \
+ __extension__ \
+ ({ unsigned long long int _zzq_args[6]; \
+ unsigned long long int _zzq_result; \
+ unsigned long long int* _zzq_ptr; \
+ _zzq_args[0] = (unsigned long long int)(_zzq_request); \
+ _zzq_args[1] = (unsigned long long int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned long long int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned long long int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned long long int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned long long int)(_zzq_arg5); \
+ _zzq_ptr = _zzq_args; \
+ __asm__ volatile("mr 3,%1\n\t" /*default*/ \
+ "mr 4,%2\n\t" /*ptr*/ \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %R3 = client_request ( %R4 ) */ \
+ "or 1,1,1\n\t" \
+ "mr %0,3" /*result*/ \
+ : "=b" (_zzq_result) \
+ : "b" (_zzq_default), "b" (_zzq_ptr) \
+ : "cc", "memory", "r3", "r4"); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ unsigned long long int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %R3 = guest_NRADDR */ \
+ "or 2,2,2\n\t" \
+ "mr %0,3" \
+ : "=b" (__addr) \
+ : \
+ : "cc", "memory", "r3" \
+ ); \
+ _zzq_orig->nraddr = __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %R3 = guest_NRADDR_GPR2 */ \
+ "or 4,4,4\n\t" \
+ "mr %0,3" \
+ : "=b" (__addr) \
+ : \
+ : "cc", "memory", "r3" \
+ ); \
+ _zzq_orig->r2 = __addr; \
+ }
+
+#define VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* branch-and-link-to-noredir *%R11 */ \
+ "or 3,3,3\n\t"
+
+#endif /* PLAT_ppc64_linux */
+
+/* ------------------------- arm-linux ------------------------- */
+
+#if defined(PLAT_arm_linux)
+
+typedef
+ struct {
+ unsigned int nraddr; /* where's the code? */
+ }
+ OrigFn;
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ "mov r12, r12, ror #3 ; mov r12, r12, ror #13 \n\t" \
+ "mov r12, r12, ror #29 ; mov r12, r12, ror #19 \n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ \
+ __extension__ \
+ ({volatile unsigned int _zzq_args[6]; \
+ volatile unsigned int _zzq_result; \
+ _zzq_args[0] = (unsigned int)(_zzq_request); \
+ _zzq_args[1] = (unsigned int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned int)(_zzq_arg5); \
+ __asm__ volatile("mov r3, %1\n\t" /*default*/ \
+ "mov r4, %2\n\t" /*ptr*/ \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* R3 = client_request ( R4 ) */ \
+ "orr r10, r10, r10\n\t" \
+ "mov %0, r3" /*result*/ \
+ : "=r" (_zzq_result) \
+ : "r" (_zzq_default), "r" (&_zzq_args[0]) \
+ : "cc","memory", "r3", "r4"); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ unsigned int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* R3 = guest_NRADDR */ \
+ "orr r11, r11, r11\n\t" \
+ "mov %0, r3" \
+ : "=r" (__addr) \
+ : \
+ : "cc", "memory", "r3" \
+ ); \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+#define VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* branch-and-link-to-noredir *%R4 */ \
+ "orr r12, r12, r12\n\t"
+
+#endif /* PLAT_arm_linux */
+
+/* ------------------------ s390x-linux ------------------------ */
+
+#if defined(PLAT_s390x_linux)
+
+typedef
+ struct {
+ unsigned long long int nraddr; /* where's the code? */
+ }
+ OrigFn;
+
+/* __SPECIAL_INSTRUCTION_PREAMBLE will be used to identify Valgrind specific
+ * code. This detection is implemented in platform specific toIR.c
+ * (e.g. VEX/priv/guest_s390_decoder.c).
+ */
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ "lr 15,15\n\t" \
+ "lr 1,1\n\t" \
+ "lr 2,2\n\t" \
+ "lr 3,3\n\t"
+
+#define __CLIENT_REQUEST_CODE "lr 2,2\n\t"
+#define __GET_NR_CONTEXT_CODE "lr 3,3\n\t"
+#define __CALL_NO_REDIR_CODE "lr 4,4\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ __extension__ \
+ ({volatile unsigned long long int _zzq_args[6]; \
+ volatile unsigned long long int _zzq_result; \
+ _zzq_args[0] = (unsigned long long int)(_zzq_request); \
+ _zzq_args[1] = (unsigned long long int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned long long int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned long long int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned long long int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned long long int)(_zzq_arg5); \
+ __asm__ volatile(/* r2 = args */ \
+ "lgr 2,%1\n\t" \
+ /* r3 = default */ \
+ "lgr 3,%2\n\t" \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ __CLIENT_REQUEST_CODE \
+ /* results = r3 */ \
+ "lgr %0, 3\n\t" \
+ : "=d" (_zzq_result) \
+ : "a" (&_zzq_args[0]), "0" (_zzq_default) \
+ : "cc", "2", "3", "memory" \
+ ); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ volatile unsigned long long int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ __GET_NR_CONTEXT_CODE \
+ "lgr %0, 3\n\t" \
+ : "=a" (__addr) \
+ : \
+ : "cc", "3", "memory" \
+ ); \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+#define VALGRIND_CALL_NOREDIR_R1 \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ __CALL_NO_REDIR_CODE
+
+#endif /* PLAT_s390x_linux */
+
+/* Insert assembly code for other platforms here... */
+
+#endif /* NVALGRIND */
+
+
+/* ------------------------------------------------------------------ */
+/* PLATFORM SPECIFICS for FUNCTION WRAPPING. This is all very */
+/* ugly. It's the least-worst tradeoff I can think of. */
+/* ------------------------------------------------------------------ */
+
+/* This section defines magic (a.k.a appalling-hack) macros for doing
+ guaranteed-no-redirection macros, so as to get from function
+ wrappers to the functions they are wrapping. The whole point is to
+ construct standard call sequences, but to do the call itself with a
+ special no-redirect call pseudo-instruction that the JIT
+ understands and handles specially. This section is long and
+ repetitious, and I can't see a way to make it shorter.
+
+ The naming scheme is as follows:
+
+ CALL_FN_{W,v}_{v,W,WW,WWW,WWWW,5W,6W,7W,etc}
+
+ 'W' stands for "word" and 'v' for "void". Hence there are
+ different macros for calling arity 0, 1, 2, 3, 4, etc, functions,
+ and for each, the possibility of returning a word-typed result, or
+ no result.
+*/
+
+/* Use these to write the name of your wrapper. NOTE: duplicates
+ VG_WRAP_FUNCTION_Z{U,Z} in pub_tool_redir.h. NOTE also: inserts
+ the default behaviour equivalance class tag "0000" into the name.
+ See pub_tool_redir.h for details -- normally you don't need to
+ think about this, though. */
+
+/* Use an extra level of macroisation so as to ensure the soname/fnname
+ args are fully macro-expanded before pasting them together. */
+#define VG_CONCAT4(_aa,_bb,_cc,_dd) _aa##_bb##_cc##_dd
+
+#define I_WRAP_SONAME_FNNAME_ZU(soname,fnname) \
+ VG_CONCAT4(_vgw00000ZU_,soname,_,fnname)
+
+#define I_WRAP_SONAME_FNNAME_ZZ(soname,fnname) \
+ VG_CONCAT4(_vgw00000ZZ_,soname,_,fnname)
+
+/* Use this macro from within a wrapper function to collect the
+ context (address and possibly other info) of the original function.
+ Once you have that you can then use it in one of the CALL_FN_
+ macros. The type of the argument _lval is OrigFn. */
+#define VALGRIND_GET_ORIG_FN(_lval) VALGRIND_GET_NR_CONTEXT(_lval)
+
+/* Derivatives of the main macros below, for calling functions
+ returning void. */
+
+#define CALL_FN_v_v(fnptr) \
+ do { volatile unsigned long _junk; \
+ CALL_FN_W_v(_junk,fnptr); } while (0)
+
+#define CALL_FN_v_W(fnptr, arg1) \
+ do { volatile unsigned long _junk; \
+ CALL_FN_W_W(_junk,fnptr,arg1); } while (0)
+
+#define CALL_FN_v_WW(fnptr, arg1,arg2) \
+ do { volatile unsigned long _junk; \
+ CALL_FN_W_WW(_junk,fnptr,arg1,arg2); } while (0)
+
+#define CALL_FN_v_WWW(fnptr, arg1,arg2,arg3) \
+ do { volatile unsigned long _junk; \
+ CALL_FN_W_WWW(_junk,fnptr,arg1,arg2,arg3); } while (0)
+
+#define CALL_FN_v_WWWW(fnptr, arg1,arg2,arg3,arg4) \
+ do { volatile unsigned long _junk; \
+ CALL_FN_W_WWWW(_junk,fnptr,arg1,arg2,arg3,arg4); } while (0)
+
+#define CALL_FN_v_5W(fnptr, arg1,arg2,arg3,arg4,arg5) \
+ do { volatile unsigned long _junk; \
+ CALL_FN_W_5W(_junk,fnptr,arg1,arg2,arg3,arg4,arg5); } while (0)
+
+#define CALL_FN_v_6W(fnptr, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { volatile unsigned long _junk; \
+ CALL_FN_W_6W(_junk,fnptr,arg1,arg2,arg3,arg4,arg5,arg6); } while (0)
+
+#define CALL_FN_v_7W(fnptr, arg1,arg2,arg3,arg4,arg5,arg6,arg7) \
+ do { volatile unsigned long _junk; \
+ CALL_FN_W_7W(_junk,fnptr,arg1,arg2,arg3,arg4,arg5,arg6,arg7); } while (0)
+
+/* ------------------------- x86-{linux,darwin} ---------------- */
+
+#if defined(PLAT_x86_linux) || defined(PLAT_x86_darwin)
+
+/* These regs are trashed by the hidden call. No need to mention eax
+ as gcc can already see that, plus causes gcc to bomb. */
+#define __CALLER_SAVED_REGS /*"eax"*/ "ecx", "edx"
+
+/* These CALL_FN_ macros assume that on x86-linux, sizeof(unsigned
+ long) == 4. */
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[1]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[2]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ __asm__ volatile( \
+ "subl $12, %%esp\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ "addl $16, %%esp\n" \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ __asm__ volatile( \
+ "subl $8, %%esp\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ "addl $16, %%esp\n" \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[4]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ __asm__ volatile( \
+ "subl $4, %%esp\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ "addl $16, %%esp\n" \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[5]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ __asm__ volatile( \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ "addl $16, %%esp\n" \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[6]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ __asm__ volatile( \
+ "subl $12, %%esp\n\t" \
+ "pushl 20(%%eax)\n\t" \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ "addl $32, %%esp\n" \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[7]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ __asm__ volatile( \
+ "subl $8, %%esp\n\t" \
+ "pushl 24(%%eax)\n\t" \
+ "pushl 20(%%eax)\n\t" \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ "addl $32, %%esp\n" \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[8]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ __asm__ volatile( \
+ "subl $4, %%esp\n\t" \
+ "pushl 28(%%eax)\n\t" \
+ "pushl 24(%%eax)\n\t" \
+ "pushl 20(%%eax)\n\t" \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ "addl $32, %%esp\n" \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[9]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ __asm__ volatile( \
+ "pushl 32(%%eax)\n\t" \
+ "pushl 28(%%eax)\n\t" \
+ "pushl 24(%%eax)\n\t" \
+ "pushl 20(%%eax)\n\t" \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ "addl $32, %%esp\n" \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[10]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ __asm__ volatile( \
+ "subl $12, %%esp\n\t" \
+ "pushl 36(%%eax)\n\t" \
+ "pushl 32(%%eax)\n\t" \
+ "pushl 28(%%eax)\n\t" \
+ "pushl 24(%%eax)\n\t" \
+ "pushl 20(%%eax)\n\t" \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ "addl $48, %%esp\n" \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[11]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ __asm__ volatile( \
+ "subl $8, %%esp\n\t" \
+ "pushl 40(%%eax)\n\t" \
+ "pushl 36(%%eax)\n\t" \
+ "pushl 32(%%eax)\n\t" \
+ "pushl 28(%%eax)\n\t" \
+ "pushl 24(%%eax)\n\t" \
+ "pushl 20(%%eax)\n\t" \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ "addl $48, %%esp\n" \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
+ arg6,arg7,arg8,arg9,arg10, \
+ arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[12]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ __asm__ volatile( \
+ "subl $4, %%esp\n\t" \
+ "pushl 44(%%eax)\n\t" \
+ "pushl 40(%%eax)\n\t" \
+ "pushl 36(%%eax)\n\t" \
+ "pushl 32(%%eax)\n\t" \
+ "pushl 28(%%eax)\n\t" \
+ "pushl 24(%%eax)\n\t" \
+ "pushl 20(%%eax)\n\t" \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ "addl $48, %%esp\n" \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
+ arg6,arg7,arg8,arg9,arg10, \
+ arg11,arg12) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[13]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ _argvec[12] = (unsigned long)(arg12); \
+ __asm__ volatile( \
+ "pushl 48(%%eax)\n\t" \
+ "pushl 44(%%eax)\n\t" \
+ "pushl 40(%%eax)\n\t" \
+ "pushl 36(%%eax)\n\t" \
+ "pushl 32(%%eax)\n\t" \
+ "pushl 28(%%eax)\n\t" \
+ "pushl 24(%%eax)\n\t" \
+ "pushl 20(%%eax)\n\t" \
+ "pushl 16(%%eax)\n\t" \
+ "pushl 12(%%eax)\n\t" \
+ "pushl 8(%%eax)\n\t" \
+ "pushl 4(%%eax)\n\t" \
+ "movl (%%eax), %%eax\n\t" /* target->%eax */ \
+ VALGRIND_CALL_NOREDIR_EAX \
+ "addl $48, %%esp\n" \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#endif /* PLAT_x86_linux || PLAT_x86_darwin */
+
+/* ------------------------ amd64-{linux,darwin} --------------- */
+
+#if defined(PLAT_amd64_linux) || defined(PLAT_amd64_darwin)
+
+/* ARGREGS: rdi rsi rdx rcx r8 r9 (the rest on stack in R-to-L order) */
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS /*"rax",*/ "rcx", "rdx", "rsi", \
+ "rdi", "r8", "r9", "r10", "r11"
+
+/* This is all pretty complex. It's so as to make stack unwinding
+ work reliably. See bug 243270. The basic problem is the sub and
+ add of 128 of %rsp in all of the following macros. If gcc believes
+ the CFA is in %rsp, then unwinding may fail, because what's at the
+ CFA is not what gcc "expected" when it constructs the CFIs for the
+ places where the macros are instantiated.
+
+ But we can't just add a CFI annotation to increase the CFA offset
+ by 128, to match the sub of 128 from %rsp, because we don't know
+ whether gcc has chosen %rsp as the CFA at that point, or whether it
+ has chosen some other register (eg, %rbp). In the latter case,
+ adding a CFI annotation to change the CFA offset is simply wrong.
+
+ So the solution is to get hold of the CFA using
+ __builtin_dwarf_cfa(), put it in a known register, and add a
+ CFI annotation to say what the register is. We choose %rbp for
+ this (perhaps perversely), because:
+
+ (1) %rbp is already subject to unwinding. If a new register was
+ chosen then the unwinder would have to unwind it in all stack
+ traces, which is expensive, and
+
+ (2) %rbp is already subject to precise exception updates in the
+ JIT. If a new register was chosen, we'd have to have precise
+ exceptions for it too, which reduces performance of the
+ generated code.
+
+ However .. one extra complication. We can't just whack the result
+ of __builtin_dwarf_cfa() into %rbp and then add %rbp to the
+ list of trashed registers at the end of the inline assembly
+ fragments; gcc won't allow %rbp to appear in that list. Hence
+ instead we need to stash %rbp in %r15 for the duration of the asm,
+ and say that %r15 is trashed instead. gcc seems happy to go with
+ that.
+
+ Oh .. and this all needs to be conditionalised so that it is
+ unchanged from before this commit, when compiled with older gccs
+ that don't support __builtin_dwarf_cfa. Furthermore, since
+ this header file is freestanding, it has to be independent of
+ config.h, and so the following conditionalisation cannot depend on
+ configure time checks.
+
+ Although it's not clear from
+ 'defined(__GNUC__) && defined(__GCC_HAVE_DWARF2_CFI_ASM)',
+ this expression excludes Darwin.
+ .cfi directives in Darwin assembly appear to be completely
+ different and I haven't investigated how they work.
+
+ For even more entertainment value, note we have to use the
+ completely undocumented __builtin_dwarf_cfa(), which appears to
+ really compute the CFA, whereas __builtin_frame_address(0) claims
+ to but actually doesn't. See
+ https://bugs.kde.org/show_bug.cgi?id=243270#c47
+*/
+#if defined(__GNUC__) && defined(__GCC_HAVE_DWARF2_CFI_ASM)
+# define __FRAME_POINTER \
+ ,"r"(__builtin_dwarf_cfa())
+# define VALGRIND_CFI_PROLOGUE \
+ "movq %%rbp, %%r15\n\t" \
+ "movq %2, %%rbp\n\t" \
+ ".cfi_remember_state\n\t" \
+ ".cfi_def_cfa rbp, 0\n\t"
+# define VALGRIND_CFI_EPILOGUE \
+ "movq %%r15, %%rbp\n\t" \
+ ".cfi_restore_state\n\t"
+#else
+# define __FRAME_POINTER
+# define VALGRIND_CFI_PROLOGUE
+# define VALGRIND_CFI_EPILOGUE
+#endif
+
+
+/* These CALL_FN_ macros assume that on amd64-linux, sizeof(unsigned
+ long) == 8. */
+
+/* NB 9 Sept 07. There is a nasty kludge here in all these CALL_FN_
+ macros. In order not to trash the stack redzone, we need to drop
+ %rsp by 128 before the hidden call, and restore afterwards. The
+ nastyness is that it is only by luck that the stack still appears
+ to be unwindable during the hidden call - since then the behaviour
+ of any routine using this macro does not match what the CFI data
+ says. Sigh.
+
+ Why is this important? Imagine that a wrapper has a stack
+ allocated local, and passes to the hidden call, a pointer to it.
+ Because gcc does not know about the hidden call, it may allocate
+ that local in the redzone. Unfortunately the hidden call may then
+ trash it before it comes to use it. So we must step clear of the
+ redzone, for the duration of the hidden call, to make it safe.
+
+ Probably the same problem afflicts the other redzone-style ABIs too
+ (ppc64-linux); but for those, the stack is
+ self describing (none of this CFI nonsense) so at least messing
+ with the stack pointer doesn't give a danger of non-unwindable
+ stack. */
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[1]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "subq $128,%%rsp\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ "addq $128,%%rsp\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[2]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "subq $128,%%rsp\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ "addq $128,%%rsp\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "subq $128,%%rsp\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ "addq $128,%%rsp\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[4]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "subq $128,%%rsp\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ "addq $128,%%rsp\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[5]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "subq $128,%%rsp\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ "addq $128,%%rsp\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[6]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "subq $128,%%rsp\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ "addq $128,%%rsp\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[7]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "subq $128,%%rsp\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ "addq $128,%%rsp\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[8]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "subq $136,%%rsp\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ "addq $8, %%rsp\n" \
+ "addq $136,%%rsp\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[9]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "subq $128,%%rsp\n\t" \
+ "pushq 64(%%rax)\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ "addq $16, %%rsp\n" \
+ "addq $128,%%rsp\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[10]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "subq $136,%%rsp\n\t" \
+ "pushq 72(%%rax)\n\t" \
+ "pushq 64(%%rax)\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ "addq $24, %%rsp\n" \
+ "addq $136,%%rsp\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[11]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "subq $128,%%rsp\n\t" \
+ "pushq 80(%%rax)\n\t" \
+ "pushq 72(%%rax)\n\t" \
+ "pushq 64(%%rax)\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ "addq $32, %%rsp\n" \
+ "addq $128,%%rsp\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[12]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "subq $136,%%rsp\n\t" \
+ "pushq 88(%%rax)\n\t" \
+ "pushq 80(%%rax)\n\t" \
+ "pushq 72(%%rax)\n\t" \
+ "pushq 64(%%rax)\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ "addq $40, %%rsp\n" \
+ "addq $136,%%rsp\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11,arg12) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[13]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ _argvec[12] = (unsigned long)(arg12); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "subq $128,%%rsp\n\t" \
+ "pushq 96(%%rax)\n\t" \
+ "pushq 88(%%rax)\n\t" \
+ "pushq 80(%%rax)\n\t" \
+ "pushq 72(%%rax)\n\t" \
+ "pushq 64(%%rax)\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ "addq $48, %%rsp\n" \
+ "addq $128,%%rsp\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#endif /* PLAT_amd64_linux || PLAT_amd64_darwin */
+
+/* ------------------------ ppc32-linux ------------------------ */
+
+#if defined(PLAT_ppc32_linux)
+
+/* This is useful for finding out about the on-stack stuff:
+
+ extern int f9 ( int,int,int,int,int,int,int,int,int );
+ extern int f10 ( int,int,int,int,int,int,int,int,int,int );
+ extern int f11 ( int,int,int,int,int,int,int,int,int,int,int );
+ extern int f12 ( int,int,int,int,int,int,int,int,int,int,int,int );
+
+ int g9 ( void ) {
+ return f9(11,22,33,44,55,66,77,88,99);
+ }
+ int g10 ( void ) {
+ return f10(11,22,33,44,55,66,77,88,99,110);
+ }
+ int g11 ( void ) {
+ return f11(11,22,33,44,55,66,77,88,99,110,121);
+ }
+ int g12 ( void ) {
+ return f12(11,22,33,44,55,66,77,88,99,110,121,132);
+ }
+*/
+
+/* ARGREGS: r3 r4 r5 r6 r7 r8 r9 r10 (the rest on stack somewhere) */
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS \
+ "lr", "ctr", "xer", \
+ "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
+ "r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
+ "r11", "r12", "r13"
+
+/* These CALL_FN_ macros assume that on ppc32-linux,
+ sizeof(unsigned long) == 4. */
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[1]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[2]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[4]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[5]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[6]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 7,20(11)\n\t" \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[7]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 7,20(11)\n\t" \
+ "lwz 8,24(11)\n\t" \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[8]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 7,20(11)\n\t" \
+ "lwz 8,24(11)\n\t" \
+ "lwz 9,28(11)\n\t" \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[9]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 7,20(11)\n\t" \
+ "lwz 8,24(11)\n\t" \
+ "lwz 9,28(11)\n\t" \
+ "lwz 10,32(11)\n\t" /* arg8->r10 */ \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[10]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ _argvec[9] = (unsigned long)arg9; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "addi 1,1,-16\n\t" \
+ /* arg9 */ \
+ "lwz 3,36(11)\n\t" \
+ "stw 3,8(1)\n\t" \
+ /* args1-8 */ \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 7,20(11)\n\t" \
+ "lwz 8,24(11)\n\t" \
+ "lwz 9,28(11)\n\t" \
+ "lwz 10,32(11)\n\t" /* arg8->r10 */ \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "addi 1,1,16\n\t" \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[11]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ _argvec[9] = (unsigned long)arg9; \
+ _argvec[10] = (unsigned long)arg10; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "addi 1,1,-16\n\t" \
+ /* arg10 */ \
+ "lwz 3,40(11)\n\t" \
+ "stw 3,12(1)\n\t" \
+ /* arg9 */ \
+ "lwz 3,36(11)\n\t" \
+ "stw 3,8(1)\n\t" \
+ /* args1-8 */ \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 7,20(11)\n\t" \
+ "lwz 8,24(11)\n\t" \
+ "lwz 9,28(11)\n\t" \
+ "lwz 10,32(11)\n\t" /* arg8->r10 */ \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "addi 1,1,16\n\t" \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[12]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ _argvec[9] = (unsigned long)arg9; \
+ _argvec[10] = (unsigned long)arg10; \
+ _argvec[11] = (unsigned long)arg11; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "addi 1,1,-32\n\t" \
+ /* arg11 */ \
+ "lwz 3,44(11)\n\t" \
+ "stw 3,16(1)\n\t" \
+ /* arg10 */ \
+ "lwz 3,40(11)\n\t" \
+ "stw 3,12(1)\n\t" \
+ /* arg9 */ \
+ "lwz 3,36(11)\n\t" \
+ "stw 3,8(1)\n\t" \
+ /* args1-8 */ \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 7,20(11)\n\t" \
+ "lwz 8,24(11)\n\t" \
+ "lwz 9,28(11)\n\t" \
+ "lwz 10,32(11)\n\t" /* arg8->r10 */ \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "addi 1,1,32\n\t" \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11,arg12) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[13]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ _argvec[9] = (unsigned long)arg9; \
+ _argvec[10] = (unsigned long)arg10; \
+ _argvec[11] = (unsigned long)arg11; \
+ _argvec[12] = (unsigned long)arg12; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "addi 1,1,-32\n\t" \
+ /* arg12 */ \
+ "lwz 3,48(11)\n\t" \
+ "stw 3,20(1)\n\t" \
+ /* arg11 */ \
+ "lwz 3,44(11)\n\t" \
+ "stw 3,16(1)\n\t" \
+ /* arg10 */ \
+ "lwz 3,40(11)\n\t" \
+ "stw 3,12(1)\n\t" \
+ /* arg9 */ \
+ "lwz 3,36(11)\n\t" \
+ "stw 3,8(1)\n\t" \
+ /* args1-8 */ \
+ "lwz 3,4(11)\n\t" /* arg1->r3 */ \
+ "lwz 4,8(11)\n\t" \
+ "lwz 5,12(11)\n\t" \
+ "lwz 6,16(11)\n\t" /* arg4->r6 */ \
+ "lwz 7,20(11)\n\t" \
+ "lwz 8,24(11)\n\t" \
+ "lwz 9,28(11)\n\t" \
+ "lwz 10,32(11)\n\t" /* arg8->r10 */ \
+ "lwz 11,0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "addi 1,1,32\n\t" \
+ "mr %0,3" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#endif /* PLAT_ppc32_linux */
+
+/* ------------------------ ppc64-linux ------------------------ */
+
+#if defined(PLAT_ppc64_linux)
+
+/* ARGREGS: r3 r4 r5 r6 r7 r8 r9 r10 (the rest on stack somewhere) */
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS \
+ "lr", "ctr", "xer", \
+ "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
+ "r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
+ "r11", "r12", "r13"
+
+/* These CALL_FN_ macros assume that on ppc64-linux, sizeof(unsigned
+ long) == 8. */
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+0]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)" /* restore tocptr */ \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+1]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)" /* restore tocptr */ \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+2]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)" /* restore tocptr */ \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+3]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)" /* restore tocptr */ \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+4]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)" /* restore tocptr */ \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+5]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(11)\n\t" /* arg5->r7 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)" /* restore tocptr */ \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+6]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(11)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(11)\n\t" /* arg6->r8 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)" /* restore tocptr */ \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+7]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(11)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(11)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(11)\n\t" /* arg7->r9 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)" /* restore tocptr */ \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+8]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ _argvec[2+8] = (unsigned long)arg8; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(11)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(11)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(11)\n\t" /* arg7->r9 */ \
+ "ld 10, 64(11)\n\t" /* arg8->r10 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)" /* restore tocptr */ \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+9]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ _argvec[2+8] = (unsigned long)arg8; \
+ _argvec[2+9] = (unsigned long)arg9; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "addi 1,1,-128\n\t" /* expand stack frame */ \
+ /* arg9 */ \
+ "ld 3,72(11)\n\t" \
+ "std 3,112(1)\n\t" \
+ /* args1-8 */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(11)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(11)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(11)\n\t" /* arg7->r9 */ \
+ "ld 10, 64(11)\n\t" /* arg8->r10 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ "addi 1,1,128" /* restore frame */ \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+10]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ _argvec[2+8] = (unsigned long)arg8; \
+ _argvec[2+9] = (unsigned long)arg9; \
+ _argvec[2+10] = (unsigned long)arg10; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "addi 1,1,-128\n\t" /* expand stack frame */ \
+ /* arg10 */ \
+ "ld 3,80(11)\n\t" \
+ "std 3,120(1)\n\t" \
+ /* arg9 */ \
+ "ld 3,72(11)\n\t" \
+ "std 3,112(1)\n\t" \
+ /* args1-8 */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(11)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(11)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(11)\n\t" /* arg7->r9 */ \
+ "ld 10, 64(11)\n\t" /* arg8->r10 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ "addi 1,1,128" /* restore frame */ \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+11]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ _argvec[2+8] = (unsigned long)arg8; \
+ _argvec[2+9] = (unsigned long)arg9; \
+ _argvec[2+10] = (unsigned long)arg10; \
+ _argvec[2+11] = (unsigned long)arg11; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "addi 1,1,-144\n\t" /* expand stack frame */ \
+ /* arg11 */ \
+ "ld 3,88(11)\n\t" \
+ "std 3,128(1)\n\t" \
+ /* arg10 */ \
+ "ld 3,80(11)\n\t" \
+ "std 3,120(1)\n\t" \
+ /* arg9 */ \
+ "ld 3,72(11)\n\t" \
+ "std 3,112(1)\n\t" \
+ /* args1-8 */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(11)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(11)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(11)\n\t" /* arg7->r9 */ \
+ "ld 10, 64(11)\n\t" /* arg8->r10 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ "addi 1,1,144" /* restore frame */ \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11,arg12) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3+12]; \
+ volatile unsigned long _res; \
+ /* _argvec[0] holds current r2 across the call */ \
+ _argvec[1] = (unsigned long)_orig.r2; \
+ _argvec[2] = (unsigned long)_orig.nraddr; \
+ _argvec[2+1] = (unsigned long)arg1; \
+ _argvec[2+2] = (unsigned long)arg2; \
+ _argvec[2+3] = (unsigned long)arg3; \
+ _argvec[2+4] = (unsigned long)arg4; \
+ _argvec[2+5] = (unsigned long)arg5; \
+ _argvec[2+6] = (unsigned long)arg6; \
+ _argvec[2+7] = (unsigned long)arg7; \
+ _argvec[2+8] = (unsigned long)arg8; \
+ _argvec[2+9] = (unsigned long)arg9; \
+ _argvec[2+10] = (unsigned long)arg10; \
+ _argvec[2+11] = (unsigned long)arg11; \
+ _argvec[2+12] = (unsigned long)arg12; \
+ __asm__ volatile( \
+ "mr 11,%1\n\t" \
+ "std 2,-16(11)\n\t" /* save tocptr */ \
+ "ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
+ "addi 1,1,-144\n\t" /* expand stack frame */ \
+ /* arg12 */ \
+ "ld 3,96(11)\n\t" \
+ "std 3,136(1)\n\t" \
+ /* arg11 */ \
+ "ld 3,88(11)\n\t" \
+ "std 3,128(1)\n\t" \
+ /* arg10 */ \
+ "ld 3,80(11)\n\t" \
+ "std 3,120(1)\n\t" \
+ /* arg9 */ \
+ "ld 3,72(11)\n\t" \
+ "std 3,112(1)\n\t" \
+ /* args1-8 */ \
+ "ld 3, 8(11)\n\t" /* arg1->r3 */ \
+ "ld 4, 16(11)\n\t" /* arg2->r4 */ \
+ "ld 5, 24(11)\n\t" /* arg3->r5 */ \
+ "ld 6, 32(11)\n\t" /* arg4->r6 */ \
+ "ld 7, 40(11)\n\t" /* arg5->r7 */ \
+ "ld 8, 48(11)\n\t" /* arg6->r8 */ \
+ "ld 9, 56(11)\n\t" /* arg7->r9 */ \
+ "ld 10, 64(11)\n\t" /* arg8->r10 */ \
+ "ld 11, 0(11)\n\t" /* target->r11 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ "mr 11,%1\n\t" \
+ "mr %0,3\n\t" \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ "addi 1,1,144" /* restore frame */ \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "r" (&_argvec[2]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#endif /* PLAT_ppc64_linux */
+
+/* ------------------------- arm-linux ------------------------- */
+
+#if defined(PLAT_arm_linux)
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS "r0", "r1", "r2", "r3","r4","r14"
+
+/* These CALL_FN_ macros assume that on arm-linux, sizeof(unsigned
+ long) == 4. */
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[1]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ "mov %0, r0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[2]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ __asm__ volatile( \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ "mov %0, r0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ __asm__ volatile( \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ "mov %0, r0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[4]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ __asm__ volatile( \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ "mov %0, r0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[5]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ __asm__ volatile( \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[6]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ __asm__ volatile( \
+ "ldr r0, [%1, #20] \n\t" \
+ "push {r0} \n\t" \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ "add sp, sp, #4 \n\t" \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[7]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ __asm__ volatile( \
+ "ldr r0, [%1, #20] \n\t" \
+ "ldr r1, [%1, #24] \n\t" \
+ "push {r0, r1} \n\t" \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ "add sp, sp, #8 \n\t" \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[8]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ __asm__ volatile( \
+ "ldr r0, [%1, #20] \n\t" \
+ "ldr r1, [%1, #24] \n\t" \
+ "ldr r2, [%1, #28] \n\t" \
+ "push {r0, r1, r2} \n\t" \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ "add sp, sp, #12 \n\t" \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[9]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ __asm__ volatile( \
+ "ldr r0, [%1, #20] \n\t" \
+ "ldr r1, [%1, #24] \n\t" \
+ "ldr r2, [%1, #28] \n\t" \
+ "ldr r3, [%1, #32] \n\t" \
+ "push {r0, r1, r2, r3} \n\t" \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ "add sp, sp, #16 \n\t" \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[10]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ __asm__ volatile( \
+ "ldr r0, [%1, #20] \n\t" \
+ "ldr r1, [%1, #24] \n\t" \
+ "ldr r2, [%1, #28] \n\t" \
+ "ldr r3, [%1, #32] \n\t" \
+ "ldr r4, [%1, #36] \n\t" \
+ "push {r0, r1, r2, r3, r4} \n\t" \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ "add sp, sp, #20 \n\t" \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[11]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ __asm__ volatile( \
+ "ldr r0, [%1, #40] \n\t" \
+ "push {r0} \n\t" \
+ "ldr r0, [%1, #20] \n\t" \
+ "ldr r1, [%1, #24] \n\t" \
+ "ldr r2, [%1, #28] \n\t" \
+ "ldr r3, [%1, #32] \n\t" \
+ "ldr r4, [%1, #36] \n\t" \
+ "push {r0, r1, r2, r3, r4} \n\t" \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ "add sp, sp, #24 \n\t" \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
+ arg6,arg7,arg8,arg9,arg10, \
+ arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[12]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ __asm__ volatile( \
+ "ldr r0, [%1, #40] \n\t" \
+ "ldr r1, [%1, #44] \n\t" \
+ "push {r0, r1} \n\t" \
+ "ldr r0, [%1, #20] \n\t" \
+ "ldr r1, [%1, #24] \n\t" \
+ "ldr r2, [%1, #28] \n\t" \
+ "ldr r3, [%1, #32] \n\t" \
+ "ldr r4, [%1, #36] \n\t" \
+ "push {r0, r1, r2, r3, r4} \n\t" \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ "add sp, sp, #28 \n\t" \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory",__CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
+ arg6,arg7,arg8,arg9,arg10, \
+ arg11,arg12) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[13]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ _argvec[12] = (unsigned long)(arg12); \
+ __asm__ volatile( \
+ "ldr r0, [%1, #40] \n\t" \
+ "ldr r1, [%1, #44] \n\t" \
+ "ldr r2, [%1, #48] \n\t" \
+ "push {r0, r1, r2} \n\t" \
+ "ldr r0, [%1, #20] \n\t" \
+ "ldr r1, [%1, #24] \n\t" \
+ "ldr r2, [%1, #28] \n\t" \
+ "ldr r3, [%1, #32] \n\t" \
+ "ldr r4, [%1, #36] \n\t" \
+ "push {r0, r1, r2, r3, r4} \n\t" \
+ "ldr r0, [%1, #4] \n\t" \
+ "ldr r1, [%1, #8] \n\t" \
+ "ldr r2, [%1, #12] \n\t" \
+ "ldr r3, [%1, #16] \n\t" \
+ "ldr r4, [%1] \n\t" /* target->r4 */ \
+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ "add sp, sp, #32 \n\t" \
+ "mov %0, r0" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#endif /* PLAT_arm_linux */
+
+/* ------------------------- s390x-linux ------------------------- */
+
+#if defined(PLAT_s390x_linux)
+
+/* Similar workaround as amd64 (see above), but we use r11 as frame
+ pointer and save the old r11 in r7. r11 might be used for
+ argvec, therefore we copy argvec in r1 since r1 is clobbered
+ after the call anyway. */
+#if defined(__GNUC__) && defined(__GCC_HAVE_DWARF2_CFI_ASM)
+# define __FRAME_POINTER \
+ ,"d"(__builtin_dwarf_cfa())
+# define VALGRIND_CFI_PROLOGUE \
+ ".cfi_remember_state\n\t" \
+ "lgr 1,%1\n\t" /* copy the argvec pointer in r1 */ \
+ "lgr 7,11\n\t" \
+ "lgr 11,%2\n\t" \
+ ".cfi_def_cfa r11, 0\n\t"
+# define VALGRIND_CFI_EPILOGUE \
+ "lgr 11, 7\n\t" \
+ ".cfi_restore_state\n\t"
+#else
+# define __FRAME_POINTER
+# define VALGRIND_CFI_PROLOGUE \
+ "lgr 1,%1\n\t"
+# define VALGRIND_CFI_EPILOGUE
+#endif
+
+
+
+
+/* These regs are trashed by the hidden call. Note that we overwrite
+ r14 in s390_irgen_noredir (VEX/priv/guest_s390_irgen.c) to give the
+ function a proper return address. All others are ABI defined call
+ clobbers. */
+#define __CALLER_SAVED_REGS "0","1","2","3","4","5","14", \
+ "f0","f1","f2","f3","f4","f5","f6","f7"
+
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[1]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-160\n\t" \
+ "lg 1, 0(1)\n\t" /* target->r1 */ \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "lgr %0, 2\n\t" \
+ "aghi 15,160\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "d" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+/* The call abi has the arguments in r2-r6 and stack */
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[2]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-160\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "lgr %0, 2\n\t" \
+ "aghi 15,160\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1, arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-160\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "lgr %0, 2\n\t" \
+ "aghi 15,160\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1, arg2, arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[4]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-160\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "lgr %0, 2\n\t" \
+ "aghi 15,160\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1, arg2, arg3, arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[5]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-160\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "lgr %0, 2\n\t" \
+ "aghi 15,160\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1, arg2, arg3, arg4, arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[6]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-160\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 6,40(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "lgr %0, 2\n\t" \
+ "aghi 15,160\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1, arg2, arg3, arg4, arg5, \
+ arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[7]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-168\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 6,40(1)\n\t" \
+ "mvc 160(8,15), 48(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "lgr %0, 2\n\t" \
+ "aghi 15,168\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1, arg2, arg3, arg4, arg5, \
+ arg6, arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[8]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-176\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 6,40(1)\n\t" \
+ "mvc 160(8,15), 48(1)\n\t" \
+ "mvc 168(8,15), 56(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "lgr %0, 2\n\t" \
+ "aghi 15,176\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1, arg2, arg3, arg4, arg5, \
+ arg6, arg7 ,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[9]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-184\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 6,40(1)\n\t" \
+ "mvc 160(8,15), 48(1)\n\t" \
+ "mvc 168(8,15), 56(1)\n\t" \
+ "mvc 176(8,15), 64(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "lgr %0, 2\n\t" \
+ "aghi 15,184\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1, arg2, arg3, arg4, arg5, \
+ arg6, arg7 ,arg8, arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[10]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ _argvec[9] = (unsigned long)arg9; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-192\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 6,40(1)\n\t" \
+ "mvc 160(8,15), 48(1)\n\t" \
+ "mvc 168(8,15), 56(1)\n\t" \
+ "mvc 176(8,15), 64(1)\n\t" \
+ "mvc 184(8,15), 72(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "lgr %0, 2\n\t" \
+ "aghi 15,192\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1, arg2, arg3, arg4, arg5, \
+ arg6, arg7 ,arg8, arg9, arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[11]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ _argvec[9] = (unsigned long)arg9; \
+ _argvec[10] = (unsigned long)arg10; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-200\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 6,40(1)\n\t" \
+ "mvc 160(8,15), 48(1)\n\t" \
+ "mvc 168(8,15), 56(1)\n\t" \
+ "mvc 176(8,15), 64(1)\n\t" \
+ "mvc 184(8,15), 72(1)\n\t" \
+ "mvc 192(8,15), 80(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "lgr %0, 2\n\t" \
+ "aghi 15,200\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1, arg2, arg3, arg4, arg5, \
+ arg6, arg7 ,arg8, arg9, arg10, arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[12]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ _argvec[9] = (unsigned long)arg9; \
+ _argvec[10] = (unsigned long)arg10; \
+ _argvec[11] = (unsigned long)arg11; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-208\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 6,40(1)\n\t" \
+ "mvc 160(8,15), 48(1)\n\t" \
+ "mvc 168(8,15), 56(1)\n\t" \
+ "mvc 176(8,15), 64(1)\n\t" \
+ "mvc 184(8,15), 72(1)\n\t" \
+ "mvc 192(8,15), 80(1)\n\t" \
+ "mvc 200(8,15), 88(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "lgr %0, 2\n\t" \
+ "aghi 15,208\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1, arg2, arg3, arg4, arg5, \
+ arg6, arg7 ,arg8, arg9, arg10, arg11, arg12)\
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[13]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)arg1; \
+ _argvec[2] = (unsigned long)arg2; \
+ _argvec[3] = (unsigned long)arg3; \
+ _argvec[4] = (unsigned long)arg4; \
+ _argvec[5] = (unsigned long)arg5; \
+ _argvec[6] = (unsigned long)arg6; \
+ _argvec[7] = (unsigned long)arg7; \
+ _argvec[8] = (unsigned long)arg8; \
+ _argvec[9] = (unsigned long)arg9; \
+ _argvec[10] = (unsigned long)arg10; \
+ _argvec[11] = (unsigned long)arg11; \
+ _argvec[12] = (unsigned long)arg12; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ "aghi 15,-216\n\t" \
+ "lg 2, 8(1)\n\t" \
+ "lg 3,16(1)\n\t" \
+ "lg 4,24(1)\n\t" \
+ "lg 5,32(1)\n\t" \
+ "lg 6,40(1)\n\t" \
+ "mvc 160(8,15), 48(1)\n\t" \
+ "mvc 168(8,15), 56(1)\n\t" \
+ "mvc 176(8,15), 64(1)\n\t" \
+ "mvc 184(8,15), 72(1)\n\t" \
+ "mvc 192(8,15), 80(1)\n\t" \
+ "mvc 200(8,15), 88(1)\n\t" \
+ "mvc 208(8,15), 96(1)\n\t" \
+ "lg 1, 0(1)\n\t" \
+ VALGRIND_CALL_NOREDIR_R1 \
+ "lgr %0, 2\n\t" \
+ "aghi 15,216\n\t" \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=d" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+
+#endif /* PLAT_s390x_linux */
+
+
+/* ------------------------------------------------------------------ */
+/* ARCHITECTURE INDEPENDENT MACROS for CLIENT REQUESTS. */
+/* */
+/* ------------------------------------------------------------------ */
+
+/* Some request codes. There are many more of these, but most are not
+ exposed to end-user view. These are the public ones, all of the
+ form 0x1000 + small_number.
+
+ Core ones are in the range 0x00000000--0x0000ffff. The non-public
+ ones start at 0x2000.
+*/
+
+/* These macros are used by tools -- they must be public, but don't
+ embed them into other programs. */
+#define VG_USERREQ_TOOL_BASE(a,b) \
+ ((unsigned int)(((a)&0xff) << 24 | ((b)&0xff) << 16))
+#define VG_IS_TOOL_USERREQ(a, b, v) \
+ (VG_USERREQ_TOOL_BASE(a,b) == ((v) & 0xffff0000))
+
+/* !! ABIWARNING !! ABIWARNING !! ABIWARNING !! ABIWARNING !!
+ This enum comprises an ABI exported by Valgrind to programs
+ which use client requests. DO NOT CHANGE THE ORDER OF THESE
+ ENTRIES, NOR DELETE ANY -- add new ones at the end. */
+typedef
+ enum { VG_USERREQ__RUNNING_ON_VALGRIND = 0x1001,
+ VG_USERREQ__DISCARD_TRANSLATIONS = 0x1002,
+
+ /* These allow any function to be called from the simulated
+ CPU but run on the real CPU. Nb: the first arg passed to
+ the function is always the ThreadId of the running
+ thread! So CLIENT_CALL0 actually requires a 1 arg
+ function, etc. */
+ VG_USERREQ__CLIENT_CALL0 = 0x1101,
+ VG_USERREQ__CLIENT_CALL1 = 0x1102,
+ VG_USERREQ__CLIENT_CALL2 = 0x1103,
+ VG_USERREQ__CLIENT_CALL3 = 0x1104,
+
+ /* Can be useful in regression testing suites -- eg. can
+ send Valgrind's output to /dev/null and still count
+ errors. */
+ VG_USERREQ__COUNT_ERRORS = 0x1201,
+
+ /* Allows a string (gdb monitor command) to be passed to the tool
+ Used for interaction with vgdb/gdb */
+ VG_USERREQ__GDB_MONITOR_COMMAND = 0x1202,
+
+ /* These are useful and can be interpreted by any tool that
+ tracks malloc() et al, by using vg_replace_malloc.c. */
+ VG_USERREQ__MALLOCLIKE_BLOCK = 0x1301,
+ VG_USERREQ__RESIZEINPLACE_BLOCK = 0x130b,
+ VG_USERREQ__FREELIKE_BLOCK = 0x1302,
+ /* Memory pool support. */
+ VG_USERREQ__CREATE_MEMPOOL = 0x1303,
+ VG_USERREQ__DESTROY_MEMPOOL = 0x1304,
+ VG_USERREQ__MEMPOOL_ALLOC = 0x1305,
+ VG_USERREQ__MEMPOOL_FREE = 0x1306,
+ VG_USERREQ__MEMPOOL_TRIM = 0x1307,
+ VG_USERREQ__MOVE_MEMPOOL = 0x1308,
+ VG_USERREQ__MEMPOOL_CHANGE = 0x1309,
+ VG_USERREQ__MEMPOOL_EXISTS = 0x130a,
+
+ /* Allow printfs to valgrind log. */
+ /* The first two pass the va_list argument by value, which
+ assumes it is the same size as or smaller than a UWord,
+ which generally isn't the case. Hence are deprecated.
+ The second two pass the vargs by reference and so are
+ immune to this problem. */
+ /* both :: char* fmt, va_list vargs (DEPRECATED) */
+ VG_USERREQ__PRINTF = 0x1401,
+ VG_USERREQ__PRINTF_BACKTRACE = 0x1402,
+ /* both :: char* fmt, va_list* vargs */
+ VG_USERREQ__PRINTF_VALIST_BY_REF = 0x1403,
+ VG_USERREQ__PRINTF_BACKTRACE_VALIST_BY_REF = 0x1404,
+
+ /* Stack support. */
+ VG_USERREQ__STACK_REGISTER = 0x1501,
+ VG_USERREQ__STACK_DEREGISTER = 0x1502,
+ VG_USERREQ__STACK_CHANGE = 0x1503,
+
+ /* Wine support */
+ VG_USERREQ__LOAD_PDB_DEBUGINFO = 0x1601,
+
+ /* Querying of debug info. */
+ VG_USERREQ__MAP_IP_TO_SRCLOC = 0x1701,
+
+ /* Disable/enable error reporting level. Takes a single
+ Word arg which is the delta to this thread's error
+ disablement indicator. Hence 1 disables or further
+ disables errors, and -1 moves back towards enablement.
+ Other values are not allowed. */
+ VG_USERREQ__CHANGE_ERR_DISABLEMENT = 0x1801
+ } Vg_ClientRequest;
+
+#if !defined(__GNUC__)
+# define __extension__ /* */
+#endif
+
+
+/* Returns the number of Valgrinds this code is running under. That
+ is, 0 if running natively, 1 if running under Valgrind, 2 if
+ running under Valgrind which is running under another Valgrind,
+ etc. */
+#define RUNNING_ON_VALGRIND \
+ (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* if not */, \
+ VG_USERREQ__RUNNING_ON_VALGRIND, \
+ 0, 0, 0, 0, 0) \
+
+
+/* Discard translation of code in the range [_qzz_addr .. _qzz_addr +
+ _qzz_len - 1]. Useful if you are debugging a JITter or some such,
+ since it provides a way to make sure valgrind will retranslate the
+ invalidated area. Returns no value. */
+#define VALGRIND_DISCARD_TRANSLATIONS(_qzz_addr,_qzz_len) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DISCARD_TRANSLATIONS, \
+ _qzz_addr, _qzz_len, 0, 0, 0)
+
+
+/* These requests are for getting Valgrind itself to print something.
+ Possibly with a backtrace. This is a really ugly hack. The return value
+ is the number of characters printed, excluding the "**<pid>** " part at the
+ start and the backtrace (if present). */
+
+#if defined(__GNUC__) || defined(__INTEL_COMPILER)
+/* Modern GCC will optimize the static routine out if unused,
+ and unused attribute will shut down warnings about it. */
+static int VALGRIND_PRINTF(const char *format, ...)
+ __attribute__((format(__printf__, 1, 2), __unused__));
+#endif
+static int
+#if defined(_MSC_VER)
+__inline
+#endif
+VALGRIND_PRINTF(const char *format, ...)
+{
+#if defined(NVALGRIND)
+ return 0;
+#else /* NVALGRIND */
+#if defined(_MSC_VER)
+ uintptr_t _qzz_res;
+#else
+ unsigned long _qzz_res;
+#endif
+ va_list vargs;
+ va_start(vargs, format);
+#if defined(_MSC_VER)
+ _qzz_res = VALGRIND_DO_CLIENT_REQUEST_EXPR(0,
+ VG_USERREQ__PRINTF_VALIST_BY_REF,
+ (uintptr_t)format,
+ (uintptr_t)&vargs,
+ 0, 0, 0);
+#else
+ _qzz_res = VALGRIND_DO_CLIENT_REQUEST_EXPR(0,
+ VG_USERREQ__PRINTF_VALIST_BY_REF,
+ (unsigned long)format,
+ (unsigned long)&vargs,
+ 0, 0, 0);
+#endif
+ va_end(vargs);
+ return (int)_qzz_res;
+#endif /* NVALGRIND */
+}
+
+#if defined(__GNUC__) || defined(__INTEL_COMPILER)
+static int VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
+ __attribute__((format(__printf__, 1, 2), __unused__));
+#endif
+static int
+#if defined(_MSC_VER)
+__inline
+#endif
+VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
+{
+#if defined(NVALGRIND)
+ return 0;
+#else /* NVALGRIND */
+#if defined(_MSC_VER)
+ uintptr_t _qzz_res;
+#else
+ unsigned long _qzz_res;
+#endif
+ va_list vargs;
+ va_start(vargs, format);
+#if defined(_MSC_VER)
+ _qzz_res = VALGRIND_DO_CLIENT_REQUEST_EXPR(0,
+ VG_USERREQ__PRINTF_BACKTRACE_VALIST_BY_REF,
+ (uintptr_t)format,
+ (uintptr_t)&vargs,
+ 0, 0, 0);
+#else
+ _qzz_res = VALGRIND_DO_CLIENT_REQUEST_EXPR(0,
+ VG_USERREQ__PRINTF_BACKTRACE_VALIST_BY_REF,
+ (unsigned long)format,
+ (unsigned long)&vargs,
+ 0, 0, 0);
+#endif
+ va_end(vargs);
+ return (int)_qzz_res;
+#endif /* NVALGRIND */
+}
+
+
+/* These requests allow control to move from the simulated CPU to the
+ real CPU, calling an arbitary function.
+
+ Note that the current ThreadId is inserted as the first argument.
+ So this call:
+
+ VALGRIND_NON_SIMD_CALL2(f, arg1, arg2)
+
+ requires f to have this signature:
+
+ Word f(Word tid, Word arg1, Word arg2)
+
+ where "Word" is a word-sized type.
+
+ Note that these client requests are not entirely reliable. For example,
+ if you call a function with them that subsequently calls printf(),
+ there's a high chance Valgrind will crash. Generally, your prospects of
+ these working are made higher if the called function does not refer to
+ any global variables, and does not refer to any libc or other functions
+ (printf et al). Any kind of entanglement with libc or dynamic linking is
+ likely to have a bad outcome, for tricky reasons which we've grappled
+ with a lot in the past.
+*/
+#define VALGRIND_NON_SIMD_CALL0(_qyy_fn) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \
+ VG_USERREQ__CLIENT_CALL0, \
+ _qyy_fn, \
+ 0, 0, 0, 0)
+
+#define VALGRIND_NON_SIMD_CALL1(_qyy_fn, _qyy_arg1) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \
+ VG_USERREQ__CLIENT_CALL1, \
+ _qyy_fn, \
+ _qyy_arg1, 0, 0, 0)
+
+#define VALGRIND_NON_SIMD_CALL2(_qyy_fn, _qyy_arg1, _qyy_arg2) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \
+ VG_USERREQ__CLIENT_CALL2, \
+ _qyy_fn, \
+ _qyy_arg1, _qyy_arg2, 0, 0)
+
+#define VALGRIND_NON_SIMD_CALL3(_qyy_fn, _qyy_arg1, _qyy_arg2, _qyy_arg3) \
+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \
+ VG_USERREQ__CLIENT_CALL3, \
+ _qyy_fn, \
+ _qyy_arg1, _qyy_arg2, \
+ _qyy_arg3, 0)
+
+
+/* Counts the number of errors that have been recorded by a tool. Nb:
+ the tool must record the errors with VG_(maybe_record_error)() or
+ VG_(unique_error)() for them to be counted. */
+#define VALGRIND_COUNT_ERRORS \
+ (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ 0 /* default return */, \
+ VG_USERREQ__COUNT_ERRORS, \
+ 0, 0, 0, 0, 0)
+
+/* Several Valgrind tools (Memcheck, Massif, Helgrind, DRD) rely on knowing
+ when heap blocks are allocated in order to give accurate results. This
+ happens automatically for the standard allocator functions such as
+ malloc(), calloc(), realloc(), memalign(), new, new[], free(), delete,
+ delete[], etc.
+
+ But if your program uses a custom allocator, this doesn't automatically
+ happen, and Valgrind will not do as well. For example, if you allocate
+ superblocks with mmap() and then allocates chunks of the superblocks, all
+ Valgrind's observations will be at the mmap() level and it won't know that
+ the chunks should be considered separate entities. In Memcheck's case,
+ that means you probably won't get heap block overrun detection (because
+ there won't be redzones marked as unaddressable) and you definitely won't
+ get any leak detection.
+
+ The following client requests allow a custom allocator to be annotated so
+ that it can be handled accurately by Valgrind.
+
+ VALGRIND_MALLOCLIKE_BLOCK marks a region of memory as having been allocated
+ by a malloc()-like function. For Memcheck (an illustrative case), this
+ does two things:
+
+ - It records that the block has been allocated. This means any addresses
+ within the block mentioned in error messages will be
+ identified as belonging to the block. It also means that if the block
+ isn't freed it will be detected by the leak checker.
+
+ - It marks the block as being addressable and undefined (if 'is_zeroed' is
+ not set), or addressable and defined (if 'is_zeroed' is set). This
+ controls how accesses to the block by the program are handled.
+
+ 'addr' is the start of the usable block (ie. after any
+ redzone), 'sizeB' is its size. 'rzB' is the redzone size if the allocator
+ can apply redzones -- these are blocks of padding at the start and end of
+ each block. Adding redzones is recommended as it makes it much more likely
+ Valgrind will spot block overruns. `is_zeroed' indicates if the memory is
+ zeroed (or filled with another predictable value), as is the case for
+ calloc().
+
+ VALGRIND_MALLOCLIKE_BLOCK should be put immediately after the point where a
+ heap block -- that will be used by the client program -- is allocated.
+ It's best to put it at the outermost level of the allocator if possible;
+ for example, if you have a function my_alloc() which calls
+ internal_alloc(), and the client request is put inside internal_alloc(),
+ stack traces relating to the heap block will contain entries for both
+ my_alloc() and internal_alloc(), which is probably not what you want.
+
+ For Memcheck users: if you use VALGRIND_MALLOCLIKE_BLOCK to carve out
+ custom blocks from within a heap block, B, that has been allocated with
+ malloc/calloc/new/etc, then block B will be *ignored* during leak-checking
+ -- the custom blocks will take precedence.
+
+ VALGRIND_FREELIKE_BLOCK is the partner to VALGRIND_MALLOCLIKE_BLOCK. For
+ Memcheck, it does two things:
+
+ - It records that the block has been deallocated. This assumes that the
+ block was annotated as having been allocated via
+ VALGRIND_MALLOCLIKE_BLOCK. Otherwise, an error will be issued.
+
+ - It marks the block as being unaddressable.
+
+ VALGRIND_FREELIKE_BLOCK should be put immediately after the point where a
+ heap block is deallocated.
+
+ VALGRIND_RESIZEINPLACE_BLOCK informs a tool about reallocation. For
+ Memcheck, it does four things:
+
+ - It records that the size of a block has been changed. This assumes that
+ the block was annotated as having been allocated via
+ VALGRIND_MALLOCLIKE_BLOCK. Otherwise, an error will be issued.
+
+ - If the block shrunk, it marks the freed memory as being unaddressable.
+
+ - If the block grew, it marks the new area as undefined and defines a red
+ zone past the end of the new block.
+
+ - The V-bits of the overlap between the old and the new block are preserved.
+
+ VALGRIND_RESIZEINPLACE_BLOCK should be put after allocation of the new block
+ and before deallocation of the old block.
+
+ In many cases, these three client requests will not be enough to get your
+ allocator working well with Memcheck. More specifically, if your allocator
+ writes to freed blocks in any way then a VALGRIND_MAKE_MEM_UNDEFINED call
+ will be necessary to mark the memory as addressable just before the zeroing
+ occurs, otherwise you'll get a lot of invalid write errors. For example,
+ you'll need to do this if your allocator recycles freed blocks, but it
+ zeroes them before handing them back out (via VALGRIND_MALLOCLIKE_BLOCK).
+ Alternatively, if your allocator reuses freed blocks for allocator-internal
+ data structures, VALGRIND_MAKE_MEM_UNDEFINED calls will also be necessary.
+
+ Really, what's happening is a blurring of the lines between the client
+ program and the allocator... after VALGRIND_FREELIKE_BLOCK is called, the
+ memory should be considered unaddressable to the client program, but the
+ allocator knows more than the rest of the client program and so may be able
+ to safely access it. Extra client requests are necessary for Valgrind to
+ understand the distinction between the allocator and the rest of the
+ program.
+
+ Ignored if addr == 0.
+*/
+#define VALGRIND_MALLOCLIKE_BLOCK(addr, sizeB, rzB, is_zeroed) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MALLOCLIKE_BLOCK, \
+ addr, sizeB, rzB, is_zeroed, 0)
+
+/* See the comment for VALGRIND_MALLOCLIKE_BLOCK for details.
+ Ignored if addr == 0.
+*/
+#define VALGRIND_RESIZEINPLACE_BLOCK(addr, oldSizeB, newSizeB, rzB) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__RESIZEINPLACE_BLOCK, \
+ addr, oldSizeB, newSizeB, rzB, 0)
+
+/* See the comment for VALGRIND_MALLOCLIKE_BLOCK for details.
+ Ignored if addr == 0.
+*/
+#define VALGRIND_FREELIKE_BLOCK(addr, rzB) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__FREELIKE_BLOCK, \
+ addr, rzB, 0, 0, 0)
+
+/* Create a memory pool. */
+#define VALGRIND_CREATE_MEMPOOL(pool, rzB, is_zeroed) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__CREATE_MEMPOOL, \
+ pool, rzB, is_zeroed, 0, 0)
+
+/* Destroy a memory pool. */
+#define VALGRIND_DESTROY_MEMPOOL(pool) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DESTROY_MEMPOOL, \
+ pool, 0, 0, 0, 0)
+
+/* Associate a piece of memory with a memory pool. */
+#define VALGRIND_MEMPOOL_ALLOC(pool, addr, size) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MEMPOOL_ALLOC, \
+ pool, addr, size, 0, 0)
+
+/* Disassociate a piece of memory from a memory pool. */
+#define VALGRIND_MEMPOOL_FREE(pool, addr) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MEMPOOL_FREE, \
+ pool, addr, 0, 0, 0)
+
+/* Disassociate any pieces outside a particular range. */
+#define VALGRIND_MEMPOOL_TRIM(pool, addr, size) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MEMPOOL_TRIM, \
+ pool, addr, size, 0, 0)
+
+/* Resize and/or move a piece associated with a memory pool. */
+#define VALGRIND_MOVE_MEMPOOL(poolA, poolB) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MOVE_MEMPOOL, \
+ poolA, poolB, 0, 0, 0)
+
+/* Resize and/or move a piece associated with a memory pool. */
+#define VALGRIND_MEMPOOL_CHANGE(pool, addrA, addrB, size) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MEMPOOL_CHANGE, \
+ pool, addrA, addrB, size, 0)
+
+/* Return 1 if a mempool exists, else 0. */
+#define VALGRIND_MEMPOOL_EXISTS(pool) \
+ (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \
+ VG_USERREQ__MEMPOOL_EXISTS, \
+ pool, 0, 0, 0, 0)
+
+/* Mark a piece of memory as being a stack. Returns a stack id. */
+#define VALGRIND_STACK_REGISTER(start, end) \
+ (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \
+ VG_USERREQ__STACK_REGISTER, \
+ start, end, 0, 0, 0)
+
+/* Unmark the piece of memory associated with a stack id as being a
+ stack. */
+#define VALGRIND_STACK_DEREGISTER(id) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__STACK_DEREGISTER, \
+ id, 0, 0, 0, 0)
+
+/* Change the start and end address of the stack id. */
+#define VALGRIND_STACK_CHANGE(id, start, end) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__STACK_CHANGE, \
+ id, start, end, 0, 0)
+
+/* Load PDB debug info for Wine PE image_map. */
+#define VALGRIND_LOAD_PDB_DEBUGINFO(fd, ptr, total_size, delta) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__LOAD_PDB_DEBUGINFO, \
+ fd, ptr, total_size, delta, 0)
+
+/* Map a code address to a source file name and line number. buf64
+ must point to a 64-byte buffer in the caller's address space. The
+ result will be dumped in there and is guaranteed to be zero
+ terminated. If no info is found, the first byte is set to zero. */
+#define VALGRIND_MAP_IP_TO_SRCLOC(addr, buf64) \
+ (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \
+ VG_USERREQ__MAP_IP_TO_SRCLOC, \
+ addr, buf64, 0, 0, 0)
+
+/* Disable error reporting for this thread. Behaves in a stack like
+ way, so you can safely call this multiple times provided that
+ VALGRIND_ENABLE_ERROR_REPORTING is called the same number of times
+ to re-enable reporting. The first call of this macro disables
+ reporting. Subsequent calls have no effect except to increase the
+ number of VALGRIND_ENABLE_ERROR_REPORTING calls needed to re-enable
+ reporting. Child threads do not inherit this setting from their
+ parents -- they are always created with reporting enabled. */
+#define VALGRIND_DISABLE_ERROR_REPORTING \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__CHANGE_ERR_DISABLEMENT, \
+ 1, 0, 0, 0, 0)
+
+/* Re-enable error reporting, as per comments on
+ VALGRIND_DISABLE_ERROR_REPORTING. */
+#define VALGRIND_ENABLE_ERROR_REPORTING \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__CHANGE_ERR_DISABLEMENT, \
+ -1, 0, 0, 0, 0)
+
+#undef PLAT_x86_darwin
+#undef PLAT_amd64_darwin
+#undef PLAT_x86_win32
+#undef PLAT_x86_linux
+#undef PLAT_amd64_linux
+#undef PLAT_ppc32_linux
+#undef PLAT_ppc64_linux
+#undef PLAT_arm_linux
+#undef PLAT_s390x_linux
+
+#endif /* __VALGRIND_H */
diff --git a/src/lib/malloc.c b/src/lib/malloc.c
index 2e700f7..19862eb 100644
--- a/src/lib/malloc.c
+++ b/src/lib/malloc.c
@@ -1,6 +1,10 @@
#include <stdlib.h>
#include <console/console.h>
+#if CONFIG_ULINUX_VALGRIND
+#include <valgrind.h>
+#endif
+
#if CONFIG_DEBUG_MALLOC
#define MALLOCDBG(x...) printk(BIOS_SPEW, x)
#else
@@ -8,7 +12,7 @@
#endif
extern unsigned char _heap, _eheap;
-static void *free_mem_ptr = &_heap; /* Start of heap */
+static void *free_mem_ptr = &_heap + 64; /* Start of heap */
static void *free_mem_end_ptr = &_eheap; /* End of heap */
/* We don't restrict the boundary. This is firmware,
@@ -26,9 +30,9 @@ void *memalign(size_t boundary, size_t size)
die("Error! memalign: Free_mem_ptr <= 0");
free_mem_ptr = (void *)ALIGN((unsigned long)free_mem_ptr, boundary);
-
+ VALGRIND_MEMPOOL_ALLOC(&_heap, free_mem_ptr, size);
p = free_mem_ptr;
- free_mem_ptr += size;
+ free_mem_ptr += (size + 8);
if (free_mem_ptr >= free_mem_end_ptr)
die("Error! memalign: Out of memory (free_mem_ptr >= free_mem_end_ptr)");
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