coreboot March 2012

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Patch set updated for coreboot: a022953 Add TPM support to coreboot
by Stefan Reinauer 29 Mar '12

29 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/731 -gerrit commit a02295382303dd95a16720e2df4331a6834356d7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 11 14:46:25 2011 -0700 Add TPM support to coreboot and initialize the TPM on S3 resume This patch integrates the TPM driver and runs TPM resume upon an ACPI S3 resume without including any other parts of vboot. We could link against vboot_fw.a but it is compiled with u-boot's CFLAGS (that are incompatible with coreboot's) and it does a lot more than we want it to do. Change-Id: I000d4322ef313e931e23c56defaa17e3a4d7f8cf Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/Kconfig | 4 + src/arch/x86/boot/acpi.c | 8 + src/include/pc80/tpm.h | 29 ++ src/pc80/Makefile.inc | 1 + src/pc80/tpm.c | 554 ++++++++++++++++++++++++++++++++ src/vendorcode/google/chromeos/vboot.c | 201 ++++++++++++ 6 files changed, 797 insertions(+), 0 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 74fd015..f9ee914 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -254,6 +254,10 @@ config IOAPIC bool default n +config TPM + bool + default n + # TODO: Can probably be removed once all chipsets have kconfig options for it. config VIDEO_MB int diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 168933a..33d730b 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -32,6 +32,9 @@ #include <device/pci.h> #include <cbmem.h> #include <cpu/x86/lapic_def.h> +#if CONFIG_CHROMEOS +#include <vendorcode/google/chromeos/chromeos.h> +#endif u8 acpi_checksum(u8 *table, u32 length) { @@ -524,6 +527,11 @@ void *acpi_find_wakeup_vector(void) if (!acpi_is_wakeup()) return NULL; +#if CONFIG_CHROMEOS + printk(BIOS_DEBUG, "Verified boot TPM initialization.\n"); + init_vboot(); +#endif + printk(BIOS_DEBUG, "Trying to find the wakeup vector...\n"); /* Find RSDP. */ diff --git a/src/include/pc80/tpm.h b/src/include/pc80/tpm.h new file mode 100644 index 0000000..2eff15a --- /dev/null +++ b/src/include/pc80/tpm.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef TPM_H_ +#define TPM_H_ + +int tis_init(void); +int tis_open(void); +int tis_close(void); +int tis_sendrecv(const u8 *sendbuf, size_t send_size, u8 *recvbuf, + size_t *recv_len); + +#endif /* TPM_H_ */ diff --git a/src/pc80/Makefile.inc b/src/pc80/Makefile.inc index 2c8a80e..cd6ea33 100644 --- a/src/pc80/Makefile.inc +++ b/src/pc80/Makefile.inc @@ -4,6 +4,7 @@ ramstage-y += i8254.c ramstage-y += i8259.c ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c +ramstage-$(CONFIG_TPM) += tpm.c romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c subdirs-y += vga diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c new file mode 100644 index 0000000..1cbf800 --- /dev/null +++ b/src/pc80/tpm.c @@ -0,0 +1,554 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * The code in this file has been heavily based on the article "Writing a TPM + * Device Driver" published on http://ptgmedia.pearsoncmg.com and the + * submission by Stefan Berger on Qemu-devel mailing list. + * + * One principal difference is that in the simplest config the other than 0 + * TPM localities do not get mapped by some devices (for instance, by + * Infineon slb9635), so this driver provides access to locality 0 only. + */ + +/* #define DEBUG */ +#include <stdlib.h> +#include <string.h> +#include <delay.h> +#include <arch/io.h> +#include <arch/byteorder.h> +#include <console/console.h> +#include <pc80/tpm.h> + +#ifdef DEBUG +#define TPM_DEBUG_ON 1 +#else +#define TPM_DEBUG_ON 0 +#endif + +#define PREFIX "lpc_tpm: " + +/* coreboot wrapper for TPM driver (start) */ +#define TPM_DEBUG(fmt, args...) \ + if (TPM_DEBUG_ON) { \ + printk(BIOS_DEBUG, PREFIX); \ + printk(BIOS_DEBUG, fmt , ##args); \ + } +#define printf(x...) printk(BIOS_ERR, x) + +#define min(a,b) MIN(a,b) +#define max(a,b) MAX(a,b) +#define readb(_a) (*(volatile unsigned char *) (_a)) +#define writeb(_v, _a) (*(volatile unsigned char *) (_a) = (_v)) +#define readl(_a) (*(volatile unsigned long *) (_a)) +#define writel(_v, _a) (*(volatile unsigned long *) (_a) = (_v)) +/* coreboot wrapper for TPM driver (end) */ + +#ifndef CONFIG_TPM_TIS_BASE_ADDRESS +/* Base TPM address standard for x86 systems */ +#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 +#endif + +/* the macro accepts the locality value, but only locality 0 is operational */ +#define TIS_REG(LOCALITY, REG) \ + (void *)(CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG) + +/* hardware registers' offsets */ +#define TIS_REG_ACCESS 0x0 +#define TIS_REG_INT_ENABLE 0x8 +#define TIS_REG_INT_VECTOR 0xc +#define TIS_REG_INT_STATUS 0x10 +#define TIS_REG_INTF_CAPABILITY 0x14 +#define TIS_REG_STS 0x18 +#define TIS_REG_DATA_FIFO 0x24 +#define TIS_REG_DID_VID 0xf00 +#define TIS_REG_RID 0xf04 + +/* Some registers' bit field definitions */ +#define TIS_STS_VALID (1 << 7) /* 0x80 */ +#define TIS_STS_COMMAND_READY (1 << 6) /* 0x40 */ +#define TIS_STS_TPM_GO (1 << 5) /* 0x20 */ +#define TIS_STS_DATA_AVAILABLE (1 << 4) /* 0x10 */ +#define TIS_STS_EXPECT (1 << 3) /* 0x08 */ +#define TIS_STS_RESPONSE_RETRY (1 << 1) /* 0x02 */ + +#define TIS_ACCESS_TPM_REG_VALID_STS (1 << 7) /* 0x80 */ +#define TIS_ACCESS_ACTIVE_LOCALITY (1 << 5) /* 0x20 */ +#define TIS_ACCESS_BEEN_SEIZED (1 << 4) /* 0x10 */ +#define TIS_ACCESS_SEIZE (1 << 3) /* 0x08 */ +#define TIS_ACCESS_PENDING_REQUEST (1 << 2) /* 0x04 */ +#define TIS_ACCESS_REQUEST_USE (1 << 1) /* 0x02 */ +#define TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0) /* 0x01 */ + +#define TIS_STS_BURST_COUNT_MASK (0xffff) +#define TIS_STS_BURST_COUNT_SHIFT (8) + +/* + * Error value returned if a tpm register does not enter the expected state + * after continuous polling. No actual TPM register reading ever returns ~0, + * so this value is a safe error indication to be mixed with possible status + * register values. + */ +#define TPM_TIMEOUT_ERR (~0) + +/* Error value returned on various TPM driver errors */ +#define TPM_DRIVER_ERR (~0) + + /* 1 second is plenty for anything TPM does.*/ +#define MAX_DELAY_US (1000 * 1000) + +/* Retrieve burst count value out of the status register contents. */ +#define BURST_COUNT(status) ((u16)(((status) >> TIS_STS_BURST_COUNT_SHIFT) & \ + TIS_STS_BURST_COUNT_MASK)) + +/* + * Structures defined below allow creating descriptions of TPM vendor/device + * ID information for run time discovery. The only device the system knows + * about at this time is Infineon slb9635 + */ +struct device_name { + u16 dev_id; + const char * const dev_name; +}; + +struct vendor_name { + u16 vendor_id; + const char * vendor_name; + struct device_name* dev_names; +}; + +static struct device_name infineon_devices[] = { + {0xb, "SLB9635 TT 1.2"}, + {0} +}; + +static const struct vendor_name vendor_names[] = { + {0x15d1, "Infineon", infineon_devices}, +}; + +/* + * Cached vendor/device ID pair to indicate that the device has been already + * discovered + */ +static u32 vendor_dev_id; + +static int is_byte_reg(u32 reg) +{ + /* + * These TPM registers are 8 bits wide and as such require byte access + * on writes and truncated value on reads. + */ + return ((reg == TIS_REG_ACCESS) || + (reg == TIS_REG_INT_VECTOR) || + (reg == TIS_REG_DATA_FIFO)); +} + +/* TPM access functions are carved out to make tracing easier. */ +static u32 tpm_read(int locality, u32 reg) +{ + u32 value; + /* + * Data FIFO register must be read and written in byte access mode, + * otherwise the FIFO values are returned 4 bytes at a time. + */ + if (is_byte_reg(reg)) + value = readb(TIS_REG(locality, reg)); + else + value = readl(TIS_REG(locality, reg)); + + TPM_DEBUG("Read reg 0x%x returns 0x%x\n", reg, value); + return value; +} + +static void tpm_write(u32 value, int locality, u32 reg) +{ + TPM_DEBUG("Write reg 0x%x with 0x%x\n", reg, value); + + if (is_byte_reg(reg)) + writeb(value & 0xff, TIS_REG(locality, reg)); + else + writel(value, TIS_REG(locality, reg)); +} + +/* + * tis_wait_reg() + * + * Wait for at least a second for a register to change its state to match the + * expected state. Normally the transition happens within microseconds. + * + * @reg - the TPM register offset + * @locality - locality + * @mask - bitmask for the bitfield(s) to watch + * @expected - value the field(s) are supposed to be set to + * + * Returns the register contents in case the expected value was found in the + * appropriate register bits, or TPM_TIMEOUT_ERR on timeout. + */ +static u32 tis_wait_reg(u8 reg, u8 locality, u8 mask, u8 expected) +{ + u32 time_us = MAX_DELAY_US; + while (time_us > 0) { + u32 value = tpm_read(locality, reg); + if ((value & mask) == expected) + return value; + udelay(1); /* 1 us */ + time_us--; + } + return TPM_TIMEOUT_ERR; +} + +/* + * Probe the TPM device and try determining its manufacturer/device name. + * + * Returns 0 on success (the device is found or was found during an earlier + * invocation) or TPM_DRIVER_ERR if the device is not found. + */ +static u32 tis_probe(void) +{ + u32 didvid = tpm_read(0, TIS_REG_DID_VID); + int i; + const char *device_name = "unknown"; + const char *vendor_name = device_name; + u16 vid, did; + + if (vendor_dev_id) + return 0; /* Already probed. */ + + if (!didvid || (didvid == 0xffffffff)) { + printf("%s: No TPM device found\n", __FUNCTION__); + return TPM_DRIVER_ERR; + } + + vendor_dev_id = didvid; + + vid = didvid & 0xffff; + did = (didvid >> 16) & 0xffff; + for (i = 0; i < ARRAY_SIZE(vendor_names); i++) { + int j = 0; + u16 known_did; + if (vid == vendor_names[i].vendor_id) { + vendor_name = vendor_names[i].vendor_name; + } + while ((known_did = vendor_names[i].dev_names[j].dev_id) != 0) { + if (known_did == did) { + device_name = + vendor_names[i].dev_names[j].dev_name; + break; + } + j++; + } + break; + } + /* this will have to be converted into debug printout */ + TPM_DEBUG("Found TPM %s by %s\n", device_name, vendor_name); + return 0; +} + +/* + * tis_senddata() + * + * send the passed in data to the TPM device. + * + * @data - address of the data to send, byte by byte + * @len - length of the data to send + * + * Returns 0 on success, TPM_DRIVER_ERR on error (in case the device does + * not accept the entire command). + */ +static u32 tis_senddata(const u8 * const data, u32 len) +{ + u32 offset = 0; + u16 burst = 0; + u32 max_cycles = 0; + u8 locality = 0; + u32 value; + + value = tis_wait_reg(TIS_REG_STS, locality, TIS_STS_COMMAND_READY, + TIS_STS_COMMAND_READY); + if (value == TPM_TIMEOUT_ERR) { + printf("%s:%d - failed to get 'command_ready' status\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + burst = BURST_COUNT(value); + + while (1) { + unsigned count; + + /* Wait till the device is ready to accept more data. */ + while (!burst) { + if (max_cycles++ == MAX_DELAY_US) { + printf("%s:%d failed to feed %d bytes of %d\n", + __FILE__, __LINE__, len - offset, len); + return TPM_DRIVER_ERR; + } + udelay(1); + burst = BURST_COUNT(tpm_read(locality, TIS_REG_STS)); + } + + max_cycles = 0; + + /* + * Calculate number of bytes the TPM is ready to accept in one + * shot. + * + * We want to send the last byte outside of the loop (hence + * the -1 below) to make sure that the 'expected' status bit + * changes to zero exactly after the last byte is fed into the + * FIFO. + */ + count = min(burst, len - offset - 1); + while (count--) + tpm_write(data[offset++], locality, TIS_REG_DATA_FIFO); + + value = tis_wait_reg(TIS_REG_STS, locality, + TIS_STS_VALID, TIS_STS_VALID); + + if ((value == TPM_TIMEOUT_ERR) || !(value & TIS_STS_EXPECT)) { + printf("%s:%d TPM command feed overflow\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + + burst = BURST_COUNT(value); + if ((offset == (len - 1)) && burst) + /* + * We need to be able to send the last byte to the + * device, so burst size must be nonzero before we + * break out. + */ + break; + } + + /* Send the last byte. */ + tpm_write(data[offset++], locality, TIS_REG_DATA_FIFO); + + /* + * Verify that TPM does not expect any more data as part of this + * command. + */ + value = tis_wait_reg(TIS_REG_STS, locality, + TIS_STS_VALID, TIS_STS_VALID); + if ((value == TPM_TIMEOUT_ERR) || (value & TIS_STS_EXPECT)) { + printf("%s:%d unexpected TPM status 0x%x\n", + __FILE__, __LINE__, value); + return TPM_DRIVER_ERR; + } + + /* OK, sitting pretty, let's start the command execution. */ + tpm_write(TIS_STS_TPM_GO, locality, TIS_REG_STS); + + return 0; +} + +/* + * tis_readresponse() + * + * read the TPM device response after a command was issued. + * + * @buffer - address where to read the response, byte by byte. + * @len - pointer to the size of buffer + * + * On success stores the number of received bytes to len and returns 0. On + * errors (misformatted TPM data or synchronization problems) returns + * TPM_DRIVER_ERR. + */ +static u32 tis_readresponse(u8 *buffer, size_t *len) +{ + u16 burst_count; + u32 status; + u32 offset = 0; + u8 locality = 0; + const u32 has_data = TIS_STS_DATA_AVAILABLE | TIS_STS_VALID; + u32 expected_count = *len; + int max_cycles = 0; + + /* Wait for the TPM to process the command */ + status = tis_wait_reg(TIS_REG_STS, locality, has_data, has_data); + if (status == TPM_TIMEOUT_ERR) { + printf("%s:%d failed processing command\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + + do { + while ((burst_count = BURST_COUNT(status)) == 0) { + if (max_cycles++ == MAX_DELAY_US) { + printf("%s:%d TPM stuck on read\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + udelay(1); + status = tpm_read(locality, TIS_REG_STS); + } + + max_cycles = 0; + + while (burst_count-- && (offset < expected_count)) { + buffer[offset++] = (u8) tpm_read(locality, + TIS_REG_DATA_FIFO); + if (offset == 6) { + /* + * We got the first six bytes of the reply, + * let's figure out how many bytes to expect + * total - it is stored as a 4 byte number in + * network order, starting with offset 2 into + * the body of the reply. + */ + u32 real_length; + memcpy(&real_length, + buffer + 2, + sizeof(real_length)); + expected_count = be32_to_cpu(real_length); + + if ((expected_count < offset) || + (expected_count > *len)) { + printf("%s:%d bad response size %d\n", + __FILE__, __LINE__, + expected_count); + return TPM_DRIVER_ERR; + } + } + } + + /* Wait for the next portion */ + status = tis_wait_reg(TIS_REG_STS, locality, + TIS_STS_VALID, TIS_STS_VALID); + if (status == TPM_TIMEOUT_ERR) { + printf("%s:%d failed to read response\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + + if (offset == expected_count) + break; /* We got all we need */ + + } while ((status & has_data) == has_data); + + /* + * Make sure we indeed read all there was. The TIS_STS_VALID bit is + * known to be set. + */ + if (status & TIS_STS_DATA_AVAILABLE) { + printf("%s:%d wrong receive status %x\n", + __FILE__, __LINE__, status); + return TPM_DRIVER_ERR; + } + + /* Tell the TPM that we are done. */ + tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS); + + *len = offset; + return 0; +} + +/* + * tis_init() + * + * Initialize the TPM device. Returns 0 on success or TPM_DRIVER_ERR on + * failure (in case device probing did not succeed). + */ +int tis_init(void) +{ + if (tis_probe()) + return TPM_DRIVER_ERR; + return 0; +} + +/* + * tis_open() + * + * Requests access to locality 0 for the caller. After all commands have been + * completed the caller is supposed to call tis_close(). + * + * Returns 0 on success, TPM_DRIVER_ERR on failure. + */ +int tis_open(void) +{ + u8 locality = 0; /* we use locality zero for everything */ + + if (tis_close()) + return TPM_DRIVER_ERR; + + /* now request access to locality */ + tpm_write(TIS_ACCESS_REQUEST_USE, locality, TIS_REG_ACCESS); + + /* did we get a lock? */ + if (tis_wait_reg(TIS_REG_ACCESS, locality, + TIS_ACCESS_ACTIVE_LOCALITY, + TIS_ACCESS_ACTIVE_LOCALITY) == TPM_TIMEOUT_ERR) { + printf("%s:%d - failed to lock locality %d\n", + __FILE__, __LINE__, locality); + return TPM_DRIVER_ERR; + } + + tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS); + + return 0; +} + +/* + * tis_close() + * + * terminate the currect session with the TPM by releasing the locked + * locality. Returns 0 on success of TPM_DRIVER_ERR on failure (in case lock + * removal did not succeed). + */ +int tis_close(void) +{ + u8 locality = 0; + if (tpm_read(locality, TIS_REG_ACCESS) & + TIS_ACCESS_ACTIVE_LOCALITY) { + tpm_write(TIS_ACCESS_ACTIVE_LOCALITY, locality, TIS_REG_ACCESS); + + if (tis_wait_reg(TIS_REG_ACCESS, locality, + TIS_ACCESS_ACTIVE_LOCALITY, 0) == + TPM_TIMEOUT_ERR) { + printf("%s:%d - failed to release locality %d\n", + __FILE__, __LINE__, locality); + return TPM_DRIVER_ERR; + } + } + return 0; +} + +/* + * tis_sendrecv() + * + * Send the requested data to the TPM and then try to get its response + * + * @sendbuf - buffer of the data to send + * @send_size size of the data to send + * @recvbuf - memory to save the response to + * @recv_len - pointer to the size of the response buffer + * + * Returns 0 on success (and places the number of response bytes at recv_len) + * or TPM_DRIVER_ERR on failure. + */ +int tis_sendrecv(const uint8_t *sendbuf, size_t send_size, + uint8_t *recvbuf, size_t *recv_len) +{ + if (tis_senddata(sendbuf, send_size)) { + printf("%s:%d failed sending data to TPM\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + + return tis_readresponse(recvbuf, recv_len); +} diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c new file mode 100644 index 0000000..e0a8c9b --- /dev/null +++ b/src/vendorcode/google/chromeos/vboot.c @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <pc80/tpm.h> +#include "chromeos.h" + +//#define EXTRA_LOGGING + +#define TPM_LARGE_ENOUGH_COMMAND_SIZE 256 /* saves space in the firmware */ + +#define TPM_SUCCESS ((u32)0x00000000) + +#define TPM_E_IOERROR ((u32)0x0000001f) +#define TPM_E_COMMUNICATION_ERROR ((u32)0x00005004) +#define TPM_E_NON_FATAL ((u32)0x00000800) +#define TPM_E_INVALID_POSTINIT ((u32)0x00000026) + +#define TPM_E_NEEDS_SELFTEST ((u32)(TPM_E_NON_FATAL + 1)) +#define TPM_E_DOING_SELFTEST ((u32)(TPM_E_NON_FATAL + 2)) + +static const struct { + u8 buffer[12]; +} tpm_resume_cmd = { + { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2 } +}; + +static const struct { + u8 buffer[10]; +} tpm_continueselftest_cmd = { + { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 } +}; + +static inline void FromTpmUint32(const u8 * buffer, u32 * x) +{ + *x = ((buffer[0] << 24) | + (buffer[1] << 16) | (buffer[2] << 8) | buffer[3]); +} + +static inline int TpmCommandSize(const u8 * buffer) +{ + u32 size; + FromTpmUint32(buffer + sizeof(u16), &size); + return (int)size; +} + +/* Gets the code field of a TPM command. */ +static inline int TpmCommandCode(const u8 * buffer) +{ + u32 code; + FromTpmUint32(buffer + sizeof(u16) + sizeof(u32), &code); + return code; +} + +/* Gets the return code field of a TPM result. */ +static inline int TpmReturnCode(const u8 * buffer) +{ + return TpmCommandCode(buffer); +} + +/* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or + * DOING_SELFTEST errors are returned. + */ +static u32 TlclSendReceiveNoRetry(const u8 * request, + u8 * response, int max_length) +{ + size_t response_length = max_length; + u32 result; + +#ifdef EXTRA_LOGGING + printk(BIOS_DEBUG, "TPM: command: %x%x %x%x%x%x %x%x%x%x\n", + request[0], request[1], + request[2], request[3], request[4], request[5], + request[6], request[7], request[8], request[9]); +#endif + + result = TPM_SUCCESS; + if (tis_sendrecv + (request, TpmCommandSize(request), response, &response_length)) + result = TPM_E_IOERROR; + + if (0 != result) { + /* Communication with TPM failed, so response is garbage */ + printk(BIOS_DEBUG, + "TPM: command 0x%x send/receive failed: 0x%x\n", + TpmCommandCode(request), result); + return TPM_E_COMMUNICATION_ERROR; + } + /* Otherwise, use the result code from the response */ + result = TpmReturnCode(response); + +/* TODO: add paranoia about returned response_length vs. max_length + * (and possibly expected length from the response header). See + * crosbug.com/17017 */ + +#ifdef EXTRA_LOGGING + printk(BIOS_DEBUG, "TPM: response: %x%x %x%x%x%x %x%x%x%x\n", + response[0], response[1], + response[2], response[3], response[4], response[5], + response[6], response[7], response[8], response[9]); +#endif + + printk(BIOS_DEBUG, "TPM: command 0x%x returned 0x%x\n", + TpmCommandCode(request), result); + + return result; +} + +static inline u32 TlclContinueSelfTest(void) +{ + u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + printk(BIOS_DEBUG, "TPM: Continue self test\n"); + /* Call the No Retry version of SendReceive to avoid recursion. */ + return TlclSendReceiveNoRetry(tpm_continueselftest_cmd.buffer, + response, sizeof(response)); +} + +/* Sends a TPM command and gets a response. Returns 0 if success or the TPM + * error code if error. In the firmware, waits for the self test to complete + * if needed. In the host, reports the first error without retries. */ +static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length) +{ + u32 result = TlclSendReceiveNoRetry(request, response, max_length); + /* When compiling for the firmware, hide command failures due to the self + * test not having run or completed. */ + /* If the command fails because the self test has not completed, try it + * again after attempting to ensure that the self test has completed. */ + if (result == TPM_E_NEEDS_SELFTEST || result == TPM_E_DOING_SELFTEST) { + result = TlclContinueSelfTest(); + if (result != TPM_SUCCESS) { + return result; + } +#if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE) + /* Retry only once */ + result = TlclSendReceiveNoRetry(request, response, max_length); +#else + /* This needs serious testing. The TPM specification says: + * "iii. The caller MUST wait for the actions of + * TPM_ContinueSelfTest to complete before reissuing the + * command C1." But, if ContinueSelfTest is non-blocking, how + * do we know that the actions have completed other than trying + * again? */ + do { + result = + TlclSendReceiveNoRetry(request, response, + max_length); + } while (result == TPM_E_DOING_SELFTEST); +#endif + } + + return result; +} + +void init_vboot(void) +{ + u32 result; + u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + + printk(BIOS_DEBUG, "TPM: Init\n"); + if (tis_init()) + return; + + printk(BIOS_DEBUG, "TPM: Open\n"); + if (tis_open()) + return; + + printk(BIOS_DEBUG, "TPM: Resume\n"); + + result = + TlclSendReceive(tpm_resume_cmd.buffer, response, sizeof(response)); + + if (result == TPM_E_INVALID_POSTINIT) { + /* We're on a platform where the TPM maintains power in S3, so + * it's already initialized. */ + printk(BIOS_DEBUG, "TPM: Already initialized.\n"); + return; + } + if (result == TPM_SUCCESS) { + printk(BIOS_DEBUG, "TPM: OK.\n"); + return; + } + // TODO(reinauer) hard reboot? +}

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Patch merged into coreboot/master: 2bdfda7 Detect whether the OXPCIE card is really present while in the ROM stage.
by gerrit＠coreboot.org 29 Mar '12

29 Mar '12

the following patch was just integrated into master: commit 2bdfda7e68e9a80fd733abfc08b1e382e5f02ac1 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Oct 5 01:52:08 2011 -0700 Detect whether the OXPCIE card is really present while in the ROM stage. Use an int in CAR global data to store whether or not the OXPCIE serial card is actually there. Also, time out if the card doesn't show up quickly enough, don't continue initialization if it's not there, and don't make the initialization routine default to a card if none is found. Change-Id: I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c Signed-off-by: Gabe Black <gabeblack(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 9 16:51:21 2012, giving +1 See http://review.coreboot.org/728 for details. -gerrit

1 0

Patch set updated for coreboot: 3a11ccf Add infrastructure for global data in the CAR phase of boot
by Stefan Reinauer 29 Mar '12

29 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/727 -gerrit commit 3a11ccf569f5220f861bdab28b693c18954f8d26 Author: Gabe Black <gabeblack(a)google.com> Date: Sat Oct 1 04:27:32 2011 -0700 Add infrastructure for global data in the CAR phase of boot The cbmem console structure and car global data are put in their own section, with the cbmem console coming after the global data. These areas are linked to be where CAR is available and at the very bottom of the stack. There is one shortcoming of this change: The section created by this change needs to be stripped out by the Makefile since leaving it in confuses cbfstool when it installs the stage in the image. I would like to make the tools link those symbols at the right location but leave allocation of that space out of the ELF. Change-Id: Iccfb99b128d59c5b7d6164796d21ba46d2a674e0 Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/arch/x86/Makefile.inc | 2 +- src/arch/x86/init/bootblock.ld | 7 +++++++ src/include/cpu/x86/car.h | 31 +++++++++++++++++++++++++++++++ src/lib/cbmem_console.c | 7 +++++-- 4 files changed, 44 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index fc3cd14..d378a20 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -272,7 +272,7 @@ $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) rm -f $@ cp $(obj)/coreboot.pre1 $@ $(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \ - $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) + $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) #FIXME: location.txt might require an offset of header size ####################################################################### diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld index 27d718f..ca4e820 100644 --- a/src/arch/x86/init/bootblock.ld +++ b/src/arch/x86/init/bootblock.ld @@ -46,5 +46,12 @@ SECTIONS *(.eh_frame); } + . = CONFIG_DCACHE_RAM_BASE; + .car.data . (NOLOAD) : { + *(.car.global_data); + *(.car.cbmem_console); + } + + _bogus = ASSERT((SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_CPU_AMD_AGESA, "Do not use global variables in romstage"); } diff --git a/src/include/cpu/x86/car.h b/src/include/cpu/x86/car.h new file mode 100644 index 0000000..2d2af03 --- /dev/null +++ b/src/include/cpu/x86/car.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef CPU_X86_CAR_H +#define CPU_X86_CAR_H + +#ifdef __PRE_RAM__ +#define CAR_GLOBAL __attribute__((section(".car.global_data,\"w\",@nobits#"))) +#define CAR_CBMEM __attribute__((section(".car.cbmem_console,\"w\",@nobits#"))) +#else +#define CAR_GLOBAL +#define CAR_CBMEM +#endif + +#endif diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 8cfb33b..2e22dec 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <cbmem.h> +#include <cpu/x86/car.h> #include <string.h> /* @@ -39,7 +40,9 @@ struct cbmem_console { * ram space is used for the console buffer storage. The size and location of * the area are defined in the config. */ -#define cbmem_console_p ((struct cbmem_console *)CONFIG_DCACHE_RAM_BASE) + +static struct cbmem_console car_cbmem_console CAR_CBMEM; +#define cbmem_console_p (&car_cbmem_console) /* * Once DRAM is initialized and the cache as ram mode is disabled, while still @@ -92,7 +95,7 @@ void cbmemc_tx_byte(unsigned char data) * DCACHE_RAM_BASE), use the redirect pointer to find out where the * actual console buffer is. */ - if ((u32)&cursor < (u32)CONFIG_DCACHE_RAM_BASE) + if ((uintptr_t)&cursor < (uintptr_t)&car_cbmem_console) cbm_cons_p = CBMEM_CONSOLE_REDIRECT; #endif if (!cbm_cons_p)

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Patch merged into coreboot/master: 0959090 Fix typos in src/console/Kconfig
by gerrit＠coreboot.org 29 Mar '12

29 Mar '12

the following patch was just integrated into master: commit 0959090a5524f258a928986fa20e75f21e6f68f8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 4 16:21:17 2011 -0700 Fix typos in src/console/Kconfig - cash -> Cache - make the new size of the cbmem console buffer the default Change-Id: Ia906077257e93622ad56bc54a42f8184ade78b29 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Thu Mar 29 22:25:28 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Mar 29 22:34:41 2012, giving +2 See http://review.coreboot.org/726 for details. -gerrit

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Patch merged into coreboot/master: a8c3524 Add support for enabling PCIe Common Clock and ASPM
by gerrit＠coreboot.org 29 Mar '12

29 Mar '12

the following patch was just integrated into master: commit a8c35245174b3e3f7bd92025468fa54433041fda Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 14:15:11 2011 -0700 Add support for enabling PCIe Common Clock and ASPM These are guarded by individual Kconfig entries. The deprecated CONFIG_PCIE_TUNING defines have been removed in favor of using specific config options. This is the generic half, there is board-specific pieces still to come that tune before and after ASPM is enabled. Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Build-Tested: build bot (Jenkins) at Sat Mar 10 05:16:04 2012, giving +1 See http://review.coreboot.org/735 for details. -gerrit

1 0

Patch set updated for coreboot: 0959090 Fix typos in src/console/Kconfig
by Stefan Reinauer 29 Mar '12

29 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/726 -gerrit commit 0959090a5524f258a928986fa20e75f21e6f68f8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 4 16:21:17 2011 -0700 Fix typos in src/console/Kconfig - cash -> Cache - make the new size of the cbmem console buffer the default Change-Id: Ia906077257e93622ad56bc54a42f8184ade78b29 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/console/Kconfig | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index fefbe2e..f1129a1 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -201,15 +201,15 @@ config CONSOLE_CBMEM config CONSOLE_CBMEM_BUFFER_SIZE depends on CONSOLE_CBMEM hex "Room allocated for console output in CBMEM" - default 0xae00 + default 0x10000 help Space allocated for console output storage in CBMEM. The default - value (almost 45K or 0xaeoo bytes) is large enough to accommodate + value (64K or 0x10000 bytes) is large enough to accommodate even the BIOS_SPEW level. config CONSOLE_CAR_BUFFER_SIZE depends on CONSOLE_CBMEM - hex "Room allocated for console output in cash as RAM" + hex "Room allocated for console output in Cache as RAM" default 0xc00 help Console is used before RAM is initialized. This is the room reserved

1 0

Re: [coreboot] Can I use gdb debug tool with coreboot v4.0?
by Stefan Reinauer 29 Mar '12

29 Mar '12

* Julian Shulika <hercares(a)gmail.com> [120329 14:28]: > Hi , everyone! Can I use gdb debug tool with coreboot v4.0? This information is > oudated > > > coreboot has an easy to use interface to the GNU debugger gdb. To enable it, > add the following two lines to your mainboard's Options.lb: > > uses CONFIG_GDB_STUB > ... > default CONFIG_GDB_STUB=1 I updated http://www.coreboot.org/Debugging to reflect the current situation. Stefan

1 0

Patch merged into coreboot/master: 3ec1727 Refactor publishing CBMEM addresses through coreboot table.
by gerrit＠coreboot.org 29 Mar '12

29 Mar '12

the following patch was just integrated into master: commit 3ec1727e7072024e075615b067aeff001539a9b7 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Oct 3 14:58:57 2011 -0700 Refactor publishing CBMEM addresses through coreboot table. We need to provide u-boot access to several different CBMEM sections. To do that, a common coreboot table structure is used, just different tags match different coreboot table sections. Also, the code is added to export CBMEM console and MRC cache addresses through the same mechanism. Change-Id: I63adb67093b8b50ee61b0deb0b56ebb2c4856895 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Build-Tested: build bot (Jenkins) at Fri Mar 9 20:03:43 2012, giving +1 See http://review.coreboot.org/724 for details. -gerrit

1 0

Patch merged into coreboot/master: 8cdfe4b Add timestamp table pointer to the coreboot table.
by gerrit＠coreboot.org 29 Mar '12

29 Mar '12

the following patch was just integrated into master: commit 8cdfe4b772d367a4036eec4ce1e1df23c1ed0699 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Sep 23 09:56:11 2011 -0700 Add timestamp table pointer to the coreboot table. This change exports the timestamp table pointer through coreboot table to make it possible for u-boot to add timestamps to the table. Inclusion of cbmem.h allows to drop external declarations in coreboot_table.c. Change-Id: Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Build-Tested: build bot (Jenkins) at Fri Mar 9 15:34:15 2012, giving +1 See http://review.coreboot.org/716 for details. -gerrit

1 0

Patch merged into coreboot/master: 930ecd2 Introduce utility for parsing CBMEM contents.
by gerrit＠coreboot.org 29 Mar '12

29 Mar '12

the following patch was just integrated into master: commit 930ecd22286a3a8f708e562362cef1e3a81f0200 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Sep 30 14:21:03 2011 -0700 Introduce utility for parsing CBMEM contents. This is a python script which is supposed to run on a target which is controlled by coreboot. The script examines top of memory looking for the CBMEM signature at addresses aligned at 128K boundary. Once the script finds the CBMEM, it iterates through the CBMEM table of contents and parses two entries: the timestamps and the console log. This submission is just a template to build upon to create a utility for displaying CBMEM information while running Linux on the target. BUG=chrome-os-partner:4200 TEST=manual See test description of d81e6b8c8d41f2d6 for test procedure. Change-Id: Id863a8598eaadc2d20d728f9186843e65cbe6f37 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://gerrit-int.chromium.org/5942 Tested-by: Vadim Bendebury <vbendeb(a)google.com> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 9 19:45:29 2012, giving +1 See http://review.coreboot.org/723 for details. -gerrit

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coreboot March 2012