coreboot November 2012

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895 discussions

New patch to review for coreboot: d1603db pirq_route_irqs is private
by Patrick Georgi 28 Nov '12

28 Nov '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1936 -gerrit commit d1603dbe0615e4d4defea99eeecfd9fcb5e80605 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Oct 8 09:33:38 2012 +0200 pirq_route_irqs is private Change-Id: I120913dac3150a72c2e66c74872ee00074ee0267 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/boot/pirq_routing.c | 2 +- src/arch/x86/include/arch/pirq_routing.h | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/src/arch/x86/boot/pirq_routing.c b/src/arch/x86/boot/pirq_routing.c index 55deac1..ca74862 100644 --- a/src/arch/x86/boot/pirq_routing.c +++ b/src/arch/x86/boot/pirq_routing.c @@ -145,7 +145,7 @@ static u8 pirq_get_next_free_irq(u8* pirq, u16 bitmap) return irq; } -void pirq_route_irqs(unsigned long addr) +static void pirq_route_irqs(unsigned long addr) { int i, intx, num_entries; unsigned char irq_slot[MAX_INTX_ENTRIES]; diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h index 9488473..241ec3b 100644 --- a/src/arch/x86/include/arch/pirq_routing.h +++ b/src/arch/x86/include/arch/pirq_routing.h @@ -67,10 +67,7 @@ unsigned long copy_pirq_routing_table(unsigned long addr, const struct irq_routi unsigned long write_pirq_routing_table(unsigned long start); #if CONFIG_PIRQ_ROUTE -void pirq_route_irqs(unsigned long start); void pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]); -#else -#define pirq_route_irqs(start) {} #endif #else

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Re: [coreboot] 486 Motherboard from scratch
by Rex O'Regan 27 Nov '12

27 Nov '12

Thinking about the ARM stuff... perhaps if I put my 486 mobo on hold and just build an ARM based DSO... I have an old laptop that would make a pretty sweet case for one with a little refurbishment. Use coreboot with a linux payload that defaultly runs a DSO program... use existing swappable sections(CDROM) for swappable input/output configurations... Suggestions, queries, recommendations? Cheers, Rex

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Patch merged into coreboot/master: 5079a0d Remove assembly coded log2 function
by gerrit＠coreboot.org 27 Nov '12

27 Nov '12

the following patch was just integrated into master: commit 5079a0d32f2824445cf593dfbcb65598eaa97dee Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Nov 27 11:32:38 2012 -0800 Remove assembly coded log2 function As we move to supporting other systems we need to get rid of assembly where we can. The log2 function in src/lib is identical to the assembly one (tested for all 32-bit signed integers :-) and takes about 10 ns to run as opposed to 5ns for the non-portable assembly version. While speed is good, I think we can spare the 15 ns or so we add to boot time by using the C version only. Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/1928 Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Wed Nov 28 01:33:26 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Nov 28 07:57:08 2012, giving +2 See http://review.coreboot.org/1928 for details. -gerrit

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Patch merged into coreboot/master: acf4431 add .h files for common exynos 5
by gerrit＠coreboot.org 27 Nov '12

27 Nov '12

the following patch was just integrated into master: commit acf443191bd035c26ee89c3ca56f065a5111901b Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Nov 27 10:48:56 2012 -0800 add .h files for common exynos 5 Change-Id: I48497adc29a1b8ca11d1e0a5d879cab5b6b55dcd Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/1926 Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Wed Nov 28 00:38:11 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Nov 28 07:55:24 2012, giving +2 See http://review.coreboot.org/1926 for details. -gerrit

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Patch merged into coreboot/master: 6e3728b Add .h files for samsung exynos 5250
by gerrit＠coreboot.org 27 Nov '12

27 Nov '12

the following patch was just integrated into master: commit 6e3728bb12688e8de300c04d5e7a688bc99a2d15 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Nov 27 10:36:06 2012 -0800 Add .h files for samsung exynos 5250 Per a conversation with Stefan, these chip-dependent files are moved to the src tree, in the manner of other chips (north and southbridge). Change-Id: I12645ba05eb241eda200ed06cb633541a6a98119 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Reviewed-on: http://review.coreboot.org/1925 Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Wed Nov 28 00:31:56 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Nov 28 07:55:51 2012, giving +2 See http://review.coreboot.org/1925 for details. -gerrit

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Patch merged into coreboot/master: bbc880e amdk8/amdfam10: Use CAR_GLOBAL for sysinfo
by gerrit＠coreboot.org 27 Nov '12

27 Nov '12

the following patch was just integrated into master: commit bbc880eee702fc175d4a3c3e87b682c26c38f940 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Tue Nov 20 18:20:56 2012 +0100 amdk8/amdfam10: Use CAR_GLOBAL for sysinfo This gets rid of the somewhat unstructured placement of AMD's sysinfo structure in CAR. We used to carve out some CAR space using a Kconfig variable, and then put sysinfo there manually (by "virtue" of pointer magic). Now it's a variable with the CAR_GLOBAL qualifier, and build system magic. For this, the following steps were done (but must happen together since the intermediates won't build): - Add new CAR_GLOBAL sysinfo_car - point all sysinfo pointers to sysinfo_car instead of GLOBAL_VAR - remove DCACHE_RAM_GLOBAL_VAR_SIZE - from CAR setup (no need to reserve the space) - commented out code (that was commented out for years) - only copy sizeof(sysinfo) into RAM after ram init, where before it copied the whole GLOBAL_VAR area. - from Kconfig Change-Id: I3cbcccd883ca6751326c8e32afde2eb0c91229ed Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/1887 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Marc Jones <marcj303(a)gmail.com> See http://review.coreboot.org/1887 for details. -gerrit

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New patch to review for coreboot: eb77a18 crossgcc: Only build iasl in acpica.
by Zheng Bao 27 Nov '12

27 Nov '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1935 -gerrit commit eb77a186233aa8c9e01a2740fe8906928e96defb Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Wed Nov 28 16:13:40 2012 +0800 crossgcc: Only build iasl in acpica. Other acpica's modules are not needed. Change-Id: I16846caa922aded8db7c1d9e64c007fb2772ff98 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- util/crossgcc/buildgcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 983dd3b..8689e1a 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -601,7 +601,7 @@ printf "Building IASL ${IASL_VERSION} ... " export PATH=$PATH:$DESTDIR$TARGETDIR/bin rm -f ../../source/compiler/.failed CFLAGS="$HOSTCFLAGS" - $MAKE CC="$CC" || touch ../../source/compiler/.failed + $MAKE CC="$CC" iasl || touch ../../source/compiler/.failed rm -f $DESTDIR$TARGETDIR/bin/iasl || touch ../../source/compiler/.failed if [ -d bin32 ]; then cp bin32/iasl $DESTDIR$TARGETDIR/bin || touch ../../source/compiler/.failed ; fi if [ -d bin64 ]; then cp bin64/iasl $DESTDIR$TARGETDIR/bin || touch ../../source/compiler/.failed ; fi

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Patch set updated for coreboot: dd8ac27 AMD S3: Leverage the public SPI routine
by Zheng Bao 27 Nov '12

27 Nov '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1920 -gerrit commit dd8ac275bf9246f894714e4dde17b5c9117fd225 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Wed Nov 28 11:36:52 2012 +0800 AMD S3: Leverage the public SPI routine Remove the old, unflexible code for storing S3 data in SPI flash. Refer to flashrom. Tested on Parmer. Change-Id: I60a10476befb4afab2b4241f01a988f4a8bb22cd Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 88 ++++++------- src/southbridge/amd/Kconfig | 4 + src/southbridge/amd/agesa/hudson/spi.c | 232 ++++++++++----------------------- src/southbridge/amd/agesa/hudson/spi.h | 43 ------ src/southbridge/amd/cimx/sb800/spi.c | 228 ++++++++++---------------------- src/southbridge/amd/cimx/sb800/spi.h | 42 ------ 6 files changed, 179 insertions(+), 458 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 0348a9f..6302c3d 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -41,7 +41,8 @@ #include "agesawrapper.h" #ifndef __PRE_RAM__ -#include "spi.h" +#include <spi.h> +#include <spi_flash.h> #endif void restore_mtrr(void) @@ -151,14 +152,18 @@ void move_stack_high_mem(void) void OemAgesaSaveMtrr(void) { #ifndef __PRE_RAM__ - u32 spi_address; msr_t msr_data; - device_t dev; u32 nvram_pos = S3_DATA_MTRR_POS; u32 i; + struct spi_flash *flash; - dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); - spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + spi_init(); + + flash = spi_flash_probe(0, 0, 0, 0); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + return; + } /* Enable access to AMD RdDram and WrDram extension bits */ msr_data = rdmsr(SYS_CFG); @@ -167,28 +172,29 @@ void OemAgesaSaveMtrr(void) /* Fixed MTRRs */ msr_data = rdmsr(0x250); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; msr_data = rdmsr(0x258); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; msr_data = rdmsr(0x259); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; for (i = 0x268; i < 0x270; i++) { msr_data = rdmsr(i); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; } @@ -200,35 +206,33 @@ void OemAgesaSaveMtrr(void) /* Variable MTRRs */ for (i = 0x200; i < 0x210; i++) { msr_data = rdmsr(i); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; } /* SYS_CFG */ msr_data = rdmsr(0xC0010010); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; /* TOM */ msr_data = rdmsr(0xC001001A); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; /* TOM2 */ msr_data = rdmsr(0xC001001D); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; - write_spi_status((u8 *)spi_address, 0x3c); - spi_write_disable((u8 *) spi_address); #endif } @@ -251,9 +255,9 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) { u32 pos = S3_DATA_VOLATILE_POS; - u32 spi_address, data; + u32 data; u32 nvram_pos; - device_t dev; + struct spi_flash *flash; if (S3DataType == S3DataTypeNonVolatile) { pos = S3_DATA_NONVOLATILE_POS; @@ -261,39 +265,27 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) pos = S3_DATA_VOLATILE_POS; } - dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); - spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + spi_init(); + flash = spi_flash_probe(0, 0, 0, 0); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + /* Dont make flow stop. */ + return AGESA_SUCCESS; + } - /* printk(BIOS_DEBUG, "spi_address=%x\n", spi_address); */ - read_spi_id((u8 *) spi_address); - write_spi_status((u8 *)spi_address, 0); if (S3DataType == S3DataTypeNonVolatile) { - sector_erase_spi((u8 *) spi_address, S3_DATA_NONVOLATILE_POS); + flash->erase(flash, S3_DATA_NONVOLATILE_POS, 0x1000); } else { - sector_erase_spi((u8 *) spi_address, S3_DATA_VOLATILE_POS); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x1000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x2000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x3000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x4000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x5000); + flash->erase(flash, S3_DATA_VOLATILE_POS, 0x6000); } nvram_pos = 0; - dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos, DataSize); + flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize); for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { data = *(u32 *) (Data + nvram_pos); - dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos + 4, - *(u32 *) (Data + nvram_pos)); + flash->write(flash, nvram_pos + pos + 4, sizeof(u32), (u32 *)(Data + nvram_pos)); } - /* write_spi_status((u8 *)spi_address, 0x3c); */ - - /* spi_write_disable((u8 *) spi_address); */ return AGESA_SUCCESS; } diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 867afca..20d5573 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -14,3 +14,7 @@ source src/southbridge/amd/sb800/Kconfig source src/southbridge/amd/cimx/Kconfig source src/southbridge/amd/agesa/Kconfig source src/southbridge/amd/sr5650/Kconfig + +config SPI_FLASH + bool + default y if HAVE_ACPI_RESUME && CPU_AMD_AGESA diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index ad8b6d4..3b54490 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -16,203 +16,107 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> #include <arch/io.h> +#include <spi.h> #include <device/device.h> -#include "spi.h" +#include <device/pci.h> +#include <device/pci_ops.h> -void execute_command(volatile u8 * spi_address) -{ - *(spi_address + 2) |= 1; -} +static u32 spibar; -void wait4command_complete(volatile u8 * spi_address) +static void reset_internal_fifo_pointer(void) { -// while (*(spi_address + 2) & 1) - while ((*(spi_address + 2) & 1) && (*(spi_address + 3) & 0x80)) - printk(BIOS_DEBUG, "wait4CommandComplete\n"); + do { + write8(spibar + 2, read8(spibar + 2) | 0x10); + } while (read8(spibar + 0xD) & 0x7); } -void reset_internal_fifo_pointer(volatile u8 * spi_address) +static void execute_command(void) { - u8 val; + write8(spibar + 2, read8(spibar + 2) | 1); - do { - *(spi_address + 2) |= 0x10; - val = *(spi_address + 0xd); - } while (val & 0x7); + while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80)); } -u8 read_spi_status(volatile u8 * spi_address) +void spi_init() { - u8 val; - *spi_address = 0x05; - *(spi_address + 1) = 0x21; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0x0; /* dummy */ - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - val = *(spi_address + 0xC); - val = *(spi_address + 0xC); - val = *(spi_address + 0xC); - return val; -} + device_t dev; -void wait4flashpart_ready(volatile u8 * spi_address) -{ - while (read_spi_status(spi_address) & 1) ; + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spibar = pci_read_config32(dev, 0xA0) & ~0x1F; } -void write_spi_status(volatile u8 * spi_address, u8 status) +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bitsout, void *din, unsigned int bitsin) { - *spi_address = 0x50; /* EWSR */ - *(spi_address + 1) = 0; /* RxByte=TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); - - *spi_address = 0x01; /* WRSR */ - *(spi_address + 1) = 0x01; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = status; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); - - read_spi_status(spi_address); -} + /* First byte is cmd which can not being sent through FIFO. */ + u8 cmd = *(u8 *)dout++; + u8 readoffby1; + u8 readwrite; + u8 bytesout, bytesin; + u8 count; + + bitsout -= 8; + bytesout = bitsout / 8; + bytesin = bitsin / 8; + + readoffby1 = bytesout ? 0 : 1; + + readwrite = (bytesin + readoffby1) << 4 | bytesout; + write8(spibar + 1, readwrite); + write8(spibar + 0, cmd); + + reset_internal_fifo_pointer(); + for (count = 0; count < bytesout; count++, dout++) { + write8(spibar + 0x0C, *(u8 *)dout); + } -void read_spi_id(volatile u8 * spi_address) -{ - u8 mid = 0, did = 0; - *spi_address = 0x90; - *(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */ - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - - mid = *(spi_address + 0xC); - did = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); -} + reset_internal_fifo_pointer(); + execute_command(); -void spi_write_enable(volatile u8 * spi_address) -{ - *spi_address = 0x06; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); -} + reset_internal_fifo_pointer(); + /* Skip the bytes we sent. */ + for (count = 0; count < bytesout; count++) { + cmd = read8(spibar + 0x0C); + } -void spi_write_disable(volatile u8 * spi_address) + reset_internal_fifo_pointer(); + for (count = 0; count < bytesin; count++, din++) { + *(u8 *)din = read8(spibar + 0x0C); + } + + return 0; +} +int spi_claim_bus(struct spi_slave *slave) { - *spi_address = 0x04; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); + return 0; } -void sector_erase_spi(volatile u8 * spi_address, u32 address) +void spi_release_bus(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x20; - *(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */ - - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void chip_erase_spi(volatile u8 * spi_address) +void spi_cs_activate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0xC7; - *(spi_address + 1) = 0x00; - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void byte_program(volatile u8 * spi_address, u32 address, u32 data) +void spi_cs_deactivate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) { - u8 i; - /* - * printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data); - */ - for (i = 0; i < 4; i++) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - data >>= 8; - address++; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); + struct spi_slave *slave = malloc(sizeof(*slave)); + + if (!slave) { + return NULL; } -} -void dword_program(volatile u8 * spi_address, u32 address, u32 data) -{ - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 7; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - *(spi_address + 0xC) = (data >> 8) & 0xFF; - *(spi_address + 0xC) = (data >> 16) & 0xFF; - *(spi_address + 0xC) = (data >> 24) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); -} + memset(slave, 0, sizeof(*slave)); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data) -{ - spi_write_enable(spi_address); - *address = data; - wait4flashpart_ready(spi_address); + return slave; } diff --git a/src/southbridge/amd/agesa/hudson/spi.h b/src/southbridge/amd/agesa/hudson/spi.h deleted file mode 100644 index 657ce4e..0000000 --- a/src/southbridge/amd/agesa/hudson/spi.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#ifndef _HUDSON_CIMX_SPI_H_ -#define _HUDSON_CIMX_SPI_H_ - -void execute_command(volatile u8 * spi_address); -void wait4command_complete(volatile u8 * spi_address); -void reset_internal_fifo_pointer(volatile u8 * spi_address); -u8 read_spi_status(volatile u8 * spi_address); -void wait4flashpart_ready(volatile u8 * spi_address); -void write_spi_status(volatile u8 * spi_address, u8 status); -void read_spi_id(volatile u8 * spi_address); -void spi_write_enable(volatile u8 * spi_address); -void spi_write_disable(volatile u8 * spi_address); -void sector_erase_spi(volatile u8 * spi_address, u32 address); -void chip_erase_spi(volatile u8 * spi_address); -void byte_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_program(volatile u8 * spi_address, u32 address, u32 data); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data); - -#endif diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index e1c2ecb..3b54490 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -16,201 +16,107 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> #include <arch/io.h> +#include <spi.h> #include <device/device.h> -#include "SBPLATFORM.h" +#include <device/pci.h> +#include <device/pci_ops.h> +static u32 spibar; -void execute_command(volatile u8 * spi_address) +static void reset_internal_fifo_pointer(void) { - *(spi_address + 2) |= 1; + do { + write8(spibar + 2, read8(spibar + 2) | 0x10); + } while (read8(spibar + 0xD) & 0x7); } -void wait4command_complete(volatile u8 * spi_address) +static void execute_command(void) { - while (*(spi_address + 2) & 1) - printk(BIOS_DEBUG, "wait4CommandComplete\n"); + write8(spibar + 2, read8(spibar + 2) | 1); + + while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80)); } -void reset_internal_fifo_pointer(volatile u8 * spi_address) +void spi_init() { - u8 val; + device_t dev; - do { - *(spi_address + 2) |= 0x10; - val = *(spi_address + 0xd); - } while (val & 0x7); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spibar = pci_read_config32(dev, 0xA0) & ~0x1F; } -u8 read_spi_status(volatile u8 * spi_address) +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bitsout, void *din, unsigned int bitsin) { - u8 val; - *spi_address = 0x05; - *(spi_address + 1) = 0x11; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0x0; /* dummy */ - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - val = *(spi_address + 0xC); - val = *(spi_address + 0xC); - return val; -} + /* First byte is cmd which can not being sent through FIFO. */ + u8 cmd = *(u8 *)dout++; + u8 readoffby1; + u8 readwrite; + u8 bytesout, bytesin; + u8 count; + + bitsout -= 8; + bytesout = bitsout / 8; + bytesin = bitsin / 8; + + readoffby1 = bytesout ? 0 : 1; + + readwrite = (bytesin + readoffby1) << 4 | bytesout; + write8(spibar + 1, readwrite); + write8(spibar + 0, cmd); + + reset_internal_fifo_pointer(); + for (count = 0; count < bytesout; count++, dout++) { + write8(spibar + 0x0C, *(u8 *)dout); + } -void wait4flashpart_ready(volatile u8 * spi_address) -{ - while (read_spi_status(spi_address) & 1) ; -} + reset_internal_fifo_pointer(); + execute_command(); -void write_spi_status(volatile u8 * spi_address, u8 status) -{ - *spi_address = 0x50; /* EWSR */ - *(spi_address + 1) = 0; /* RxByte=TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); - - *spi_address = 0x01; /* WRSR */ - *(spi_address + 1) = 0x01; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = status; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); - - read_spi_status(spi_address); -} + reset_internal_fifo_pointer(); + /* Skip the bytes we sent. */ + for (count = 0; count < bytesout; count++) { + cmd = read8(spibar + 0x0C); + } -void read_spi_id(volatile u8 * spi_address) -{ - u8 mid = 0, did = 0; - *spi_address = 0x90; - *(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */ - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - - mid = *(spi_address + 0xC); - did = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); -} + reset_internal_fifo_pointer(); + for (count = 0; count < bytesin; count++, din++) { + *(u8 *)din = read8(spibar + 0x0C); + } -void spi_write_enable(volatile u8 * spi_address) -{ - *spi_address = 0x06; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); + return 0; } -void spi_write_disable(volatile u8 * spi_address) +int spi_claim_bus(struct spi_slave *slave) { - *spi_address = 0x04; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); + return 0; } -void sector_erase_spi(volatile u8 * spi_address, u32 address) +void spi_release_bus(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x20; - *(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */ - - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void chip_erase_spi(volatile u8 * spi_address) +void spi_cs_activate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0xC7; - *(spi_address + 1) = 0x00; - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void byte_program(volatile u8 * spi_address, u32 address, u32 data) +void spi_cs_deactivate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) { - u8 i; - /* - * printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data); - */ - for (i = 0; i < 4; i++) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - data >>= 8; - address++; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); + struct spi_slave *slave = malloc(sizeof(*slave)); + + if (!slave) { + return NULL; } -} -void dword_program(volatile u8 * spi_address, u32 address, u32 data) -{ - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 7; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - *(spi_address + 0xC) = (data >> 8) & 0xFF; - *(spi_address + 0xC) = (data >> 16) & 0xFF; - *(spi_address + 0xC) = (data >> 24) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); -} + memset(slave, 0, sizeof(*slave)); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data) -{ - spi_write_enable(spi_address); - *address = data; - wait4flashpart_ready(spi_address); + return slave; } diff --git a/src/southbridge/amd/cimx/sb800/spi.h b/src/southbridge/amd/cimx/sb800/spi.h deleted file mode 100644 index 57921d9..0000000 --- a/src/southbridge/amd/cimx/sb800/spi.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#ifndef _SB800_CIMX_SPI_H_ -#define _SB800_CIMX_SPI_H_ - -void execute_command(volatile u8 * spi_address); -void wait4command_complete(volatile u8 * spi_address); -void reset_internal_fifo_pointer(volatile u8 * spi_address); -u8 read_spi_status(volatile u8 * spi_address); -void wait4flashpart_ready(volatile u8 * spi_address); -void write_spi_status(volatile u8 * spi_address, u8 status); -void read_spi_id(volatile u8 * spi_address); -void spi_write_enable(volatile u8 * spi_address); -void sector_erase_spi(volatile u8 * spi_address, u32 address); -void chip_erase_spi(volatile u8 * spi_address); -void byte_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_program(volatile u8 * spi_address, u32 address, u32 data); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data); - -#endif

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Patch set updated for coreboot: 18ed795 Add include files for samesung s5p-common
by Stefan Reinauer 27 Nov '12

27 Nov '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1930 -gerrit commit 18ed795a016d6a5b8e35e99f7019f2feb704c9fc Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Nov 27 13:20:43 2012 -0800 Add include files for samesung s5p-common These are from u-boot but have been cleaned up somewhat to remove references to linux include files. Change-Id: I5fe3954a11d8c4aa792620ef5e1a5ee8932b8578 Signed-off-by: Hung-Ti Lin <hungte(a)chromium.org> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/s5p-common/clk.h | 38 ++++++++ src/cpu/samsung/s5p-common/clock.h | 94 ++++++++++++++++++ src/cpu/samsung/s5p-common/cpu.h | 116 ++++++++++++++++++++++ src/cpu/samsung/s5p-common/gpio.h | 173 +++++++++++++++++++++++++++++++++ src/cpu/samsung/s5p-common/mmc.h | 73 ++++++++++++++ src/cpu/samsung/s5p-common/power.h | 42 ++++++++ src/cpu/samsung/s5p-common/pwm.h | 75 ++++++++++++++ src/cpu/samsung/s5p-common/sromc.h | 53 ++++++++++ src/cpu/samsung/s5p-common/sys_proto.h | 29 ++++++ src/cpu/samsung/s5p-common/uart.h | 58 +++++++++++ src/cpu/samsung/s5p-common/watchdog.h | 58 +++++++++++ 11 files changed, 809 insertions(+) diff --git a/src/cpu/samsung/s5p-common/clk.h b/src/cpu/samsung/s5p-common/clk.h new file mode 100644 index 0000000..69c7e4e --- /dev/null +++ b/src/cpu/samsung/s5p-common/clk.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __S5P_COMMON_CLK_H_ +#define __S5P_COMMON_CLK_H_ + +#define APLL 0 +#define MPLL 1 +#define EPLL 2 +#define HPLL 3 +#define VPLL 4 + +unsigned long get_pll_clk(int pllreg); +unsigned long get_arm_clk(void); +unsigned long get_pwm_clk(void); +unsigned long get_uart_clk(int dev_index); +void set_mmc_clk(int dev_index, unsigned int div); + +#endif diff --git a/src/cpu/samsung/s5p-common/clock.h b/src/cpu/samsung/s5p-common/clock.h new file mode 100644 index 0000000..7b4eb89 --- /dev/null +++ b/src/cpu/samsung/s5p-common/clock.h @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_CLOCK_H_ +#define __ASM_ARM_ARCH_CLOCK_H_ + +#ifndef __ASSEMBLY__ +struct s5pc100_clock { + unsigned int apll_lock; + unsigned int mpll_lock; + unsigned int epll_lock; + unsigned int hpll_lock; + unsigned char res1[0xf0]; + unsigned int apll_con; + unsigned int mpll_con; + unsigned int epll_con; + unsigned int hpll_con; + unsigned char res2[0xf0]; + unsigned int src0; + unsigned int src1; + unsigned int src2; + unsigned int src3; + unsigned char res3[0xf0]; + unsigned int div0; + unsigned int div1; + unsigned int div2; + unsigned int div3; + unsigned int div4; + unsigned char res4[0x1ec]; + unsigned int gate_d00; + unsigned int gate_d01; + unsigned int gate_d02; + unsigned char res5[0x54]; + unsigned int gate_sclk0; + unsigned int gate_sclk1; +}; + +struct s5pc110_clock { + unsigned int apll_lock; + unsigned char res1[0x4]; + unsigned int mpll_lock; + unsigned char res2[0x4]; + unsigned int epll_lock; + unsigned char res3[0xc]; + unsigned int vpll_lock; + unsigned char res4[0xdc]; + unsigned int apll_con; + unsigned char res5[0x4]; + unsigned int mpll_con; + unsigned char res6[0x4]; + unsigned int epll_con; + unsigned char res7[0xc]; + unsigned int vpll_con; + unsigned char res8[0xdc]; + unsigned int src0; + unsigned int src1; + unsigned int src2; + unsigned int src3; + unsigned char res9[0xf0]; + unsigned int div0; + unsigned int div1; + unsigned int div2; + unsigned int div3; + unsigned int div4; + unsigned char res10[0x1ec]; + unsigned int gate_d00; + unsigned int gate_d01; + unsigned int gate_d02; + unsigned char res11[0x54]; + unsigned int gate_sclk0; + unsigned int gate_sclk1; +}; +#endif + +#endif diff --git a/src/cpu/samsung/s5p-common/cpu.h b/src/cpu/samsung/s5p-common/cpu.h new file mode 100644 index 0000000..34be1f2 --- /dev/null +++ b/src/cpu/samsung/s5p-common/cpu.h @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _S5PC1XX_CPU_H +#define _S5PC1XX_CPU_H + +#define S5PC1XX_ADDR_BASE 0xE0000000 + +/* S5PC100 */ +#define S5PC100_PRO_ID 0xE0000000 +#define S5PC100_CLOCK_BASE 0xE0100000 +#define S5PC100_GPIO_BASE 0xE0300000 +#define S5PC100_VIC0_BASE 0xE4000000 +#define S5PC100_VIC1_BASE 0xE4100000 +#define S5PC100_VIC2_BASE 0xE4200000 +#define S5PC100_DMC_BASE 0xE6000000 +#define S5PC100_SROMC_BASE 0xE7000000 +#define S5PC100_ONENAND_BASE 0xE7100000 +#define S5PC100_PWMTIMER_BASE 0xEA000000 +#define S5PC100_WATCHDOG_BASE 0xEA200000 +#define S5PC100_UART_BASE 0xEC000000 +#define S5PC100_MMC_BASE 0xED800000 + +/* S5PC110 */ +#define S5PC110_PRO_ID 0xE0000000 +#define S5PC110_CLOCK_BASE 0xE0100000 +#define S5PC110_GPIO_BASE 0xE0200000 +#define S5PC110_PWMTIMER_BASE 0xE2500000 +#define S5PC110_WATCHDOG_BASE 0xE2700000 +#define S5PC110_UART_BASE 0xE2900000 +#define S5PC110_SROMC_BASE 0xE8000000 +#define S5PC110_MMC_BASE 0xEB000000 +#define S5PC110_DMC0_BASE 0xF0000000 +#define S5PC110_DMC1_BASE 0xF1400000 +#define S5PC110_VIC0_BASE 0xF2000000 +#define S5PC110_VIC1_BASE 0xF2100000 +#define S5PC110_VIC2_BASE 0xF2200000 +#define S5PC110_VIC3_BASE 0xF2300000 +#define S5PC110_OTG_BASE 0xEC000000 +#define S5PC110_PHY_BASE 0xEC100000 +#define S5PC110_USB_PHY_CONTROL 0xE010E80C + + +#include <arch/io.h> +/* CPU detection macros */ +extern unsigned int s5p_cpu_id; + +/* FIXME(dhendrix): conflicts with the one in cpu_info.c ... */ +#if 0 +inline void s5p_set_cpu_id(void) +{ + s5p_cpu_id = readl(S5PC100_PRO_ID); + s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12); +} +#endif +inline void s5p_set_cpu_id(void); + +#define IS_SAMSUNG_TYPE(type, id) \ +static inline int cpu_is_##type(void) \ +{ \ + return s5p_cpu_id == id ? 1 : 0; \ +} + +IS_SAMSUNG_TYPE(s5pc100, 0xc100) +IS_SAMSUNG_TYPE(s5pc110, 0xc110) + +/* + * FIXME(dhendrix): collides with SAMSUNG_BASE in exynos header files. We + * don't really care about old S5P processors right now. + */ +#if 0 +#define SAMSUNG_BASE(device, base) \ +static inline unsigned int samsung_get_base_##device(void) \ +{ \ + if (cpu_is_s5pc100()) \ + return S5PC100_##base; \ + else if (cpu_is_s5pc110()) \ + return S5PC110_##base; \ + else \ + return 0; \ +} + +SAMSUNG_BASE(clock, CLOCK_BASE) +SAMSUNG_BASE(gpio, GPIO_BASE) +SAMSUNG_BASE(pro_id, PRO_ID) +SAMSUNG_BASE(mmc, MMC_BASE) +SAMSUNG_BASE(sromc, SROMC_BASE) +SAMSUNG_BASE(timer, PWMTIMER_BASE) +SAMSUNG_BASE(uart, UART_BASE) +SAMSUNG_BASE(watchdog, WATCHDOG_BASE) +#endif + +int s5p_get_cpu_rev(void); +//void s5p_set_cpu_id(void); +int s5p_get_cpu_id(void); + +#endif /* _S5PC1XX_CPU_H */ diff --git a/src/cpu/samsung/s5p-common/gpio.h b/src/cpu/samsung/s5p-common/gpio.h new file mode 100644 index 0000000..2522808 --- /dev/null +++ b/src/cpu/samsung/s5p-common/gpio.h @@ -0,0 +1,173 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef S5P_GPIO_H_ +#define S5P_GPIO_H_ + +#include <cpu/samsung/s5p-common/cpu.h> /* FIXME: for S5PC110_GPIO_BASE */ + +#ifndef __ASSEMBLY__ +struct s5p_gpio_bank { + unsigned int con; + unsigned int dat; + unsigned int pull; + unsigned int drv; + unsigned int pdn_con; + unsigned int pdn_pull; + unsigned char res1[8]; +}; + +struct s5pc100_gpio { + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank b; + struct s5p_gpio_bank c; + struct s5p_gpio_bank d; + struct s5p_gpio_bank e0; + struct s5p_gpio_bank e1; + struct s5p_gpio_bank f0; + struct s5p_gpio_bank f1; + struct s5p_gpio_bank f2; + struct s5p_gpio_bank f3; + struct s5p_gpio_bank g0; + struct s5p_gpio_bank g1; + struct s5p_gpio_bank g2; + struct s5p_gpio_bank g3; + struct s5p_gpio_bank i; + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; + struct s5p_gpio_bank j2; + struct s5p_gpio_bank j3; + struct s5p_gpio_bank j4; + struct s5p_gpio_bank k0; + struct s5p_gpio_bank k1; + struct s5p_gpio_bank k2; + struct s5p_gpio_bank k3; + struct s5p_gpio_bank l0; + struct s5p_gpio_bank l1; + struct s5p_gpio_bank l2; + struct s5p_gpio_bank l3; + struct s5p_gpio_bank l4; + struct s5p_gpio_bank h0; + struct s5p_gpio_bank h1; + struct s5p_gpio_bank h2; + struct s5p_gpio_bank h3; +}; + +struct s5pc110_gpio { + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank b; + struct s5p_gpio_bank c0; + struct s5p_gpio_bank c1; + struct s5p_gpio_bank d0; + struct s5p_gpio_bank d1; + struct s5p_gpio_bank e0; + struct s5p_gpio_bank e1; + struct s5p_gpio_bank f0; + struct s5p_gpio_bank f1; + struct s5p_gpio_bank f2; + struct s5p_gpio_bank f3; + struct s5p_gpio_bank g0; + struct s5p_gpio_bank g1; + struct s5p_gpio_bank g2; + struct s5p_gpio_bank g3; + struct s5p_gpio_bank i; + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; + struct s5p_gpio_bank j2; + struct s5p_gpio_bank j3; + struct s5p_gpio_bank j4; + struct s5p_gpio_bank mp0_1; + struct s5p_gpio_bank mp0_2; + struct s5p_gpio_bank mp0_3; + struct s5p_gpio_bank mp0_4; + struct s5p_gpio_bank mp0_5; + struct s5p_gpio_bank mp0_6; + struct s5p_gpio_bank mp0_7; + struct s5p_gpio_bank mp1_0; + struct s5p_gpio_bank mp1_1; + struct s5p_gpio_bank mp1_2; + struct s5p_gpio_bank mp1_3; + struct s5p_gpio_bank mp1_4; + struct s5p_gpio_bank mp1_5; + struct s5p_gpio_bank mp1_6; + struct s5p_gpio_bank mp1_7; + struct s5p_gpio_bank mp1_8; + struct s5p_gpio_bank mp2_0; + struct s5p_gpio_bank mp2_1; + struct s5p_gpio_bank mp2_2; + struct s5p_gpio_bank mp2_3; + struct s5p_gpio_bank mp2_4; + struct s5p_gpio_bank mp2_5; + struct s5p_gpio_bank mp2_6; + struct s5p_gpio_bank mp2_7; + struct s5p_gpio_bank mp2_8; + struct s5p_gpio_bank res1[48]; + struct s5p_gpio_bank h0; + struct s5p_gpio_bank h1; + struct s5p_gpio_bank h2; + struct s5p_gpio_bank h3; +}; + +/* functions */ +void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); +void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); +void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); +void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); +unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio); +void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); +void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); +void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); + +/* GPIO pins per bank */ +#define GPIO_PER_BANK 8 + +static inline unsigned int s5p_gpio_base(int nr) +{ + return S5PC110_GPIO_BASE; +} + +#define s5pc110_gpio_get_nr(bank, pin) \ + ((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\ + - S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) +#endif + +/* Pin configurations */ +#define GPIO_INPUT 0x0 +#define GPIO_OUTPUT 0x1 +#define GPIO_IRQ 0xf +#define GPIO_FUNC(x) (x) + +/* Pull mode */ +#define GPIO_PULL_NONE 0x0 +#define GPIO_PULL_DOWN 0x1 +#define GPIO_PULL_UP 0x2 + +/* Drive Strength level */ +#define GPIO_DRV_1X 0x0 +#define GPIO_DRV_3X 0x1 +#define GPIO_DRV_2X 0x2 +#define GPIO_DRV_4X 0x3 +#define GPIO_DRV_FAST 0x0 +#define GPIO_DRV_SLOW 0x1 + +#endif /* S5P_GPIO_H_ */ diff --git a/src/cpu/samsung/s5p-common/mmc.h b/src/cpu/samsung/s5p-common/mmc.h new file mode 100644 index 0000000..adef4ee --- /dev/null +++ b/src/cpu/samsung/s5p-common/mmc.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_MMC_H_ +#define __ASM_ARCH_MMC_H_ + +#ifndef __ASSEMBLY__ +struct s5p_mmc { + unsigned int sysad; + unsigned short blksize; + unsigned short blkcnt; + unsigned int argument; + unsigned short trnmod; + unsigned short cmdreg; + unsigned int rspreg0; + unsigned int rspreg1; + unsigned int rspreg2; + unsigned int rspreg3; + unsigned int bdata; + unsigned int prnsts; + unsigned char hostctl; + unsigned char pwrcon; + unsigned char blkgap; + unsigned char wakcon; + unsigned short clkcon; + unsigned char timeoutcon; + unsigned char swrst; + unsigned int norintsts; /* errintsts */ + unsigned int norintstsen; /* errintstsen */ + unsigned int norintsigen; /* errintsigen */ + unsigned short acmd12errsts; + unsigned char res1[2]; + unsigned int capareg; + unsigned char res2[4]; + unsigned int maxcurr; + unsigned char res3[0x34]; + unsigned int control2; + unsigned int control3; + unsigned char res4[4]; + unsigned int control4; + unsigned char res5[0x6e]; + unsigned short hcver; + unsigned char res6[0xFFF00]; +}; + +struct mmc_host { + struct s5p_mmc *reg; + unsigned int version; /* SDHCI spec. version */ + unsigned int clock; /* Current clock (MHz) */ + int dev_index; +}; + +int s5p_mmc_init(int dev_index, int bus_width); + +#endif /* __ASSEMBLY__ */ +#endif diff --git a/src/cpu/samsung/s5p-common/power.h b/src/cpu/samsung/s5p-common/power.h new file mode 100644 index 0000000..57e2a2b --- /dev/null +++ b/src/cpu/samsung/s5p-common/power.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2009 Samsung Electronics + * Kyungmin Park <kyungmin.park(a)samsung.com> + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_POWER_H_ +#define __ASM_ARM_ARCH_POWER_H_ + +/* + * Power control + */ +#define S5PC100_OTHERS 0xE0108200 +#define S5PC100_RST_STAT 0xE0108300 +#define S5PC100_SLEEP_WAKEUP (1 << 3) +#define S5PC100_WAKEUP_STAT 0xE0108304 +#define S5PC100_INFORM0 0xE0108400 + +#define S5PC110_RST_STAT 0xE010A000 +#define S5PC110_SLEEP_WAKEUP (1 << 3) +#define S5PC110_WAKEUP_STAT 0xE010C200 +#define S5PC110_OTHERS 0xE010E000 +#define S5PC110_USB_PHY_CON 0xE010E80C +#define S5PC110_INFORM0 0xE010F000 + +#endif diff --git a/src/cpu/samsung/s5p-common/pwm.h b/src/cpu/samsung/s5p-common/pwm.h new file mode 100644 index 0000000..1ac348b --- /dev/null +++ b/src/cpu/samsung/s5p-common/pwm.h @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Kyungmin Park <kyungmin.park(a)samsung.com> + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __S5P_COMMON_PWM_H_ +#define __S5P_COMMON_PWM_H_ + +#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */ +#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */ + +/* Divider MUX */ +#define MUX_DIV_1 0 /* 1/1 period */ +#define MUX_DIV_2 1 /* 1/2 period */ +#define MUX_DIV_4 2 /* 1/4 period */ +#define MUX_DIV_8 3 /* 1/8 period */ +#define MUX_DIV_16 4 /* 1/16 period */ + +#define MUX_DIV_SHIFT(x) (x * 4) + +#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2) + +#define TCON_START(x) (1 << TCON_OFFSET(x)) +#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1)) +#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2)) +#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3)) +#define TCON4_AUTO_RELOAD (1 << 22) + +#ifndef __ASSEMBLY__ +struct s5p_timer { + unsigned int tcfg0; + unsigned int tcfg1; + unsigned int tcon; + unsigned int tcntb0; + unsigned int tcmpb0; + unsigned int tcnto0; + unsigned int tcntb1; + unsigned int tcmpb1; + unsigned int tcnto1; + unsigned int tcntb2; + unsigned int tcmpb2; + unsigned int tcnto2; + unsigned int tcntb3; + unsigned int res1; + unsigned int tcnto3; + unsigned int tcntb4; + unsigned int tcnto4; + unsigned int tintcstat; +}; +#endif /* __ASSEMBLY__ */ + +/* FIXME(dhendrix): added missing prototypes... */ +int pwm_config(int pwm_id, int duty_ns, int period_ns); +int pwm_check_enabled(int pwm_id); +void pwm_disable(int pwm_id); +int pwm_enable(int pwm_id); +int pwm_init(int pwm_id, int div, int invert); + +#endif /* __S5P_COMMON_PWM_H_ */ diff --git a/src/cpu/samsung/s5p-common/sromc.h b/src/cpu/samsung/s5p-common/sromc.h new file mode 100644 index 0000000..3800a8d --- /dev/null +++ b/src/cpu/samsung/s5p-common/sromc.h @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Naveen Krishna Ch <ch.naveen(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: This file contains the register description for Memory subsystem + * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX. + * + * Only SROMC is defined as of now + */ + +#ifndef __ASM_ARCH_SROMC_H_ +#define __ASM_ARCH_SROMC_H_ + +#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) +#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ + /* 1-> Byte base address*/ +#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2)) +#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3)) + +#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */ +#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */ +#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */ +#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */ +#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */ +#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */ +#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ + +#ifndef __ASSEMBLY__ +struct s5p_sromc { + unsigned int bw; + unsigned int bc[6]; +}; +#endif /* __ASSEMBLY__ */ + +/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ +void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); + +#endif /* __ASM_ARCH_SMC_H_ */ diff --git a/src/cpu/samsung/s5p-common/sys_proto.h b/src/cpu/samsung/s5p-common/sys_proto.h new file mode 100644 index 0000000..7b83c5a --- /dev/null +++ b/src/cpu/samsung/s5p-common/sys_proto.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2009 Samsung Electrnoics + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +u32 get_device_type(void); + +#endif diff --git a/src/cpu/samsung/s5p-common/uart.h b/src/cpu/samsung/s5p-common/uart.h new file mode 100644 index 0000000..1c56739 --- /dev/null +++ b/src/cpu/samsung/s5p-common/uart.h @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_UART_H_ +#define __ASM_ARCH_UART_H_ + +#ifndef __ASSEMBLY__ +/* baudrate rest value */ +union br_rest { + unsigned short slot; /* udivslot */ + unsigned char value; /* ufracval */ +}; + +struct s5p_uart { + unsigned int ulcon; + unsigned int ucon; + unsigned int ufcon; + unsigned int umcon; + unsigned int utrstat; + unsigned int uerstat; + unsigned int ufstat; + unsigned int umstat; + unsigned char utxh; + unsigned char res1[3]; + unsigned char urxh; + unsigned char res2[3]; + unsigned int ubrdiv; + union br_rest rest; + unsigned char res3[0x3d0]; +}; + +static inline int s5p_uart_divslot(void) +{ + return 1; +} + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/src/cpu/samsung/s5p-common/watchdog.h b/src/cpu/samsung/s5p-common/watchdog.h new file mode 100644 index 0000000..0f80ca5 --- /dev/null +++ b/src/cpu/samsung/s5p-common/watchdog.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * Heungjun Kim <riverful.kim(a)samsung.com> + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_WATCHDOG_H_ +#define __ASM_ARM_ARCH_WATCHDOG_H_ + +#define WTCON_RESET_OFFSET 0 +#define WTCON_INTEN_OFFSET 2 +#define WTCON_CLKSEL_OFFSET 3 +#define WTCON_EN_OFFSET 5 +#define WTCON_PRE_OFFSET 8 + +#define WTCON_CLK_16 0x0 +#define WTCON_CLK_32 0x1 +#define WTCON_CLK_64 0x2 +#define WTCON_CLK_128 0x3 + +#define WTCON_CLK(x) ((x & 0x3) << WTCON_CLKSEL_OFFSET) +#define WTCON_PRESCALER(x) ((x) << WTCON_PRE_OFFSET) +#define WTCON_EN (0x1 << WTCON_EN_OFFSET) +#define WTCON_RESET (0x1 << WTCON_RESET_OFFSET) +#define WTCON_INT (0x1 << WTCON_INTEN_OFFSET) + +#ifndef __ASSEMBLY__ +struct s5p_watchdog { + unsigned int wtcon; + unsigned int wtdat; + unsigned int wtcnt; + unsigned int wtclrint; +}; + +/* functions */ +void wdt_stop(void); +void wdt_start(unsigned int timeout); +#endif /* __ASSEMBLY__ */ + +#endif

1 0

Patch set updated for coreboot: c59d159 Remove assembly coded log2 function
by Stefan Reinauer 27 Nov '12

27 Nov '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1928 -gerrit commit c59d159507ac4980523feeca571e32e1a6365832 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Nov 27 11:32:38 2012 -0800 Remove assembly coded log2 function As we move to supporting other systems we need to get rid of assembly where we can. The log2 function in src/lib is identical to the assembly one (tested for all 32-bit signed integers :-) and takes about 10 ns to run as opposed to 5ns for the non-portable assembly version. While speed is good, I think we can spare the 15 ns or so we add to boot time by using the C version only. Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/x86/include/bitops.h | 20 -------------------- src/cpu/amd/geode_gx2/cpubug.c | 1 - src/cpu/amd/geode_lx/cpubug.c | 1 - src/cpu/amd/sc520/sc520.c | 1 - src/devices/device.c | 1 - src/devices/hypertransport.c | 2 +- src/devices/pci_device.c | 1 - src/devices/pnp_device.c | 1 - src/mainboard/emulation/qemu-x86/northbridge.c | 1 - src/northbridge/amd/agesa/family10/northbridge.c | 2 +- src/northbridge/amd/agesa/family12/northbridge.c | 2 +- src/northbridge/amd/agesa/family14/northbridge.c | 2 +- src/northbridge/amd/agesa/family15/northbridge.c | 2 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- src/northbridge/amd/amdfam10/misc_control.c | 2 +- src/northbridge/amd/amdfam10/northbridge.c | 2 +- src/northbridge/amd/amdk8/misc_control.c | 2 +- src/northbridge/amd/amdk8/northbridge.c | 2 +- src/northbridge/amd/gx1/northbridge.c | 1 - src/northbridge/amd/gx2/northbridge.c | 1 - src/northbridge/amd/gx2/northbridgeinit.c | 1 - src/northbridge/amd/lx/northbridge.c | 1 - src/northbridge/amd/lx/northbridgeinit.c | 1 - src/northbridge/intel/e7501/northbridge.c | 1 - src/northbridge/intel/e7505/northbridge.c | 1 - src/northbridge/intel/e7520/northbridge.c | 1 - src/northbridge/intel/e7525/northbridge.c | 1 - src/northbridge/intel/gm45/northbridge.c | 1 - src/northbridge/intel/i3100/northbridge.c | 1 - src/northbridge/intel/i440bx/northbridge.c | 1 - src/northbridge/intel/i440lx/northbridge.c | 1 - src/northbridge/intel/i5000/northbridge.c | 1 - src/northbridge/intel/i82810/northbridge.c | 1 - src/northbridge/intel/i82830/northbridge.c | 1 - src/northbridge/intel/i855/northbridge.c | 1 - src/northbridge/intel/i945/northbridge.c | 1 - src/northbridge/intel/sandybridge/northbridge.c | 1 - src/northbridge/intel/sch/northbridge.c | 1 - src/northbridge/rdc/r8610/northbridge.c | 1 - src/northbridge/via/cn400/northbridge.c | 2 +- src/northbridge/via/cn400/vga.c | 1 - src/northbridge/via/cn700/northbridge.c | 2 +- src/northbridge/via/cn700/vga.c | 1 - src/northbridge/via/cx700/northbridge.c | 1 - src/northbridge/via/cx700/vga.c | 1 - src/northbridge/via/vt8601/northbridge.c | 1 - src/northbridge/via/vt8623/northbridge.c | 1 - src/northbridge/via/vt8623/vga.c | 1 - src/northbridge/via/vx800/northbridge.c | 1 - src/northbridge/via/vx800/vga.c | 1 - src/southbridge/amd/agesa/hudson/lpc.c | 1 - src/southbridge/amd/agesa/hudson/sm.c | 1 - src/southbridge/amd/amd8111/acpi.c | 2 +- src/southbridge/amd/cimx/sb700/lpc.c | 1 - src/southbridge/amd/cimx/sb800/lpc.c | 1 - src/southbridge/amd/cs5535/chipsetinit.c | 1 - src/southbridge/amd/sb600/lpc.c | 1 - src/southbridge/amd/sb600/sm.c | 1 - src/southbridge/amd/sb700/lpc.c | 1 - src/southbridge/amd/sb700/sm.c | 1 - src/southbridge/amd/sb800/lpc.c | 1 - src/southbridge/amd/sb800/sm.c | 1 - src/southbridge/broadcom/bcm5785/lpc.c | 1 - src/southbridge/broadcom/bcm5785/sb_pci_main.c | 1 - src/southbridge/nvidia/ck804/lpc.c | 1 - src/southbridge/nvidia/ck804/smbus.c | 1 - src/southbridge/nvidia/mcp55/lpc.c | 1 - src/southbridge/nvidia/mcp55/smbus.c | 1 - src/southbridge/sis/sis966/lpc.c | 1 - src/southbridge/sis/sis966/sis761.c | 1 - src/southbridge/via/k8t890/dram.c | 2 +- src/superio/nsc/pc8374/superio.c | 1 - src/superio/nsc/pc87351/superio.c | 1 - src/superio/nsc/pc87360/superio.c | 1 - src/superio/nsc/pc87366/superio.c | 1 - src/superio/nsc/pc87382/superio.c | 1 - src/superio/nsc/pc87384/superio.c | 1 - src/superio/nsc/pc87392/superio.c | 1 - src/superio/nsc/pc87417/superio.c | 1 - src/superio/nsc/pc87427/superio.c | 1 - src/superio/nuvoton/wpcm450/superio.c | 1 - src/superio/renesas/m3885x/superio.c | 1 - src/superio/smsc/kbc1100/superio.c | 1 - src/superio/smsc/lpc47b272/superio.c | 1 - src/superio/smsc/lpc47b397/superio.c | 1 - src/superio/smsc/lpc47m10x/superio.c | 1 - src/superio/smsc/lpc47m15x/superio.c | 1 - src/superio/smsc/lpc47n217/superio.c | 1 - src/superio/smsc/lpc47n227/superio.c | 1 - src/superio/smsc/mec1308/superio.c | 1 - src/superio/smsc/sch4037/superio.c | 1 - src/superio/smsc/sio1036/superio.c | 1 - src/superio/winbond/w83627ehg/superio.c | 1 - src/superio/winbond/w83627hf/superio.c | 1 - src/superio/winbond/w83627thg/superio.c | 1 - src/superio/winbond/w83627uhg/superio.c | 1 - src/superio/winbond/w83697hf/superio.c | 2 +- src/superio/winbond/w83977f/superio.c | 1 - src/superio/winbond/w83977tf/superio.c | 1 - 99 files changed, 15 insertions(+), 118 deletions(-) diff --git a/src/arch/x86/include/bitops.h b/src/arch/x86/include/bitops.h deleted file mode 100644 index 9206465..0000000 --- a/src/arch/x86/include/bitops.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef I386_BITOPS_H -#define I386_BITOPS_H - -/** - * log2 - Find the truncated log base 2 of x - */ - -static inline unsigned long log2(unsigned long x) -{ - unsigned long r = 0; - __asm__( - "bsrl %1, %0\n\t" - "jnz 1f\n\t" - "movl $-1, %0\n\t" - "1:\n\t" - : "=r" (r) : "r" (x)); - return r; - -} -#endif /* I386_BITOPS_H */ diff --git a/src/cpu/amd/geode_gx2/cpubug.c b/src/cpu/amd/geode_gx2/cpubug.c index 473766c..54d7e0e 100644 --- a/src/cpu/amd/geode_gx2/cpubug.c +++ b/src/cpu/amd/geode_gx2/cpubug.c @@ -6,7 +6,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/amd/gx2def.h> #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> diff --git a/src/cpu/amd/geode_lx/cpubug.c b/src/cpu/amd/geode_lx/cpubug.c index e3b6e51..5b1a7ac 100644 --- a/src/cpu/amd/geode_lx/cpubug.c +++ b/src/cpu/amd/geode_lx/cpubug.c @@ -26,7 +26,6 @@ #include <device/device.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c index 382eb87..6954f44 100644 --- a/src/cpu/amd/sc520/sc520.c +++ b/src/cpu/amd/sc520/sc520.c @@ -12,7 +12,6 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <delay.h> /* diff --git a/src/devices/device.c b/src/devices/device.c index 03e7ea7..07bbc7a 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -33,7 +33,6 @@ */ #include <console/console.h> -#include <bitops.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/devices/hypertransport.c b/src/devices/hypertransport.c index 420054e..a6320fe 100644 --- a/src/devices/hypertransport.c +++ b/src/devices/hypertransport.c @@ -23,7 +23,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <bitops.h> +#include <lib.h> #include <console/console.h> #include <device/device.h> #include <device/path.h> diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index e2a4940..d9e6b27 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -26,7 +26,6 @@ #include <console/console.h> #include <stdlib.h> #include <stdint.h> -#include <bitops.h> #include <string.h> #include <arch/io.h> #include <device/device.h> diff --git a/src/devices/pnp_device.c b/src/devices/pnp_device.c index fb6c9d6..19b492d 100644 --- a/src/devices/pnp_device.c +++ b/src/devices/pnp_device.c @@ -24,7 +24,6 @@ #include <console/console.h> #include <stdlib.h> #include <stdint.h> -#include <bitops.h> #include <string.h> #include <arch/io.h> #include <device/device.h> diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c index 6103229..16dcc3b 100644 --- a/src/mainboard/emulation/qemu-x86/northbridge.c +++ b/src/mainboard/emulation/qemu-x86/northbridge.c @@ -7,7 +7,6 @@ #include <device/pci.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <delay.h> #include <smbios.h> diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index f1ed610..4bdc7b4 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -26,7 +26,7 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> +#include <lib.h> #include <cpu/cpu.h> #include <cpu/x86/lapic.h> #include <cbmem.h> diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index ac3f308..c4b43c5 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -26,7 +26,7 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> +#include <lib.h> #include <cpu/cpu.h> #include <cbmem.h> diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 74473c0..5e8d89b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -26,7 +26,7 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> +#include <lib.h> #include <cpu/cpu.h> #include <cbmem.h> diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 78986e4..abd53b2 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -26,7 +26,7 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> +#include <lib.h> #include <cpu/cpu.h> #include <cbmem.h> diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index ac605b0..5659ac6 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -26,7 +26,7 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> +#include <lib.h> #include <cpu/cpu.h> #include <cbmem.h> diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 472382c..3975005 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -31,7 +31,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> -#include <bitops.h> +#include <lib.h> #include <cpu/amd/model_10xxx_rev.h> #include "amdfam10.h" diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 7f05b46..6bac585 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -26,7 +26,7 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> +#include <lib.h> #include <cpu/cpu.h> #include <cpu/x86/lapic.h> diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index cc69883..030c992 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -16,7 +16,7 @@ #include <device/pci_ops.h> #include <reset.h> #include <pc80/mc146818rtc.h> -#include <bitops.h> +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> #include "amdk8.h" diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 4d14efa..2f3d778 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -14,7 +14,7 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> +#include <lib.h> #include <cpu/cpu.h> #include <cpu/x86/lapic.h> diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index fbea3b5..83b84e3 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -6,7 +6,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include "northbridge.h" #include <cpu/amd/gx1def.h> #include <cpu/x86/cache.h> diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index 12096d8..80bcdf6 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include "northbridge.h" #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index f51bcc6..09f8b00 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include "northbridge.h" #include <cpu/amd/gx2def.h> #include <cpu/x86/msr.h> diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 5f98b40..aaaf46b 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include <cpu/amd/lxdef.h> #include <cpu/x86/msr.h> diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 6288608..f883900 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include "northbridge.h" #include <cpu/amd/lxdef.h> #include <cpu/x86/msr.h> diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index c70f032..e7d7d5d 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -6,7 +6,6 @@ #include <cpu/cpu.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index b6d24fa..db0ece2 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -6,7 +6,6 @@ #include <cpu/cpu.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include "e7505.h" #if CONFIG_WRITE_HIGH_TABLES diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index 3b92aa8..962e8cd 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -7,7 +7,6 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include "chip.h" #include "northbridge.h" diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index ab88899..ceb7afa 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -7,7 +7,6 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include "chip.h" #include "northbridge.h" diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 8c80f86..1839ec6 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -26,7 +26,6 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include <boot/tables.h> #include <arch/acpi.h> diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index db35b85..d90d0b5 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -29,7 +29,6 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include "chip.h" #include "i3100.h" diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 39bd6b9..ccd5e9c 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -6,7 +6,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include <pc80/keyboard.h> #include "northbridge.h" diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index 57fcfcb..c75a4bb 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -27,7 +27,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include <pc80/keyboard.h> #include "northbridge.h" diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index 1548f19..071616c 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -25,7 +25,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include <arch/acpi.h> #include <cbmem.h> diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 4c09d44..ed9876f 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -27,7 +27,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include "northbridge.h" #include "i82810.h" diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 95ac2ed..f2505bd 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -27,7 +27,6 @@ #include <cpu/cpu.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include "i82830.h" static void northbridge_init(device_t dev) diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index 74e2c76..b1e150f 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -28,7 +28,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/x86/cache.h> #include <cpu/cpu.h> diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 684bb71..c6c93e5 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -26,7 +26,6 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include <arch/acpi.h> #include "i945.h" diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 4b5a03a..8652838 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -31,7 +31,6 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include <cbmem.h> #include "chip.h" diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 4c41d68..fe5881c 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -26,7 +26,6 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include <arch/acpi.h> #include "sch.h" diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c index 65fd5eb..ebcccff 100644 --- a/src/northbridge/rdc/r8610/northbridge.c +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -28,7 +28,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <smbios.h> #if CONFIG_WRITE_HIGH_TABLES diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index 61d7345..ab9f084 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -28,7 +28,7 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> +#include <lib.h> #include <cpu/cpu.h> #include "northbridge.h" #include "cn400.h" diff --git a/src/northbridge/via/cn400/vga.c b/src/northbridge/via/cn400/vga.c index d8c921a..d87cfcb 100644 --- a/src/northbridge/via/cn400/vga.c +++ b/src/northbridge/via/cn400/vga.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include <arch/interrupt.h> #include "northbridge.h" diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index 837ec85..86c11a8 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -28,7 +28,7 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> +#include <lib.h> #include <cpu/cpu.h> #include "northbridge.h" #include "cn700.h" diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c index 0f96b2c..0ad181d 100644 --- a/src/northbridge/via/cn700/vga.c +++ b/src/northbridge/via/cn700/vga.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include <arch/interrupt.h> #include "northbridge.h" diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index 3d7137e..ce5edf8 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> diff --git a/src/northbridge/via/cx700/vga.c b/src/northbridge/via/cx700/vga.c index 6b60354..ce294fa 100644 --- a/src/northbridge/via/cx700/vga.c +++ b/src/northbridge/via/cx700/vga.c @@ -25,7 +25,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index f5f084c..950d683 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -8,7 +8,6 @@ #include <cpu/cpu.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include "northbridge.h" /* diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 42864e0..e061155 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -7,7 +7,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> diff --git a/src/northbridge/via/vt8623/vga.c b/src/northbridge/via/vt8623/vga.c index 954ff47..9bbb54b 100644 --- a/src/northbridge/via/vt8623/vga.c +++ b/src/northbridge/via/vt8623/vga.c @@ -25,7 +25,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index 5fcff76..4e0a36d 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -29,7 +29,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include "vx800.h" diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c index 319dbda..ee9924d 100644 --- a/src/northbridge/via/vx800/vga.c +++ b/src/northbridge/via/vx800/vga.c @@ -28,7 +28,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 97f27d0..b56fa38 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -25,7 +25,6 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> -#include <bitops.h> #include <arch/io.h> #include "hudson.h" diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index 36742aa..292101c 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -24,7 +24,6 @@ #include <device/pci_ops.h> #include <device/smbus.h> #include <pc80/mc146818rtc.h> -#include <bitops.h> #include <arch/io.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index df57a7e..b734846 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -5,7 +5,7 @@ #include <device/pci_ops.h> #include <device/smbus.h> #include <pc80/mc146818rtc.h> -#include <bitops.h> +#include <lib.h> #include <arch/io.h> #include "amd8111.h" #include "amd8111_smbus.h" diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index 7157a55..1ee1bbb 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -19,7 +19,6 @@ #include <device/pci.h> #include "lpc.h" -#include <bitops.h> #include <arch/io.h> #include <arch/ioapic.h> #include <console/console.h> /* printk */ diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index 59d74c0..caac5b1 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -21,7 +21,6 @@ #include <device/pci.h> #include <arch/ioapic.h> #include "lpc.h" -#include <bitops.h> #include <arch/io.h> #include <cbmem.h> diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c index 2fceefa..7e6ff3a 100644 --- a/src/southbridge/amd/cs5535/chipsetinit.c +++ b/src/southbridge/amd/cs5535/chipsetinit.c @@ -6,7 +6,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <bitops.h> #include "chip.h" #include "northbridge/amd/gx2/northbridge.h" #include <cpu/amd/gx2def.h> diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 22945a7..7177e4f 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -25,7 +25,6 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> -#include <bitops.h> #include <arch/io.h> #include <arch/ioapic.h> #include "sb600.h" diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c index 8c1dc90..8f25549 100644 --- a/src/southbridge/amd/sb600/sm.c +++ b/src/southbridge/amd/sb600/sm.c @@ -24,7 +24,6 @@ #include <device/pci_ops.h> #include <device/smbus.h> #include <pc80/mc146818rtc.h> -#include <bitops.h> #include <arch/io.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index be940e3..415b786 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -25,7 +25,6 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> -#include <bitops.h> #include <arch/io.h> #include <arch/ioapic.h> #include <cbmem.h> diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 05065b6..bd48334 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -24,7 +24,6 @@ #include <device/pci_ops.h> #include <device/smbus.h> #include <pc80/mc146818rtc.h> -#include <bitops.h> #include <arch/io.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 3cb0789..97f0f84 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -25,7 +25,6 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> -#include <bitops.h> #include <arch/io.h> #include "sb800.h" diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c index 50a8f0b..7a95feb 100644 --- a/src/southbridge/amd/sb800/sm.c +++ b/src/southbridge/amd/sb800/sm.c @@ -24,7 +24,6 @@ #include <device/pci_ops.h> #include <device/smbus.h> #include <pc80/mc146818rtc.h> -#include <bitops.h> #include <arch/io.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index adf5462..9956f49 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -26,7 +26,6 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> -#include <bitops.h> #include <arch/io.h> #include <arch/ioapic.h> #include "bcm5785.h" diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index fe809c4..955d3c7 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -26,7 +26,6 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> -#include <bitops.h> #include <arch/io.h> #include <device/smbus.h> #include "bcm5785.h" diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index d371882..6ccea6a 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -28,7 +28,6 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> -#include <bitops.h> #include <arch/io.h> #include <arch/ioapic.h> #include <cpu/x86/lapic.h> diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index 011faf8..269340e 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/smbus.h> -#include <bitops.h> #include <arch/io.h> #include "ck804.h" #include "smbus.h" diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index d16e3cc..1e2155a 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -31,7 +31,6 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> -#include <bitops.h> #include <arch/io.h> #include <arch/ioapic.h> #include <cpu/x86/lapic.h> diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index a945f23..6949186 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -27,7 +27,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/smbus.h> -#include <bitops.h> #include <arch/io.h> #include "mcp55.h" #include "smbus.h" diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index 26f60dd..9714085 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -33,7 +33,6 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> -#include <bitops.h> #include <arch/io.h> #include <arch/ioapic.h> #include <cpu/x86/lapic.h> diff --git a/src/southbridge/sis/sis966/sis761.c b/src/southbridge/sis/sis966/sis761.c index 3d7bc47..9dd16e8 100644 --- a/src/southbridge/sis/sis966/sis761.c +++ b/src/southbridge/sis/sis966/sis761.c @@ -37,7 +37,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> -#include <bitops.h> #include <cpu/amd/model_fxx_rev.h> #include <arch/io.h> diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index 11c8481..088b3d2 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -25,7 +25,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <pc80/mc146818rtc.h> -#include <bitops.h> +#include <lib.h> #include "k8x8xx.h" static void dram_enable(struct device *dev) diff --git a/src/superio/nsc/pc8374/superio.c b/src/superio/nsc/pc8374/superio.c index d5060c4..a018766 100644 --- a/src/superio/nsc/pc8374/superio.c +++ b/src/superio/nsc/pc8374/superio.c @@ -24,7 +24,6 @@ #include <device/pnp.h> #include <console/console.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> diff --git a/src/superio/nsc/pc87351/superio.c b/src/superio/nsc/pc87351/superio.c index 259430e..35725d6 100644 --- a/src/superio/nsc/pc87351/superio.c +++ b/src/superio/nsc/pc87351/superio.c @@ -24,7 +24,6 @@ #include <device/pnp.h> #include <console/console.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index 5da68e2..0a67dcf 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -24,7 +24,6 @@ #include <device/pnp.h> #include <console/console.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c index b5f2870..9b58df6 100644 --- a/src/superio/nsc/pc87366/superio.c +++ b/src/superio/nsc/pc87366/superio.c @@ -24,7 +24,6 @@ #include <device/pnp.h> #include <console/console.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 9d4bee0..3c714a6 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -23,7 +23,6 @@ #include <device/pnp.h> #include <console/console.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c index 39177fd..4b1963c 100644 --- a/src/superio/nsc/pc87384/superio.c +++ b/src/superio/nsc/pc87384/superio.c @@ -23,7 +23,6 @@ #include <device/pnp.h> #include <console/console.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index 81c679c..8a2e5c8 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -23,7 +23,6 @@ #include <device/pnp.h> #include <console/console.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <stdlib.h> #include "pc87392.h" diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index 9cd0e6b..a9e8823 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -25,7 +25,6 @@ #include <device/pnp.h> #include <console/console.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> diff --git a/src/superio/nsc/pc87427/superio.c b/src/superio/nsc/pc87427/superio.c index 3646fd1..f2e8d9f 100644 --- a/src/superio/nsc/pc87427/superio.c +++ b/src/superio/nsc/pc87427/superio.c @@ -24,7 +24,6 @@ #include <device/pnp.h> #include <console/console.h> #include <string.h> -#include <bitops.h> #include <stdlib.h> #include "chip.h" #include "pc87427.h" diff --git a/src/superio/nuvoton/wpcm450/superio.c b/src/superio/nuvoton/wpcm450/superio.c index 879f405..5ce1d2a 100644 --- a/src/superio/nuvoton/wpcm450/superio.c +++ b/src/superio/nuvoton/wpcm450/superio.c @@ -23,7 +23,6 @@ #include <device/pnp.h> #include <console/console.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> diff --git a/src/superio/renesas/m3885x/superio.c b/src/superio/renesas/m3885x/superio.c index 1a5fbe6..a098493 100644 --- a/src/superio/renesas/m3885x/superio.c +++ b/src/superio/renesas/m3885x/superio.c @@ -23,7 +23,6 @@ #include <console/console.h> #include <device/smbus.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <assert.h> #include <stdlib.h> diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index c4fde95..405b90e 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -25,7 +25,6 @@ #include <console/console.h> #include <device/smbus.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index f57c306..15e486c 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <device/smbus.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index fa549db..c83ab34 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -26,7 +26,6 @@ #include <console/console.h> #include <device/smbus.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index 3d6a8ed..b422ea0 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -28,7 +28,6 @@ #include <console/console.h> #include <device/smbus.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index 222e3c9..c3117b2 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -25,7 +25,6 @@ #include <console/console.h> #include <device/smbus.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c index 2658831..d6c153d 100644 --- a/src/superio/smsc/lpc47n217/superio.c +++ b/src/superio/smsc/lpc47n217/superio.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <device/smbus.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <assert.h> #include <stdlib.h> diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c index a241eb6..2f877a0 100644 --- a/src/superio/smsc/lpc47n227/superio.c +++ b/src/superio/smsc/lpc47n227/superio.c @@ -26,7 +26,6 @@ #include <console/console.h> #include <device/smbus.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <assert.h> #include <stdlib.h> diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index 070871d..0de06f8 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -25,7 +25,6 @@ #include <console/console.h> #include <device/smbus.h> #include <string.h> -#include <bitops.h> #include <pc80/keyboard.h> #include <stdlib.h> #include "chip.h" diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c index eebcacd..b99d7f7 100644 --- a/src/superio/smsc/sch4037/superio.c +++ b/src/superio/smsc/sch4037/superio.c @@ -25,7 +25,6 @@ #include <console/console.h> #include <device/smbus.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c index 2522d92..d1acb90 100644 --- a/src/superio/smsc/sio1036/superio.c +++ b/src/superio/smsc/sio1036/superio.c @@ -25,7 +25,6 @@ #include <console/console.h> #include <device/smbus.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 85747f2..f40bec6 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -26,7 +26,6 @@ #include <device/pnp.h> #include <console/console.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 1d1b169..da286a0 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -26,7 +26,6 @@ #include <device/pnp.h> #include <console/console.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> diff --git a/src/superio/winbond/w83627thg/superio.c b/src/superio/winbond/w83627thg/superio.c index 40a2326..d42f461 100644 --- a/src/superio/winbond/w83627thg/superio.c +++ b/src/superio/winbond/w83627thg/superio.c @@ -25,7 +25,6 @@ #include <device/pnp.h> #include <console/console.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include "chip.h" diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index 933bde6..f606948 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -25,7 +25,6 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include "chip.h" diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index 8f090d0..cdf7ecd 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -23,7 +23,7 @@ #include <device/pnp.h> #include <console/console.h> #include <string.h> -#include <bitops.h> +#include <lib.h> #include <uart8250.h> #include <pc80/mc146818rtc.h> #include <stdlib.h> diff --git a/src/superio/winbond/w83977f/superio.c b/src/superio/winbond/w83977f/superio.c index e197b37..353d428 100644 --- a/src/superio/winbond/w83977f/superio.c +++ b/src/superio/winbond/w83977f/superio.c @@ -23,7 +23,6 @@ #include <device/pnp.h> #include <console/console.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index 40952d2..eabf080 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -25,7 +25,6 @@ #include <device/pnp.h> #include <console/console.h> #include <string.h> -#include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h>

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coreboot November 2012