coreboot August 2011

coreboot@coreboot.org

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217 discussions

Patch set updated: a91c5a4 Miscellaneous AMD F14 warning fixes
by Frank Vibrans III 17 Aug '11

17 Aug '11

Frank Vibrans III (frank.vibrans(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/133 -gerrit commit a91c5a433c5a32bcab8610b4722311991ab286d0 Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Aug 4 16:18:16 2011 -0600 Miscellaneous AMD F14 warning fixes This commit adds in some more fixes to AMD F14 compile warnings. The change in the mtrr.c file is in prep- aration for changes yet to com, but it is currently innocuous. Change-Id: I6b204fe0af16a97d982f46f0dfeaccc4b8eb883e Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> --- src/include/cpu/amd/amdfam14.h | 2 ++ src/include/cpu/amd/mtrr.h | 8 ++++++-- src/include/pc80/i8254.h | 2 ++ src/pc80/i8254.c | 2 +- 4 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/include/cpu/amd/amdfam14.h b/src/include/cpu/amd/amdfam14.h index c4b7e6d..a732219 100644 --- a/src/include/cpu/amd/amdfam14.h +++ b/src/include/cpu/amd/amdfam14.h @@ -42,5 +42,7 @@ void wait_all_other_cores_started(u32 bsp_apicid); void wait_all_aps_started(u32 bsp_apicid); void allow_all_aps_stop(u32 bsp_apicid); #endif +void get_bus_conf(void); +u32 get_initial_apicid(void); #endif /* CPU_AMD_FAM14_H */ diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index c0d6b51..3637dd9 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -27,8 +27,12 @@ #define TOP_MEM_MSR 0xC001001A #define TOP_MEM2_MSR 0xC001001D -#define TOP_MEM TOP_MEM_MSR -#define TOP_MEM2 TOP_MEM2_MSR +#ifndef TOP_MEM + #define TOP_MEM TOP_MEM_MSR +#endif +#ifndef TOP_MEM2 + #define TOP_MEM2 TOP_MEM2_MSR +#endif #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) diff --git a/src/include/pc80/i8254.h b/src/include/pc80/i8254.h index b0d3a93..82f31e6 100644 --- a/src/include/pc80/i8254.h +++ b/src/include/pc80/i8254.h @@ -20,6 +20,8 @@ #ifndef PC80_I8254_H #define PC80_I8254_H +void setup_i8254(void); + /* Ports for the 8254 timer chip */ #define TIMER0_PORT 0x40 #define TIMER1_PORT 0x41 diff --git a/src/pc80/i8254.c b/src/pc80/i8254.c index ca993f4..e5dc40b 100644 --- a/src/pc80/i8254.c +++ b/src/pc80/i8254.c @@ -35,7 +35,7 @@ void setup_i8254(void) outb(0x12, TIMER1_PORT); } -#if CONFIG_UDELAY_TIMER2 +#ifdef CONFIG_UDELAY_TIMER2 static void load_timer2(unsigned int ticks) { /* Set up the timer gate, turn off the speaker */

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Re: [coreboot] Changing DRAM Frequency
by Rudolf Marek 17 Aug '11

17 Aug '11

> I am aware that coreboot initializes DRAM and sets its frequency (cache-as-ram) > during boot. I would like to know if it is possible to change the DRAM frequency > by following the same initialization sequence without rebooting the system > (along with preserving the application's memory context). Yes I had similar thoughts and I think it could work like this: 1) Execute code from ROM 2) There, issue the self refresh cycling to memory controller 3) turn off clocks for memory 4) do whatever else 5) restore clocks/just exit from self refresh (same code as S3 resume) In theory it could be possible to shift frequency / settings this way, however DQS strobing fine tunes might make it impossible. Thanks Rudolf

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Re: [coreboot] E350M1 does not POST
by Florian Zumbiehl 17 Aug '11

17 Aug '11

Hi, > On Tue, Aug 16, 2011 at 10:49 PM, Marshall Buschman > <mbuschman(a)lucidmachines.com> wrote: > > On 08/16/2011 10:36 PM, Florian Zumbiehl wrote: > >> > >> Hi, > >> > >>> Upon booting, I get this: > >> > >> [...] > >> > >> you could try commit 0df0e14fb, that may or may not work, the commit after > >> that broke fusion boards completely, apparently. > >> > >> Florian > >> > > Thank you! I can confirm that 0df0e14fb works properly. > > -Marshall > > Frank, > > It looks like we have a regression. Is there some dependency on the > other patches that have not yet been committed? in principle there probably is (http://www.coreboot.org/pipermail/coreboot/2011-August/066113.html), but that causes the serial line to go completely silent (http://www.coreboot.org/pipermail/coreboot/2011-August/066122.html, http://www.coreboot.org/pipermail/coreboot/2011-August/066133.html) Florian

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E350M1 does not POST
by Marshall Buschman 17 Aug '11

17 Aug '11

Hey All: Upon booting, I get this: coreboot-4.0-rf44bb4f Sat Aug 13 16:19:31 CDT 2011 starting... BSP Family_Model: 00500f10 cpu_init_detectedx = 00000000 Got past sb800_early_setup BSP Family_Model: 00500f10 cpu_init_detectedx = 00000001 Got past sb800_early_setup ASSERTION FAILED: file 'src/vendorcode/amd/agesa/f14/Proc/CPU/Table.c', line 18 The machine does not POST or display any further output. Please advise. Thank you! -Marshall Buschman

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Re: [coreboot] Changing DRAM Frequency
by Marc Jones 17 Aug '11

17 Aug '11

Hi Tapasya, On Tue, Aug 16, 2011 at 5:47 PM, Tapasya Patki <tpatki(a)email.arizona.edu> wrote: > Hi, > > I'm working on a research project for dynamic voltage/frequency scaling for > DRAM. > > I am aware that coreboot initializes DRAM and sets its frequency > (cache-as-ram) during boot. I would like to know if it is possible to change > the DRAM frequency by following the same initialization sequence without > rebooting the system (along with preserving the application's memory > context). > > Thanks, > Tapasya Patki I think it depends on the memory controller and how much system control you have at the point you wish to make the change. Marc -- http://se-eng.com

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Patch set updated: d728674 Add automatic SMBIOS table generation
by Sven Schnelle 17 Aug '11

17 Aug '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/152 -gerrit commit d72867419468c612f18158045817e8e38094d99b Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Aug 14 20:56:34 2011 +0200 Add automatic SMBIOS table generation Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- Makefile.inc | 1 + src/Kconfig | 15 ++- src/arch/x86/boot/Makefile.inc | 2 + src/arch/x86/boot/smbios.c | 293 ++++++++++++++++++++++++ src/arch/x86/boot/tables.c | 23 ++- src/include/cbmem.h | 1 + src/include/device/device.h | 6 + src/include/smbios.h | 197 ++++++++++++++++ src/lib/cbmem.c | 1 + src/mainboard/emulation/qemu-x86/northbridge.c | 72 ++++++- src/mainboard/getac/p470/acpi_tables.c | 10 - src/mainboard/getac/p470/dmi.h | 31 --- src/mainboard/ibase/mb899/acpi_tables.c | 10 - src/mainboard/ibase/mb899/dmi.h | 29 --- src/mainboard/intel/d945gclf/acpi_tables.c | 10 - src/mainboard/intel/d945gclf/dmi.h | 29 --- src/mainboard/iwave/iWRainbowG6/acpi_tables.c | 10 - src/mainboard/iwave/iWRainbowG6/dmi.h | 34 --- src/mainboard/kontron/986lcd-m/acpi_tables.c | 10 - src/mainboard/kontron/986lcd-m/dmi.h | 29 --- src/mainboard/lenovo/t60/acpi_tables.c | 10 - src/mainboard/lenovo/x60/acpi_tables.c | 10 - src/mainboard/roda/rk886ex/acpi_tables.c | 10 - src/mainboard/roda/rk886ex/dmi.h | 29 --- src/mainboard/via/vt8454c/acpi_tables.c | 5 - src/mainboard/via/vt8454c/dmi.h | 29 --- 26 files changed, 604 insertions(+), 302 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 89467db..2cc547a 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -128,6 +128,7 @@ $(obj)/build.h: .xcompile printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_DMI_DATE \"`LANG= date +"%m/%d/%Y"`\"\n" >> $(obj)/build.ht printf "\n" >> $(obj)/build.ht printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.ht diff --git a/src/Kconfig b/src/Kconfig index 7b4f487..f96c903 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -87,7 +87,7 @@ config SCONFIG_GENPARSER help Enable this option if you are working on the sconfig device tree parser and made changes to sconfig.l and - sconfig.y. + sconfig.y. Otherwise, say N. config USE_OPTION_TABLE @@ -304,6 +304,10 @@ config GENERATE_PIRQ_TABLE bool default HAVE_PIRQ_TABLE +config GENERATE_SMBIOS_TABLES + bool + default y + menu "System tables" config WRITE_HIGH_TABLES @@ -342,6 +346,15 @@ config GENERATE_PIRQ_TABLE If unsure, say Y. +config GENERATE_SMBIOS_TABLES + depends on ARCH_X86 + bool "Generate SMBIOS tables" + default y + help + Generate SMBIOS tables for this board. + + If unsure, say Y. + endmenu menu "Payload" diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index d4a377f..3f11c01 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -6,8 +6,10 @@ ramstage-y += tables.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S $(obj)/arch/x86/boot/coreboot_table.ramstage.o : $(OPTION_TABLE_H) +$(obj)/arch/x86/boot/smbios.ramstage.o: $(obj)/build.h diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c new file mode 100644 index 0000000..e5156d9 --- /dev/null +++ b/src/arch/x86/boot/smbios.c @@ -0,0 +1,293 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <string.h> +#include <smbios.h> +#include <console/console.h> +#include <build.h> +#include <device/device.h> +#include <arch/cpu.h> +#include <cpu/x86/name.h> +#include <cbfs_core.h> +#include <arch/byteorder.h> + +static u8 smbios_checksum(u8 *p, u32 length) +{ + u8 ret = 0; + while (length--) + ret += *p++; + return -ret; +} + + +int smbios_add_string(char *start, const char *str) +{ + int i = 1; + char *p = start; + + for(;;) { + if (!*p) { + strcpy(p, str); + p += strlen(str); + *p++ = '\0'; + *p++ = '\0'; + return i; + } + + if (!strcmp(p, str)) + return i; + + p += strlen(p)+1; + i++; + } +} + +int smbios_string_table_len(char *start) +{ + char *p = start; + int i, len = 0; + + while(*p) { + i = strlen(p) + 1; + p += i; + len += i; + } + return len + 1; +} + +static int smbios_cpu_vendor(char *start) +{ + char tmp[13]; + u32 *_tmp = (u32 *)tmp; + struct cpuid_result res = cpuid(0); + + _tmp[0] = res.ebx; + _tmp[1] = res.edx; + _tmp[2] = res.ecx; + tmp[12] = '\0'; + return smbios_add_string(start, tmp); + +} + +static int smbios_processor_name(char *start) +{ + char tmp[49]; + u32 *_tmp = (u32 *)tmp; + struct cpuid_result res; + int i; + + for (i = 0; i < 3; i++) { + res = cpuid(0x80000002 + i); + _tmp[i * 4 + 0] = res.eax; + _tmp[i * 4 + 1] = res.ebx; + _tmp[i * 4 + 2] = res.ecx; + _tmp[i * 4 + 3] = res.edx; + } + + tmp[48] = 0; + return smbios_add_string(start, tmp); +} + +static int smbios_write_type0(unsigned long *current, int handle) +{ + struct cbfs_header *hdr; + struct smbios_type0 *t = (struct smbios_type0 *)*current; + int len = sizeof(struct smbios_type0); + + memset(t, 0, sizeof(struct smbios_type0)); + t->type = SMBIOS_BIOS_INFORMATION; + t->handle = handle; + t->length = len - 2; + + t->vendor = smbios_add_string(t->eos, "coreboot"); + t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE); + t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION); + + if ((hdr = get_cbfs_header()) != (struct cbfs_header *)0xffffffff) + t->bios_rom_size = (ntohl(hdr->romsize) / 65535) - 1; + t->system_bios_major_release = 4; + t->bios_characteristics = + BIOS_CHARACTERISTICS_PCI_SUPPORTED | +#if CONFIG_CARDBUS_PLUGIN_SUPPORT + BIOS_CHARACTERISTICS_PC_CARD | +#endif + BIOS_CHARACTERISTICS_SELECTABLE_BOOT | + BIOS_CHARACTERISTICS_UPGRADEABLE; + +#if CONFIG_GENERATE_ACPI_TABLES + t->bios_characteristics_ext1 = BIOS_EXT1_CHARACTERISTICS_ACPI; +#endif + t->bios_characteristics_ext2 = BIOS_EXT2_CHARACTERISTICS_TARGET; + len = t->length + smbios_string_table_len(t->eos); + *current += len; + return len; +} + +static int smbios_write_type1(unsigned long *current, int handle) +{ + struct smbios_type1 *t = (struct smbios_type1 *)*current; + int len = sizeof(struct smbios_type1); + + memset(t, 0, sizeof(struct smbios_type1)); + t->type = SMBIOS_SYSTEM_INFORMATION; + t->handle = handle; + t->length = len - 2; + t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); + t->product_name = smbios_add_string(t->eos, CONFIG_MAINBOARD_PART_NUMBER); + len = t->length + smbios_string_table_len(t->eos); + *current += len; + return len; +} + +static int smbios_write_type3(unsigned long *current, int handle) +{ + struct smbios_type3 *t = (struct smbios_type3 *)*current; + int len = sizeof(struct smbios_type3); + + memset(t, 0, sizeof(struct smbios_type3)); + t->type = SMBIOS_SYSTEM_ENCLOSURE; + t->handle = handle; + t->length = len - 2; + t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); + t->bootup_state = SMBIOS_STATE_SAFE; + t->power_supply_state = SMBIOS_STATE_SAFE; + t->thermal_state = SMBIOS_STATE_SAFE; + t->_type = 3; + t->security_status = SMBIOS_STATE_SAFE; + len = t->length + smbios_string_table_len(t->eos); + *current += len; + return len; +} + +static int smbios_write_type4(unsigned long *current, int handle) +{ + struct cpuid_result res; + struct smbios_type4 *t = (struct smbios_type4 *)*current; + int len = sizeof(struct smbios_type4); + + res = cpuid(1); + + memset(t, 0, sizeof(struct smbios_type4)); + t->type = SMBIOS_PROCESSOR_INFORMATION; + t->handle = handle; + t->length = len - 2; + t->processor_id[0] = res.eax; + t->processor_id[1] = res.edx; + t->processor_manufacturer = smbios_cpu_vendor(t->eos); + t->processor_version = smbios_processor_name(t->eos); + t->processor_family = 0x0c; + t->processor_type = 3; /* System Processor */ + t->processor_upgrade = 0x06; + t->core_count = (res.ebx >> 16) & 0xff; + t->l1_cache_handle = 0xffff; + t->l2_cache_handle = 0xffff; + t->l3_cache_handle = 0xffff; + t->processor_upgrade = 1; + len = t->length + smbios_string_table_len(t->eos); + *current += len; + return len; +} + +static int smbios_write_type32(unsigned long *current, int handle) +{ + struct smbios_type32 *t = (struct smbios_type32 *)*current; + int len = sizeof(struct smbios_type32); + + memset(t, 0, sizeof(struct smbios_type32)); + t->type = SMBIOS_SYSTEM_BOOT_INFORMATION; + t->handle = handle; + t->length = len - 2; + *current += len; + return len; +} + +static int smbios_write_type127(unsigned long *current, int handle) +{ + struct smbios_type127 *t = (struct smbios_type127 *)*current; + int len = sizeof(struct smbios_type127); + + memset(t, 0, sizeof(struct smbios_type127)); + t->type = SMBIOS_END_OF_TABLE; + t->handle = handle; + t->length = len - 2; + *current += len; + return len; +} + +static int smbios_walk_device_tree(device_t tree, int *handle, unsigned long *current) +{ + device_t dev; + int len = 0; + + for(dev = tree; dev; dev = dev->next) { + printk(BIOS_INFO, "%s (%s)\n", dev_path(dev), dev->chip_ops ? dev->chip_ops->name : ""); + + if (dev->ops && dev->ops->get_smbios_data) + len += dev->ops->get_smbios_data(dev, handle, current); + + if (dev->chip_ops && dev->chip_ops->get_smbios_data) + len += dev->chip_ops->get_smbios_data(dev, handle, current); + } + return len; +} + +unsigned long smbios_write_tables(unsigned long current) +{ + struct smbios_entry *se; + unsigned long tables; + int len, handle = 0; + + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "%s: %08lx\n", __func__, current); + + se = (struct smbios_entry *)current; + current += sizeof(struct smbios_entry); + current = ALIGN(current, 16); + + tables = current; + len = smbios_write_type0(&current, handle++); + len += smbios_write_type1(&current, handle++); + len += smbios_write_type3(&current, handle++); + len += smbios_write_type4(&current, handle++); + len += smbios_write_type32(&current, handle++); + + len += smbios_walk_device_tree(all_devices, &handle, &current); + + len += smbios_write_type127(&current, handle++); + + memset(se, 0, sizeof(struct smbios_entry)); + memcpy(se->anchor, "_SM_", 4); + se->length = sizeof(struct smbios_entry); + se->major_version = 2; + se->minor_version = 7; + se->max_struct_size = 24; + se->struct_count = handle; + memcpy(se->intermediate_anchor_string, "_DMI_", 5); + + se->struct_table_address = (u32)tables; + se->struct_table_length = len; + + se->intermediate_checksum = smbios_checksum((u8 *)se + 0x10, + sizeof(struct smbios_entry) - 0x10); + se->checksum = smbios_checksum((u8 *)se, sizeof(struct smbios_entry)); + return current; +} diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index d816e76..cf207fe 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -31,6 +31,7 @@ #include <cpu/x86/multiboot.h> #include <cbmem.h> #include <lib.h> +#include <smbios.h> uint64_t high_tables_base = 0; uint64_t high_tables_size; @@ -120,7 +121,7 @@ struct lb_memory *write_tables(void) #endif /* CONFIG_GENERATE_MP_TABLE */ #if CONFIG_GENERATE_ACPI_TABLES == 1 -#define MAX_ACPI_SIZE (47 * 1024) +#define MAX_ACPI_SIZE (45 * 1024) post_code(0x9c); /* Write ACPI tables to F segment and high tables area */ @@ -178,7 +179,27 @@ struct lb_memory *write_tables(void) } #endif +#define MAX_SMBIOS_SIZE 2048 +#if CONFIG_GENERATE_SMBIOS_TABLES + high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS, MAX_SMBIOS_SIZE); + if (high_table_pointer) { + unsigned long new_high_table_pointer; + new_high_table_pointer = smbios_write_tables(high_table_pointer); + rom_table_end = ALIGN(rom_table_end, 16); + memcpy((void *)rom_table_end, (void *)high_table_pointer, sizeof(struct smbios_entry)); + + if (new_high_table_pointer > ( high_table_pointer + MAX_SMBIOS_SIZE)) { + printk(BIOS_ERR, "ERROR: Increase SMBIOS size\n"); + } + printk(BIOS_DEBUG, "SMBIOS tables: %ld bytes.\n", + new_high_table_pointer - high_table_pointer); + } else { + unsigned long new_rom_table_end = smbios_write_tables(rom_table_end); + printk(BIOS_DEBUG, "SMBIOS size %ld bytes\n", new_rom_table_end - rom_table_end); + rom_table_end = ALIGN(new_rom_table_end, 16); + } +#endif #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) post_code(0x9d); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index d9ec93c..7c5ec07 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -38,6 +38,7 @@ extern uint64_t high_tables_base, high_tables_size; #define CBMEM_ID_PIRQ 0x49525154 #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_RESUME 0x5245534d +#define CBMEM_ID_SMBIOS 0x534d4254 #define CBMEM_ID_NONE 0x00000000 void cbmem_initialize(void); diff --git a/src/include/device/device.h b/src/include/device/device.h index 42b68f6..a7de0c9 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -16,6 +16,9 @@ struct smbus_bus_operations; struct chip_operations { void (*enable_dev)(struct device *dev); const char *name; +#if CONFIG_GENERATE_SMBIOS_TABLES + int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current); +#endif }; #define CHIP_NAME(X) .name = X, @@ -31,6 +34,9 @@ struct device_operations { void (*enable)(device_t dev); void (*set_link)(device_t dev, unsigned int link); void (*reset_bus)(struct bus *bus); +#if CONFIG_GENERATE_SMBIOS_TABLES + int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current); +#endif const struct pci_operations *ops_pci; const struct smbus_bus_operations *ops_smbus_bus; const struct pci_bus_operations *ops_pci_bus; diff --git a/src/include/smbios.h b/src/include/smbios.h new file mode 100644 index 0000000..f13d621 --- /dev/null +++ b/src/include/smbios.h @@ -0,0 +1,197 @@ +#ifndef SMBIOS_H +#define SMBIOS_H + +#include <types.h> + +unsigned long smbios_write_tables(unsigned long start); +int smbios_add_string(char *start, const char *str); +int smbios_string_table_len(char *start); + +#define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) +#define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) +#define BIOS_CHARACTERISTICS_PNP (1 << 9) +#define BIOS_CHARACTERISTICS_APM (1 << 10) +#define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11) +#define BIOS_CHARACTERISTICS_SHADOW (1 << 12) +#define BIOS_CHARACTERISTICS_BOOT_FROM_CD (1 << 15) +#define BIOS_CHARACTERISTICS_SELECTABLE_BOOT (1 << 16) +#define BIOS_CHARACTERISTICS_BIOS_SOCKETED (1 << 17) + +#define BIOS_EXT1_CHARACTERISTICS_ACPI (1 << 0) +#define BIOS_EXT2_CHARACTERISTICS_TARGET (1 << 2) + +#define SMBIOS_STATE_SAFE 3 +typedef enum { + SMBIOS_BIOS_INFORMATION=0, + SMBIOS_SYSTEM_INFORMATION=1, + SMBIOS_SYSTEM_ENCLOSURE=3, + SMBIOS_PROCESSOR_INFORMATION=4, + SMBIOS_CACHE_INFORMATION=7, + SMBIOS_SYSTEM_SLOTS=9, + SMBIOS_PHYS_MEMORY_ARRAY=16, + SMBIOS_MEMORY_DEVICE=17, + SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS=19, + SMBIOS_SYSTEM_BOOT_INFORMATION=32, + SMBIOS_END_OF_TABLE=127, +} smbios_struct_type_t; + +struct smbios_entry { + u8 anchor[4]; + u8 checksum; + u8 length; + u8 major_version; + u8 minor_version; + u16 max_struct_size; + u8 entry_point_rev; + u8 formwatted_area[5]; + u8 intermediate_anchor_string[5]; + u8 intermediate_checksum; + u16 struct_table_length; + u32 struct_table_address; + u16 struct_count; + u8 smbios_bcd_revision; +} __attribute__((packed)); + +struct smbios_type0 { + u8 type; + u8 length; + u16 handle; + u8 vendor; + u8 bios_version; + u16 bios_start_segment; + u8 bios_release_date; + u8 bios_rom_size; + u64 bios_characteristics; + u8 bios_characteristics_ext1; + u8 bios_characteristics_ext2; + u8 system_bios_major_release; + u8 system_bios_minor_release; + u8 ec_major_release; + u8 ec_minor_release; + char eos[2]; +} __attribute__((packed)); + +struct smbios_type1 { + u8 type; + u8 length; + u16 handle; + u8 manufacturer; + u8 product_name; + u8 version; + u8 serial_number; + u8 uuid[16]; + u8 wakeup_type; + u8 sku; + u8 family; + char eos[2]; +} __attribute__((packed)); + +struct smbios_type3 { + u8 type; + u8 length; + u16 handle; + u8 manufacturer; + u8 _type; + u8 version; + u8 serial_number; + u8 asset_tag_number; + u8 bootup_state; + u8 power_supply_state; + u8 thermal_state; + u8 security_status; + u32 oem_defined; + u8 height; + u8 number_of_power_cords; + u8 element_count; + u8 element_record_length; + char eos[2]; +} __attribute__((packed)); + +struct smbios_type4 { + u8 type; + u8 length; + u16 handle; + u8 socket_designation; + u8 processor_type; + u8 processor_family; + u8 processor_manufacturer; + u32 processor_id[2]; + u8 processor_version; + u8 voltage; + u16 external_clock; + u16 max_speed; + u16 current_speed; + u8 status; + u8 processor_upgrade; + u16 l1_cache_handle; + u16 l2_cache_handle; + u16 l3_cache_handle; + u8 serial_number; + u8 asset_tag; + u8 part_number; + u8 core_count; + u8 core_enabled; + u8 thread_count; + u16 processor_characteristics; + u16 processor_family2; + char eos[2]; +} __attribute__((packed)); + +struct smbios_type16 { + u8 type; + u8 length; + u16 handle; + u8 location; + u8 use; + u8 memory_error_correction; + u32 maximum_capacity; + u16 memory_error_information_handle; + u16 number_of_memory_devices; + u64 extended_maximum_capacity; + char eos[2]; +} __attribute__((packed)); + +struct smbios_type17 { + u8 type; + u8 length; + u16 handle; + u16 phys_memory_array_handle; + u16 memory_error_information_handle; + u16 total_width; + u16 data_width; + u16 size; + u8 form_factor; + u8 device_set; + u8 device_locator; + u8 bank_locator; + u8 memory_type; + u16 type_detail; + u16 speed; + u8 manufacturer; + u8 serial_number; + u8 asset_tag; + u8 part_number; + u8 attributes; + u16 extended_size; + u16 clock_speed; + + char eos[2]; +} __attribute__((packed)); + +struct smbios_type32 { + u8 type; + u8 length; + u16 handle; + u8 reserved[6]; + u8 boot_status; + u8 eos[2]; +} __attribute__((packed)); + +struct smbios_type127 { + u8 type; + u8 length; + u16 handle; + u8 eos[2]; +} __attribute__((packed)); + +#endif diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 5417ab8..eecefcd 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -229,6 +229,7 @@ void cbmem_list(void) case CBMEM_ID_PIRQ: printk(BIOS_DEBUG, "IRQ TABLE "); break; case CBMEM_ID_MPTABLE: printk(BIOS_DEBUG, "SMP TABLE "); break; case CBMEM_ID_RESUME: printk(BIOS_DEBUG, "ACPI RESUME"); break; + case CBMEM_ID_SMBIOS: printk(BIOS_DEBUG, "SMBIOS "); break; default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id); } printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base); diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c index 1899648..3f22437 100644 --- a/src/mainboard/emulation/qemu-x86/northbridge.c +++ b/src/mainboard/emulation/qemu-x86/northbridge.c @@ -9,6 +9,7 @@ #include <bitops.h> #include "chip.h" #include <delay.h> +#include <smbios.h> #if CONFIG_WRITE_HIGH_TABLES==1 #include <cbmem.h> @@ -19,18 +20,24 @@ #define HIGH_RAM_ADDR 0x35 #define LOW_RAM_ADDR 0x34 -static void cpu_pci_domain_set_resources(device_t dev) +static unsigned long qemu_get_memory_size(void) { - u32 pci_tolm = find_pci_tolm(dev->link_list); - unsigned long tomk = 0, tolmk; - int idx; - + unsigned long tomk; outb (HIGH_RAM_ADDR, CMOS_ADDR_PORT); tomk = ((unsigned long) inb(CMOS_DATA_PORT)) << 14; outb (LOW_RAM_ADDR, CMOS_ADDR_PORT); tomk |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6; tomk += 16 * 1024; + return tomk; +} + +static void cpu_pci_domain_set_resources(device_t dev) +{ + u32 pci_tolm = find_pci_tolm(dev->link_list); + unsigned long tomk = 0, tolmk; + int idx; + tomk = qemu_get_memory_size(); printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n", tomk, tomk / 1024); @@ -80,12 +87,67 @@ static void cpu_pci_domain_read_resources(struct device *dev) IORESOURCE_ASSIGNED; } +#if CONFIG_GENERATE_SMBIOS_TABLES +static int qemu_get_smbios_data16(int handle, unsigned long *current) +{ + struct smbios_type16 *t = (struct smbios_type16 *)*current; + int len = sizeof(struct smbios_type16); + + memset(t, 0, sizeof(struct smbios_type16)); + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->handle = handle; + t->length = len - 2; + t->location = 3; /* Location: System Board */ + t->use = 3; /* System memory */ + t->memory_error_correction = 3; /* No error correction */ + t->maximum_capacity = qemu_get_memory_size(); + *current += len; + return len; +} + +static int qemu_get_smbios_data17(int handle, int parent_handle, unsigned long *current) +{ + struct smbios_type17 *t = (struct smbios_type17 *)*current; + int len; + + memset(t, 0, sizeof(struct smbios_type17)); + t->type = SMBIOS_MEMORY_DEVICE; + t->handle = handle; + t->phys_memory_array_handle = parent_handle; + t->length = sizeof(struct smbios_type17) - 2; + t->size = qemu_get_memory_size() / 1024; + t->data_width = 64; + t->total_width = 64; + t->form_factor = 9; /* DIMM */ + t->device_locator = smbios_add_string(t->eos, "Virtual"); + t->memory_type = 0x12; /* DDR */ + t->type_detail = 0x80; /* Synchronous */ + t->speed = 200; + t->clock_speed = 200; + t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); + len = t->length + smbios_string_table_len(t->eos); + *current += len; + return len; +} + +static int qemu_get_smbios_data(device_t dev, int *handle, unsigned long *current) +{ + int len; + len = qemu_get_smbios_data16(*handle, current); + len += qemu_get_smbios_data17(*handle+1, *handle, current); + *handle += 2; + return len; +} +#endif static struct device_operations pci_domain_ops = { .read_resources = cpu_pci_domain_read_resources, .set_resources = cpu_pci_domain_set_resources, .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, +#if CONFIG_GENERATE_SMBIOS_TABLES + .get_smbios_data = qemu_get_smbios_data, +#endif }; static void enable_dev(struct device *dev) diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index 649dff6..46e7b88 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -29,7 +29,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "dmi.h" extern unsigned char AmlCode[]; @@ -355,15 +354,6 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; -#endif - printk(BIOS_INFO, "ACPI: done.\n"); return current; } diff --git a/src/mainboard/getac/p470/dmi.h b/src/mainboard/getac/p470/dmi.h deleted file mode 100644 index fde4d8a..0000000 --- a/src/mainboard/getac/p470/dmi.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#define DMI_TABLE_SIZE 0x55 - -static const u8 dmi_table[DMI_TABLE_SIZE] = { - 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, - 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, - 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, - 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, - 0x30, 0x30, 0x38, 0x00, 0x00 -}; diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c index 0089e21..dbe1e91 100644 --- a/src/mainboard/ibase/mb899/acpi_tables.c +++ b/src/mainboard/ibase/mb899/acpi_tables.c @@ -28,7 +28,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> -#include "dmi.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -258,15 +257,6 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; -#endif - printk(BIOS_INFO, "ACPI: done.\n"); return current; } diff --git a/src/mainboard/ibase/mb899/dmi.h b/src/mainboard/ibase/mb899/dmi.h deleted file mode 100644 index 96b5873..0000000 --- a/src/mainboard/ibase/mb899/dmi.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define DMI_TABLE_SIZE 0x55 - -static u8 dmi_table[DMI_TABLE_SIZE] = { - 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, - 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, - 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, - 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, - 0x30, 0x30, 0x38, 0x00, 0x00 -}; diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c index bc0a790..f7e13e9 100644 --- a/src/mainboard/intel/d945gclf/acpi_tables.c +++ b/src/mainboard/intel/d945gclf/acpi_tables.c @@ -28,7 +28,6 @@ #include <device/pci_ids.h> #include <cpu/x86/msr.h> #include <arch/ioapic.h> -#include "dmi.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -245,15 +244,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, ssdt); printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; -#endif - printk(BIOS_INFO, "ACPI: done.\n"); return current; } diff --git a/src/mainboard/intel/d945gclf/dmi.h b/src/mainboard/intel/d945gclf/dmi.h deleted file mode 100644 index 96b5873..0000000 --- a/src/mainboard/intel/d945gclf/dmi.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define DMI_TABLE_SIZE 0x55 - -static u8 dmi_table[DMI_TABLE_SIZE] = { - 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, - 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, - 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, - 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, - 0x30, 0x30, 0x38, 0x00, 0x00 -}; diff --git a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c index 92874bc..8c8e788 100644 --- a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c +++ b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c @@ -28,7 +28,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> -#include "dmi.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -264,15 +263,6 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; -#endif - printk(BIOS_INFO, "ACPI: done.\n"); return current; } diff --git a/src/mainboard/iwave/iWRainbowG6/dmi.h b/src/mainboard/iwave/iWRainbowG6/dmi.h deleted file mode 100644 index d076dff..0000000 --- a/src/mainboard/iwave/iWRainbowG6/dmi.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define DMI_TABLE_SIZE 0x55 - -static u8 dmi_table[DMI_TABLE_SIZE] = { - 0x5f, 0x53, 0x4d, 0x5f, 0x2d, 0x1f, 0x02, 0x03, 0x51, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xeb, 0xa8, 0x03, 0xa0, 0xff, 0x0f, 0x00, - 0x01, 0x00, 0x23, 0x00, - 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, - 0xcb, 0x7f, 0x00, 0x00, - 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, - 0x65, 0x6d, 0x73, 0x20, - 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, - 0x31, 0x33, 0x2f, 0x32, - 0x30, 0x30, 0x38, 0x00, 0x00 -}; diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c index 0089e21..dbe1e91 100644 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -28,7 +28,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> -#include "dmi.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -258,15 +257,6 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; -#endif - printk(BIOS_INFO, "ACPI: done.\n"); return current; } diff --git a/src/mainboard/kontron/986lcd-m/dmi.h b/src/mainboard/kontron/986lcd-m/dmi.h deleted file mode 100644 index 96b5873..0000000 --- a/src/mainboard/kontron/986lcd-m/dmi.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define DMI_TABLE_SIZE 0x55 - -static u8 dmi_table[DMI_TABLE_SIZE] = { - 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, - 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, - 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, - 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, - 0x30, 0x30, 0x38, 0x00, 0x00 -}; diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index 3742c20..fa135a6 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -29,7 +29,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "dmi.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -294,15 +293,6 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; -#endif - printk(BIOS_INFO, "ACPI: done.\n"); /* Enable Dummy DCC ON# for DVI */ diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index 3742c20..fa135a6 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -29,7 +29,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "dmi.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -294,15 +293,6 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; -#endif - printk(BIOS_INFO, "ACPI: done.\n"); /* Enable Dummy DCC ON# for DVI */ diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c index 3742c20..fa135a6 100644 --- a/src/mainboard/roda/rk886ex/acpi_tables.c +++ b/src/mainboard/roda/rk886ex/acpi_tables.c @@ -29,7 +29,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "dmi.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -294,15 +293,6 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; -#endif - printk(BIOS_INFO, "ACPI: done.\n"); /* Enable Dummy DCC ON# for DVI */ diff --git a/src/mainboard/roda/rk886ex/dmi.h b/src/mainboard/roda/rk886ex/dmi.h deleted file mode 100644 index 96b5873..0000000 --- a/src/mainboard/roda/rk886ex/dmi.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define DMI_TABLE_SIZE 0x55 - -static u8 dmi_table[DMI_TABLE_SIZE] = { - 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, - 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, - 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, - 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, - 0x30, 0x30, 0x38, 0x00, 0x00 -}; diff --git a/src/mainboard/via/vt8454c/acpi_tables.c b/src/mainboard/via/vt8454c/acpi_tables.c index 434bf87..03bacc3 100644 --- a/src/mainboard/via/vt8454c/acpi_tables.c +++ b/src/mainboard/via/vt8454c/acpi_tables.c @@ -26,7 +26,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "dmi.h" extern const unsigned char AmlCode[]; @@ -194,10 +193,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_create_fadt(fadt, facs, dsdt); acpi_add_table(rsdp, fadt); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); - printk(BIOS_INFO, "ACPI: done.\n"); return current; } diff --git a/src/mainboard/via/vt8454c/dmi.h b/src/mainboard/via/vt8454c/dmi.h deleted file mode 100644 index 96b5873..0000000 --- a/src/mainboard/via/vt8454c/dmi.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define DMI_TABLE_SIZE 0x55 - -static u8 dmi_table[DMI_TABLE_SIZE] = { - 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, - 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, - 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, - 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, - 0x30, 0x30, 0x38, 0x00, 0x00 -};

1 0

Patch set updated: 8d4bc2c Add automatic SMBIOS table generation
by Sven Schnelle 17 Aug '11

17 Aug '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/152 -gerrit commit 8d4bc2c422f6b650a918cef5b6766f1c2552c22b Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Aug 14 20:56:34 2011 +0200 Add automatic SMBIOS table generation Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- Makefile.inc | 1 + src/Kconfig | 15 ++- src/arch/x86/boot/Makefile.inc | 2 + src/arch/x86/boot/smbios.c | 290 ++++++++++++++++++++++++ src/arch/x86/boot/tables.c | 23 ++- src/include/cbmem.h | 1 + src/include/device/device.h | 2 + src/include/smbios.h | 197 ++++++++++++++++ src/lib/cbmem.c | 1 + src/mainboard/emulation/qemu-x86/northbridge.c | 69 ++++++- src/mainboard/getac/p470/acpi_tables.c | 10 - src/mainboard/getac/p470/dmi.h | 31 --- src/mainboard/ibase/mb899/acpi_tables.c | 10 - src/mainboard/ibase/mb899/dmi.h | 29 --- src/mainboard/intel/d945gclf/acpi_tables.c | 10 - src/mainboard/intel/d945gclf/dmi.h | 29 --- src/mainboard/iwave/iWRainbowG6/acpi_tables.c | 10 - src/mainboard/iwave/iWRainbowG6/dmi.h | 34 --- src/mainboard/kontron/986lcd-m/acpi_tables.c | 10 - src/mainboard/kontron/986lcd-m/dmi.h | 29 --- src/mainboard/lenovo/t60/acpi_tables.c | 10 - src/mainboard/lenovo/x60/acpi_tables.c | 10 - src/mainboard/roda/rk886ex/acpi_tables.c | 10 - src/mainboard/roda/rk886ex/dmi.h | 29 --- src/mainboard/via/vt8454c/acpi_tables.c | 5 - src/mainboard/via/vt8454c/dmi.h | 29 --- 26 files changed, 594 insertions(+), 302 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 89467db..2cc547a 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -128,6 +128,7 @@ $(obj)/build.h: .xcompile printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_DMI_DATE \"`LANG= date +"%m/%d/%Y"`\"\n" >> $(obj)/build.ht printf "\n" >> $(obj)/build.ht printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.ht diff --git a/src/Kconfig b/src/Kconfig index 7b4f487..f96c903 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -87,7 +87,7 @@ config SCONFIG_GENPARSER help Enable this option if you are working on the sconfig device tree parser and made changes to sconfig.l and - sconfig.y. + sconfig.y. Otherwise, say N. config USE_OPTION_TABLE @@ -304,6 +304,10 @@ config GENERATE_PIRQ_TABLE bool default HAVE_PIRQ_TABLE +config GENERATE_SMBIOS_TABLES + bool + default y + menu "System tables" config WRITE_HIGH_TABLES @@ -342,6 +346,15 @@ config GENERATE_PIRQ_TABLE If unsure, say Y. +config GENERATE_SMBIOS_TABLES + depends on ARCH_X86 + bool "Generate SMBIOS tables" + default y + help + Generate SMBIOS tables for this board. + + If unsure, say Y. + endmenu menu "Payload" diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index d4a377f..3f11c01 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -6,8 +6,10 @@ ramstage-y += tables.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S $(obj)/arch/x86/boot/coreboot_table.ramstage.o : $(OPTION_TABLE_H) +$(obj)/arch/x86/boot/smbios.ramstage.o: $(obj)/build.h diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c new file mode 100644 index 0000000..87eea64 --- /dev/null +++ b/src/arch/x86/boot/smbios.c @@ -0,0 +1,290 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <string.h> +#include <smbios.h> +#include <console/console.h> +#include <build.h> +#include <device/device.h> +#include <arch/cpu.h> +#include <cpu/x86/name.h> +#include <cbfs_core.h> +#include <arch/byteorder.h> + +static u8 smbios_checksum(u8 *p, u32 length) +{ + u8 ret = 0; + while (length--) + ret += *p++; + return -ret; +} + + +int smbios_add_string(char *start, const char *str) +{ + int i = 1; + char *p = start; + + for(;;) { + if (!*p) { + strcpy(p, str); + p += strlen(str); + *p++ = '\0'; + *p++ = '\0'; + return i; + } + + if (!strcmp(p, str)) + return i; + + p += strlen(p)+1; + i++; + } +} + +int smbios_string_table_len(char *start) +{ + char *p = start; + int i, len = 0; + + while(*p) { + i = strlen(p) + 1; + p += i; + len += i; + } + return len + 1; +} + +static int smbios_cpu_vendor(char *start) +{ + char tmp[13]; + u32 *_tmp = (u32 *)tmp; + struct cpuid_result res = cpuid(0); + + _tmp[0] = res.ebx; + _tmp[1] = res.edx; + _tmp[2] = res.ecx; + tmp[12] = '\0'; + return smbios_add_string(start, tmp); + +} + +static int smbios_processor_name(char *start) +{ + char tmp[49]; + u32 *_tmp = (u32 *)tmp; + struct cpuid_result res; + int i; + + for (i = 0; i < 3; i++) { + res = cpuid(0x80000002 + i); + _tmp[i * 4 + 0] = res.eax; + _tmp[i * 4 + 1] = res.ebx; + _tmp[i * 4 + 2] = res.ecx; + _tmp[i * 4 + 3] = res.edx; + } + + tmp[48] = 0; + return smbios_add_string(start, tmp); +} + +static int smbios_write_type0(unsigned long *current, int handle) +{ + struct cbfs_header *hdr; + struct smbios_type0 *t = (struct smbios_type0 *)*current; + int len = sizeof(struct smbios_type0); + + memset(t, 0, sizeof(struct smbios_type0)); + t->type = SMBIOS_BIOS_INFORMATION; + t->handle = handle; + t->length = len - 2; + + t->vendor = smbios_add_string(t->eos, "coreboot"); + t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE); + t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION); + + if ((hdr = get_cbfs_header()) != (struct cbfs_header *)0xffffffff) + t->bios_rom_size = (ntohl(hdr->romsize) / 65535) - 1; + t->system_bios_major_release = 4; + t->bios_characteristics = + BIOS_CHARACTERISTICS_PCI_SUPPORTED | \ + BIOS_CHARACTERISTICS_SELECTABLE_BOOT | \ + BIOS_CHARACTERISTICS_UPGRADEABLE; + +#if CONFIG_GENERATE_ACPI_TABLES + t->bios_characteristics_ext1 = BIOS_EXT1_CHARACTERISTICS_ACPI; +#endif + t->bios_characteristics_ext2 = BIOS_EXT2_CHARACTERISTICS_TARGET; + len = t->length + smbios_string_table_len(t->eos); + *current += len; + return len; +} + +static int smbios_write_type1(unsigned long *current, int handle) +{ + struct smbios_type1 *t = (struct smbios_type1 *)*current; + int len = sizeof(struct smbios_type1); + + memset(t, 0, sizeof(struct smbios_type1)); + t->type = SMBIOS_SYSTEM_INFORMATION; + t->handle = handle; + t->length = len - 2; + t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); + t->product_name = smbios_add_string(t->eos, CONFIG_MAINBOARD_PART_NUMBER); + len = t->length + smbios_string_table_len(t->eos); + *current += len; + return len; +} + +static int smbios_write_type3(unsigned long *current, int handle) +{ + struct smbios_type3 *t = (struct smbios_type3 *)*current; + int len = sizeof(struct smbios_type3); + + memset(t, 0, sizeof(struct smbios_type3)); + t->type = SMBIOS_SYSTEM_ENCLOSURE; + t->handle = handle; + t->length = len - 2; + t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); + t->bootup_state = SMBIOS_STATE_SAFE; + t->power_supply_state = SMBIOS_STATE_SAFE; + t->thermal_state = SMBIOS_STATE_SAFE; + t->_type = 3; + t->security_status = SMBIOS_STATE_SAFE; + len = t->length + smbios_string_table_len(t->eos); + *current += len; + return len; +} + +static int smbios_write_type4(unsigned long *current, int handle) +{ + struct cpuid_result res; + struct smbios_type4 *t = (struct smbios_type4 *)*current; + int len = sizeof(struct smbios_type4); + + res = cpuid(1); + + memset(t, 0, sizeof(struct smbios_type4)); + t->type = SMBIOS_PROCESSOR_INFORMATION; + t->handle = handle; + t->length = len - 2; + t->processor_id[0] = res.eax; + t->processor_id[1] = res.edx; + t->processor_manufacturer = smbios_cpu_vendor(t->eos); + t->processor_version = smbios_processor_name(t->eos); + t->processor_family = 0x0c; + t->processor_type = 3; /* System Processor */ + t->processor_upgrade = 0x06; + t->core_count = (res.ebx >> 16) & 0xff; + t->l1_cache_handle = 0xffff; + t->l2_cache_handle = 0xffff; + t->l3_cache_handle = 0xffff; + t->processor_upgrade = 1; + len = t->length + smbios_string_table_len(t->eos); + *current += len; + return len; +} + +static int smbios_write_type32(unsigned long *current, int handle) +{ + struct smbios_type32 *t = (struct smbios_type32 *)*current; + int len = sizeof(struct smbios_type32); + + memset(t, 0, sizeof(struct smbios_type32)); + t->type = SMBIOS_SYSTEM_BOOT_INFORMATION; + t->handle = handle; + t->length = len - 2; + *current += len; + return len; +} + +static int smbios_write_type127(unsigned long *current, int handle) +{ + struct smbios_type127 *t = (struct smbios_type127 *)*current; + int len = sizeof(struct smbios_type127); + + memset(t, 0, sizeof(struct smbios_type127)); + t->type = SMBIOS_END_OF_TABLE; + t->handle = handle; + t->length = len - 2; + *current += len; + return len; +} + +static int smbios_walk_device_tree(device_t tree, int *handle, unsigned long *current) +{ + device_t dev; + int len = 0; + + for(dev = tree; dev; dev = dev->next) { + printk(BIOS_INFO, "%s (%s)\n", dev_path(dev), dev->chip_ops ? dev->chip_ops->name : ""); + + if (dev->ops && dev->ops->get_smbios_data) + len += dev->ops->get_smbios_data(dev, handle, current); + + if (dev->chip_ops && dev->chip_ops->get_smbios_data) + len += dev->chip_ops->get_smbios_data(dev, handle, current); + } + return len; +} + +unsigned long smbios_write_tables(unsigned long current) +{ + struct smbios_entry *se; + unsigned long tables; + int len, handle = 0; + + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "%s: %08lx\n", __func__, current); + + se = (struct smbios_entry *)current; + current += sizeof(struct smbios_entry); + current = ALIGN(current, 16); + + tables = current; + len = smbios_write_type0(&current, handle++); + len += smbios_write_type1(&current, handle++); + len += smbios_write_type3(&current, handle++); + len += smbios_write_type4(&current, handle++); + len += smbios_write_type32(&current, handle++); + + len += smbios_walk_device_tree(all_devices, &handle, &current); + + len += smbios_write_type127(&current, handle++); + + memset(se, 0, sizeof(struct smbios_entry)); + memcpy(se->anchor, "_SM_", 4); + se->length = sizeof(struct smbios_entry); + se->major_version = 2; + se->minor_version = 7; + se->max_struct_size = 24; + se->struct_count = handle; + memcpy(se->intermediate_anchor_string, "_DMI_", 5); + + se->struct_table_address = (u32)tables; + se->struct_table_length = len; + + se->intermediate_checksum = smbios_checksum((u8 *)se + 0x10, + sizeof(struct smbios_entry) - 0x10); + se->checksum = smbios_checksum((u8 *)se, sizeof(struct smbios_entry)); + return current; +} diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index d816e76..cf207fe 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -31,6 +31,7 @@ #include <cpu/x86/multiboot.h> #include <cbmem.h> #include <lib.h> +#include <smbios.h> uint64_t high_tables_base = 0; uint64_t high_tables_size; @@ -120,7 +121,7 @@ struct lb_memory *write_tables(void) #endif /* CONFIG_GENERATE_MP_TABLE */ #if CONFIG_GENERATE_ACPI_TABLES == 1 -#define MAX_ACPI_SIZE (47 * 1024) +#define MAX_ACPI_SIZE (45 * 1024) post_code(0x9c); /* Write ACPI tables to F segment and high tables area */ @@ -178,7 +179,27 @@ struct lb_memory *write_tables(void) } #endif +#define MAX_SMBIOS_SIZE 2048 +#if CONFIG_GENERATE_SMBIOS_TABLES + high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS, MAX_SMBIOS_SIZE); + if (high_table_pointer) { + unsigned long new_high_table_pointer; + new_high_table_pointer = smbios_write_tables(high_table_pointer); + rom_table_end = ALIGN(rom_table_end, 16); + memcpy((void *)rom_table_end, (void *)high_table_pointer, sizeof(struct smbios_entry)); + + if (new_high_table_pointer > ( high_table_pointer + MAX_SMBIOS_SIZE)) { + printk(BIOS_ERR, "ERROR: Increase SMBIOS size\n"); + } + printk(BIOS_DEBUG, "SMBIOS tables: %ld bytes.\n", + new_high_table_pointer - high_table_pointer); + } else { + unsigned long new_rom_table_end = smbios_write_tables(rom_table_end); + printk(BIOS_DEBUG, "SMBIOS size %ld bytes\n", new_rom_table_end - rom_table_end); + rom_table_end = ALIGN(new_rom_table_end, 16); + } +#endif #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) post_code(0x9d); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index d9ec93c..7c5ec07 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -38,6 +38,7 @@ extern uint64_t high_tables_base, high_tables_size; #define CBMEM_ID_PIRQ 0x49525154 #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_RESUME 0x5245534d +#define CBMEM_ID_SMBIOS 0x534d4254 #define CBMEM_ID_NONE 0x00000000 void cbmem_initialize(void); diff --git a/src/include/device/device.h b/src/include/device/device.h index 42b68f6..53d73cd 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -15,6 +15,7 @@ struct smbus_bus_operations; /* Chip operations */ struct chip_operations { void (*enable_dev)(struct device *dev); + int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current); const char *name; }; @@ -31,6 +32,7 @@ struct device_operations { void (*enable)(device_t dev); void (*set_link)(device_t dev, unsigned int link); void (*reset_bus)(struct bus *bus); + int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current); const struct pci_operations *ops_pci; const struct smbus_bus_operations *ops_smbus_bus; const struct pci_bus_operations *ops_pci_bus; diff --git a/src/include/smbios.h b/src/include/smbios.h new file mode 100644 index 0000000..f13d621 --- /dev/null +++ b/src/include/smbios.h @@ -0,0 +1,197 @@ +#ifndef SMBIOS_H +#define SMBIOS_H + +#include <types.h> + +unsigned long smbios_write_tables(unsigned long start); +int smbios_add_string(char *start, const char *str); +int smbios_string_table_len(char *start); + +#define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) +#define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) +#define BIOS_CHARACTERISTICS_PNP (1 << 9) +#define BIOS_CHARACTERISTICS_APM (1 << 10) +#define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11) +#define BIOS_CHARACTERISTICS_SHADOW (1 << 12) +#define BIOS_CHARACTERISTICS_BOOT_FROM_CD (1 << 15) +#define BIOS_CHARACTERISTICS_SELECTABLE_BOOT (1 << 16) +#define BIOS_CHARACTERISTICS_BIOS_SOCKETED (1 << 17) + +#define BIOS_EXT1_CHARACTERISTICS_ACPI (1 << 0) +#define BIOS_EXT2_CHARACTERISTICS_TARGET (1 << 2) + +#define SMBIOS_STATE_SAFE 3 +typedef enum { + SMBIOS_BIOS_INFORMATION=0, + SMBIOS_SYSTEM_INFORMATION=1, + SMBIOS_SYSTEM_ENCLOSURE=3, + SMBIOS_PROCESSOR_INFORMATION=4, + SMBIOS_CACHE_INFORMATION=7, + SMBIOS_SYSTEM_SLOTS=9, + SMBIOS_PHYS_MEMORY_ARRAY=16, + SMBIOS_MEMORY_DEVICE=17, + SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS=19, + SMBIOS_SYSTEM_BOOT_INFORMATION=32, + SMBIOS_END_OF_TABLE=127, +} smbios_struct_type_t; + +struct smbios_entry { + u8 anchor[4]; + u8 checksum; + u8 length; + u8 major_version; + u8 minor_version; + u16 max_struct_size; + u8 entry_point_rev; + u8 formwatted_area[5]; + u8 intermediate_anchor_string[5]; + u8 intermediate_checksum; + u16 struct_table_length; + u32 struct_table_address; + u16 struct_count; + u8 smbios_bcd_revision; +} __attribute__((packed)); + +struct smbios_type0 { + u8 type; + u8 length; + u16 handle; + u8 vendor; + u8 bios_version; + u16 bios_start_segment; + u8 bios_release_date; + u8 bios_rom_size; + u64 bios_characteristics; + u8 bios_characteristics_ext1; + u8 bios_characteristics_ext2; + u8 system_bios_major_release; + u8 system_bios_minor_release; + u8 ec_major_release; + u8 ec_minor_release; + char eos[2]; +} __attribute__((packed)); + +struct smbios_type1 { + u8 type; + u8 length; + u16 handle; + u8 manufacturer; + u8 product_name; + u8 version; + u8 serial_number; + u8 uuid[16]; + u8 wakeup_type; + u8 sku; + u8 family; + char eos[2]; +} __attribute__((packed)); + +struct smbios_type3 { + u8 type; + u8 length; + u16 handle; + u8 manufacturer; + u8 _type; + u8 version; + u8 serial_number; + u8 asset_tag_number; + u8 bootup_state; + u8 power_supply_state; + u8 thermal_state; + u8 security_status; + u32 oem_defined; + u8 height; + u8 number_of_power_cords; + u8 element_count; + u8 element_record_length; + char eos[2]; +} __attribute__((packed)); + +struct smbios_type4 { + u8 type; + u8 length; + u16 handle; + u8 socket_designation; + u8 processor_type; + u8 processor_family; + u8 processor_manufacturer; + u32 processor_id[2]; + u8 processor_version; + u8 voltage; + u16 external_clock; + u16 max_speed; + u16 current_speed; + u8 status; + u8 processor_upgrade; + u16 l1_cache_handle; + u16 l2_cache_handle; + u16 l3_cache_handle; + u8 serial_number; + u8 asset_tag; + u8 part_number; + u8 core_count; + u8 core_enabled; + u8 thread_count; + u16 processor_characteristics; + u16 processor_family2; + char eos[2]; +} __attribute__((packed)); + +struct smbios_type16 { + u8 type; + u8 length; + u16 handle; + u8 location; + u8 use; + u8 memory_error_correction; + u32 maximum_capacity; + u16 memory_error_information_handle; + u16 number_of_memory_devices; + u64 extended_maximum_capacity; + char eos[2]; +} __attribute__((packed)); + +struct smbios_type17 { + u8 type; + u8 length; + u16 handle; + u16 phys_memory_array_handle; + u16 memory_error_information_handle; + u16 total_width; + u16 data_width; + u16 size; + u8 form_factor; + u8 device_set; + u8 device_locator; + u8 bank_locator; + u8 memory_type; + u16 type_detail; + u16 speed; + u8 manufacturer; + u8 serial_number; + u8 asset_tag; + u8 part_number; + u8 attributes; + u16 extended_size; + u16 clock_speed; + + char eos[2]; +} __attribute__((packed)); + +struct smbios_type32 { + u8 type; + u8 length; + u16 handle; + u8 reserved[6]; + u8 boot_status; + u8 eos[2]; +} __attribute__((packed)); + +struct smbios_type127 { + u8 type; + u8 length; + u16 handle; + u8 eos[2]; +} __attribute__((packed)); + +#endif diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 5417ab8..eecefcd 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -229,6 +229,7 @@ void cbmem_list(void) case CBMEM_ID_PIRQ: printk(BIOS_DEBUG, "IRQ TABLE "); break; case CBMEM_ID_MPTABLE: printk(BIOS_DEBUG, "SMP TABLE "); break; case CBMEM_ID_RESUME: printk(BIOS_DEBUG, "ACPI RESUME"); break; + case CBMEM_ID_SMBIOS: printk(BIOS_DEBUG, "SMBIOS "); break; default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id); } printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base); diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c index 1899648..bdc764d 100644 --- a/src/mainboard/emulation/qemu-x86/northbridge.c +++ b/src/mainboard/emulation/qemu-x86/northbridge.c @@ -9,6 +9,7 @@ #include <bitops.h> #include "chip.h" #include <delay.h> +#include <smbios.h> #if CONFIG_WRITE_HIGH_TABLES==1 #include <cbmem.h> @@ -19,18 +20,24 @@ #define HIGH_RAM_ADDR 0x35 #define LOW_RAM_ADDR 0x34 -static void cpu_pci_domain_set_resources(device_t dev) +static unsigned long qemu_get_memory_size(void) { - u32 pci_tolm = find_pci_tolm(dev->link_list); - unsigned long tomk = 0, tolmk; - int idx; - + unsigned long tomk; outb (HIGH_RAM_ADDR, CMOS_ADDR_PORT); tomk = ((unsigned long) inb(CMOS_DATA_PORT)) << 14; outb (LOW_RAM_ADDR, CMOS_ADDR_PORT); tomk |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6; tomk += 16 * 1024; + return tomk; +} +static void cpu_pci_domain_set_resources(device_t dev) +{ + u32 pci_tolm = find_pci_tolm(dev->link_list); + unsigned long tomk = 0, tolmk; + int idx; + + tomk = qemu_get_memory_size(); printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n", tomk, tomk / 1024); @@ -80,12 +87,64 @@ static void cpu_pci_domain_read_resources(struct device *dev) IORESOURCE_ASSIGNED; } +static int qemu_get_smbios_data16(int handle, unsigned long *current) +{ + struct smbios_type16 *t = (struct smbios_type16 *)*current; + int len = sizeof(struct smbios_type16); + + memset(t, 0, sizeof(struct smbios_type16)); + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->handle = handle; + t->length = len - 2; + t->location = 3; /* Location: System Board */ + t->use = 3; /* System memory */ + t->memory_error_correction = 3; /* No error correction */ + t->maximum_capacity = qemu_get_memory_size(); + *current += len; + return len; +} + +static int qemu_get_smbios_data17(int handle, int parent_handle, unsigned long *current) +{ + struct smbios_type17 *t = (struct smbios_type17 *)*current; + int len; + + memset(t, 0, sizeof(struct smbios_type17)); + t->type = SMBIOS_MEMORY_DEVICE; + t->handle = handle; + t->phys_memory_array_handle = parent_handle; + t->length = sizeof(struct smbios_type17) - 2; + t->size = qemu_get_memory_size() / 1024; + t->data_width = 64; + t->total_width = 64; + t->form_factor = 9; /* DIMM */ + t->device_locator = smbios_add_string(t->eos, "Virtual"); + t->memory_type = 0x12; /* DDR */ + t->type_detail = 0x80; /* Synchronous */ + t->speed = 200; + t->clock_speed = 200; + t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); + len = t->length + smbios_string_table_len(t->eos); + *current += len; + return len; +} + +static int qemu_get_smbios_data(device_t dev, int *handle, unsigned long *current) +{ + int len; + len = qemu_get_smbios_data16(*handle, current); + len += qemu_get_smbios_data17(*handle+1, *handle, current); + *handle += 2; + return len; +} + static struct device_operations pci_domain_ops = { .read_resources = cpu_pci_domain_read_resources, .set_resources = cpu_pci_domain_set_resources, .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, + .get_smbios_data = qemu_get_smbios_data, }; static void enable_dev(struct device *dev) diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index 649dff6..46e7b88 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -29,7 +29,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "dmi.h" extern unsigned char AmlCode[]; @@ -355,15 +354,6 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; -#endif - printk(BIOS_INFO, "ACPI: done.\n"); return current; } diff --git a/src/mainboard/getac/p470/dmi.h b/src/mainboard/getac/p470/dmi.h deleted file mode 100644 index fde4d8a..0000000 --- a/src/mainboard/getac/p470/dmi.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#define DMI_TABLE_SIZE 0x55 - -static const u8 dmi_table[DMI_TABLE_SIZE] = { - 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, - 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, - 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, - 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, - 0x30, 0x30, 0x38, 0x00, 0x00 -}; diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c index 0089e21..dbe1e91 100644 --- a/src/mainboard/ibase/mb899/acpi_tables.c +++ b/src/mainboard/ibase/mb899/acpi_tables.c @@ -28,7 +28,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> -#include "dmi.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -258,15 +257,6 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; -#endif - printk(BIOS_INFO, "ACPI: done.\n"); return current; } diff --git a/src/mainboard/ibase/mb899/dmi.h b/src/mainboard/ibase/mb899/dmi.h deleted file mode 100644 index 96b5873..0000000 --- a/src/mainboard/ibase/mb899/dmi.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define DMI_TABLE_SIZE 0x55 - -static u8 dmi_table[DMI_TABLE_SIZE] = { - 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, - 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, - 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, - 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, - 0x30, 0x30, 0x38, 0x00, 0x00 -}; diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c index bc0a790..f7e13e9 100644 --- a/src/mainboard/intel/d945gclf/acpi_tables.c +++ b/src/mainboard/intel/d945gclf/acpi_tables.c @@ -28,7 +28,6 @@ #include <device/pci_ids.h> #include <cpu/x86/msr.h> #include <arch/ioapic.h> -#include "dmi.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -245,15 +244,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, ssdt); printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; -#endif - printk(BIOS_INFO, "ACPI: done.\n"); return current; } diff --git a/src/mainboard/intel/d945gclf/dmi.h b/src/mainboard/intel/d945gclf/dmi.h deleted file mode 100644 index 96b5873..0000000 --- a/src/mainboard/intel/d945gclf/dmi.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define DMI_TABLE_SIZE 0x55 - -static u8 dmi_table[DMI_TABLE_SIZE] = { - 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, - 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, - 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, - 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, - 0x30, 0x30, 0x38, 0x00, 0x00 -}; diff --git a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c index 92874bc..8c8e788 100644 --- a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c +++ b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c @@ -28,7 +28,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> -#include "dmi.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -264,15 +263,6 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; -#endif - printk(BIOS_INFO, "ACPI: done.\n"); return current; } diff --git a/src/mainboard/iwave/iWRainbowG6/dmi.h b/src/mainboard/iwave/iWRainbowG6/dmi.h deleted file mode 100644 index d076dff..0000000 --- a/src/mainboard/iwave/iWRainbowG6/dmi.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define DMI_TABLE_SIZE 0x55 - -static u8 dmi_table[DMI_TABLE_SIZE] = { - 0x5f, 0x53, 0x4d, 0x5f, 0x2d, 0x1f, 0x02, 0x03, 0x51, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xeb, 0xa8, 0x03, 0xa0, 0xff, 0x0f, 0x00, - 0x01, 0x00, 0x23, 0x00, - 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, - 0xcb, 0x7f, 0x00, 0x00, - 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, - 0x65, 0x6d, 0x73, 0x20, - 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, - 0x31, 0x33, 0x2f, 0x32, - 0x30, 0x30, 0x38, 0x00, 0x00 -}; diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c index 0089e21..dbe1e91 100644 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -28,7 +28,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> -#include "dmi.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -258,15 +257,6 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; -#endif - printk(BIOS_INFO, "ACPI: done.\n"); return current; } diff --git a/src/mainboard/kontron/986lcd-m/dmi.h b/src/mainboard/kontron/986lcd-m/dmi.h deleted file mode 100644 index 96b5873..0000000 --- a/src/mainboard/kontron/986lcd-m/dmi.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define DMI_TABLE_SIZE 0x55 - -static u8 dmi_table[DMI_TABLE_SIZE] = { - 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, - 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, - 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, - 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, - 0x30, 0x30, 0x38, 0x00, 0x00 -}; diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index 3742c20..fa135a6 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -29,7 +29,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "dmi.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -294,15 +293,6 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; -#endif - printk(BIOS_INFO, "ACPI: done.\n"); /* Enable Dummy DCC ON# for DVI */ diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index 3742c20..fa135a6 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -29,7 +29,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "dmi.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -294,15 +293,6 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; -#endif - printk(BIOS_INFO, "ACPI: done.\n"); /* Enable Dummy DCC ON# for DVI */ diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c index 3742c20..fa135a6 100644 --- a/src/mainboard/roda/rk886ex/acpi_tables.c +++ b/src/mainboard/roda/rk886ex/acpi_tables.c @@ -29,7 +29,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "dmi.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -294,15 +293,6 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; -#endif - printk(BIOS_INFO, "ACPI: done.\n"); /* Enable Dummy DCC ON# for DVI */ diff --git a/src/mainboard/roda/rk886ex/dmi.h b/src/mainboard/roda/rk886ex/dmi.h deleted file mode 100644 index 96b5873..0000000 --- a/src/mainboard/roda/rk886ex/dmi.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define DMI_TABLE_SIZE 0x55 - -static u8 dmi_table[DMI_TABLE_SIZE] = { - 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, - 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, - 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, - 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, - 0x30, 0x30, 0x38, 0x00, 0x00 -}; diff --git a/src/mainboard/via/vt8454c/acpi_tables.c b/src/mainboard/via/vt8454c/acpi_tables.c index 434bf87..03bacc3 100644 --- a/src/mainboard/via/vt8454c/acpi_tables.c +++ b/src/mainboard/via/vt8454c/acpi_tables.c @@ -26,7 +26,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "dmi.h" extern const unsigned char AmlCode[]; @@ -194,10 +193,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_create_fadt(fadt, facs, dsdt); acpi_add_table(rsdp, fadt); - - printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); - memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); - printk(BIOS_INFO, "ACPI: done.\n"); return current; } diff --git a/src/mainboard/via/vt8454c/dmi.h b/src/mainboard/via/vt8454c/dmi.h deleted file mode 100644 index 96b5873..0000000 --- a/src/mainboard/via/vt8454c/dmi.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define DMI_TABLE_SIZE 0x55 - -static u8 dmi_table[DMI_TABLE_SIZE] = { - 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, - 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, - 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, - 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, - 0x30, 0x30, 0x38, 0x00, 0x00 -};

1 0

New patch to review: 4cc7400 export get_cbfs_header()
by Sven Schnelle 17 Aug '11

17 Aug '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/157 -gerrit commit 4cc740025729dc0f97d704119d2031c1f47e46bc Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Aug 17 18:10:11 2011 +0200 export get_cbfs_header() Change-Id: I4b6afcee3d0d169e03165a7fb48cfaef2e8253e2 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/include/cbfs_core.h | 1 + src/lib/cbfs_core.c | 2 +- 2 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h index fbe0081..70368f8 100644 --- a/src/include/cbfs_core.h +++ b/src/include/cbfs_core.h @@ -176,5 +176,6 @@ void *cbfs_find_file(const char *name, int type); /* returns 0 on success, -1 on failure */ int cbfs_decompress(int algo, void *src, void *dst, int len); +struct cbfs_header *get_cbfs_header(void); #endif diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 52ba58d..596fa3f 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -55,7 +55,7 @@ /* returns pointer to master header or 0xffffffff if not found */ -static struct cbfs_header *get_cbfs_header(void) +struct cbfs_header *get_cbfs_header(void) { struct cbfs_header *header;

1 0

Patch merged into master: c630800 libpayload: Some more compatibility (for flashrom)
by gerrit＠coreboot.org 17 Aug '11

17 Aug '11

the following patch was just integrated into master: commit c630800f75d9c73def4c36021af7353d4c02d978 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jul 26 12:51:59 2011 +0200 libpayload: Some more compatibility (for flashrom) libpci defines an arbitrary set of PCI vendor IDs, flashrom uses the Intel definition. Add it. flashrom also requires inttypes.h, so add the OpenBSD version Change-Id: I9bffd8193f635c375ac4d6b6eae8d3d876b95f5f Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> See http://review.coreboot.org/154 for details. -gerrit

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ASRock E350M1: enable superio hardware monitor access
by perh52＠runbox.com 17 Aug '11

17 Aug '11

>Thanks for the patch. Should this be done in romstage per mainboard? >Maybe add new CONFIG_SB option instead of overloading the SIO config. > >Kerry, > >Is there already CIMx setup option for this? > > >Thanks, >Marc Thanks for your suggestions Marc. I modified the patch so that it fits in better with existing cimx code. It can now be enabled for each mainboard by setting CONFIG_SB_SUPERIO_HWM_PORT. There is currently only one other mainboard in the tree which has an SB800 and a w83627hf family superio: the Advansus a785e-i. Perhaps someone who has one could test it. Signed-off-by: Per Hansen <perh52(a)runbox.com> diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index e6153c0..2d0e753 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -51,6 +51,11 @@ config AMD_CIMX_SB800 bool default y +config SB_SUPERIO_HWM_PORT + bool + default y + depends on SOUTHBRIDGE_AMD_CIMX_SB800 + config MAINBOARD_DIR string default asrock/e350m1 diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 93e1c31..899801f 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -118,6 +118,7 @@ typedef union _PCI_ADDR { #define cimIrConfigDefault 0x00 // Disable #define cimSpiFastReadEnableDefault 0x01 // Enable #define cimSpiFastReadSpeedDefault 0x01 // 33 MHz +#define cimSioHwmPortEnableDefault FALSE // GPP/AB Controller #define cimNbSbGen2Default TRUE #define cimAlinkPhyPllPowerDownDefault TRUE diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 0a09e11..efc6fe9 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -48,6 +48,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; + sb_config->BuildParameters.SioHwmBaseAddress = SIO_HWM_BASE_ADDRESS; sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; sb_config->BuildParameters.GecShadowRomBase = GEC_BASE_ADDRESS; sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; @@ -92,6 +93,10 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN; sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL; + /* LPC */ + // SuperIO hardware monitor register access + sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM_PORT; + /* * GPP. default configure only enable port0 with 4 lanes, * configure in devicetree.cb would overwrite the default configuration diff --git a/src/vendorcode/amd/cimx/sb800/OEM.h b/src/vendorcode/amd/cimx/sb800/OEM.h index 6ca4271..5b3ac5c 100644 --- a/src/vendorcode/amd/cimx/sb800/OEM.h +++ b/src/vendorcode/amd/cimx/sb800/OEM.h @@ -85,6 +85,14 @@ #endif /** + * SIO_HWM_BASE_ADDRESS - Super IO HWM base address + * + */ +#ifndef SIO_HWM_BASE_ADDRESS + #define SIO_HWM_BASE_ADDRESS 0x290 +#endif + +/** * SPI_BASE_ADDRESS - SPI controller (ROM) base address * */ diff --git a/src/vendorcode/amd/cimx/sb800/SBPOR.c b/src/vendorcode/amd/cimx/sb800/SBPOR.c index 33d09d6..517a353 100644 --- a/src/vendorcode/amd/cimx/sb800/SBPOR.c +++ b/src/vendorcode/amd/cimx/sb800/SBPOR.c @@ -144,6 +144,7 @@ sbPowerOnInit ( UINT8 cimSataMode; UINT8 cimSpiFastReadEnable; UINT8 cimSpiFastReadSpeed; + UINT8 cimSioHwmPortEnable; UINT8 SataPortNum; cimNbSbGen2 = pConfig->NbSbGen2; @@ -155,12 +156,14 @@ sbPowerOnInit ( cimSpiFastReadEnable = cimSpiFastReadEnableDefault; } cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed; + cimSioHwmPortEnable = pConfig->SioHwmPortEnable; #if SB_CIMx_PARAMETER == 0 cimNbSbGen2 = cimNbSbGen2Default; cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default); cimSataMode = (UINT8) ((cimSataMode & 0x0F) | (cimSATARefClkSelDefault + cimSATARefDivSelDefault)); cimSpiFastReadEnable = cimSpiFastReadEnableDefault; cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault; + cimSioHwmPortEnable = cimSioHwmPortEnableDefault; #endif // SB800 Only Enabled (Mmio_mem_enablr) // Default value is correct @@ -200,6 +203,12 @@ sbPowerOnInit ( // Set Build option into SB WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress)); + if ( cimSioHwmPortEnable ) { + // Use Wide IO Port 1 to provide access to the superio HWM registers. + WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG66 , AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioHwmBaseAddress)); + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG48 + 3, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); // Wide IO Port 1: enable + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG74 , AccWidthUint8 | S3_SAVE, 0xFF, BIT2); // set width 0:512, 1:16 bytes + } RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress)); RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1)); // Enabled SMBUS0/SMBUS1 (ASF) Base Address @@ -354,4 +363,4 @@ sbPowerOnInit ( // Set PMx88[5]to enable LdtStp# output to do the C3 or FidVid transation RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8, 0xFF, BIT5); -} \ No newline at end of file +} diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h index ea3e6f6..9ce4490 100644 --- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h +++ b/src/vendorcode/amd/cimx/sb800/SBTYPE.h @@ -156,6 +156,10 @@ typedef struct _BUILDPARAM { * @par * SIO PME BASE Address */ + unsigned int SioHwmBaseAddress; /**< SioHwmBaseAddress + * @par + * SIO HWM BASE Address + */ unsigned int WatchDogTimerBase; /**< WatchDogTimerBase * @par * Watch Dog Timer Address @@ -912,6 +916,8 @@ typedef struct _AMDSBCFG { /** MiscDummy - Reserved */ unsigned int MiscDummy:2; //31:30 + unsigned int SioHwmPortEnable:1; // Enable SuperIO HWM access via LPC + //DebugOptions //offset 4 bytes (146-149) /** PcibAutoClkCtrlLow - Debug function Reserved */ unsigned int PcibAutoClkCtrlLow:16;

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coreboot August 2011