coreboot May 2011

coreboot@coreboot.org

62 participants
161 discussions

[PATCH]add arm toolchain support
by Hamo 25 May '11

25 May '11

This patch added arm toolchain support for coreboot building system. xcompile will find the different toolchain for X86 and ARM architectures and when we decided the target architecture using `make menuconfig` or so, makefile will choose the right toolchain. Signed-off-by: Yang Bai <hamo.by(a)gmail.com> Index: src/Kconfig =================================================================== --- src/Kconfig (revision 6567) +++ src/Kconfig (working copy) @@ -116,10 +116,19 @@ bool default n +# This option is used to set the architecture of a mainboard to ARM. +config ARCH_ARM + bool + default n + if ARCH_X86 source src/arch/x86/Kconfig endif +if ARCH_ARM +source src/arch/arm/Kconfig +endif + menu "Chipset" comment "CPU" Index: src/arch/arm/Kconfig =================================================================== --- src/arch/arm/Kconfig (revision 0) +++ src/arch/arm/Kconfig (revision 0) @@ -0,0 +1,3 @@ +menu "Architecture (ARM)" + +endmenu Index: util/xcompile/xcompile =================================================================== --- util/xcompile/xcompile (revision 6567) +++ util/xcompile/xcompile (working copy) @@ -3,6 +3,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2007-2010 coresystems GmbH +# Copyright (C) 2011 Yang Bai <hamo.by(a)gmail.com> # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -34,20 +35,27 @@ fi done -GCCPREFIX=invalid -TMPFILE=`mktemp /tmp/temp.XXXX 2>/dev/null || echo /tmp/temp.78gOIUGz` -touch $TMPFILE +TWIDTH=32 +for TARCH in i386 littlearm; do -# This should be a loop over all supported architectures -TARCH=i386 -TWIDTH=32 -for gccprefixes in `pwd`/util/crossgcc/xgcc/bin/${TARCH}-elf- ${TARCH}-elf- ""; do + GCCPREFIX=invalid + + if [ ${TARCH} == "i386" ]; then + CARCH=${TARCH}-elf + elif [ ${TARCH} == "littlearm" ]; then + CARCH=arm-none-eabi + fi + + TMPFILE=`mktemp /tmp/temp.XXXX 2>/dev/null || echo /tmp/temp.78gOIUGz` + touch $TMPFILE + + for gccprefixes in `pwd`/util/crossgcc/xgcc/bin/${CARCH}- ${CARCH}- ""; do if ! which ${gccprefixes}as 2>/dev/null >/dev/null; then - continue + continue fi rm -f ${TMPFILE}.o if ${gccprefixes}as -o ${TMPFILE}.o ${TMPFILE}; then - TYPE=`${gccprefixes}objdump -p ${TMPFILE}.o` + TYPE=`${gccprefixes}objdump -p ${TMPFILE}.o | grep "file format"` if [ ${TYPE##* } == "elf${TWIDTH}-${TARCH}" ]; then GCCPREFIX=$gccprefixes ASFLAGS= @@ -56,47 +64,44 @@ break fi fi - if ${gccprefixes}as --32 -o ${TMPFILE}.o ${TMPFILE}; then - TYPE=`${gccprefixes}objdump -p ${TMPFILE}.o` + if [ ${TARCH} == "i386" ]; then + if ${gccprefixes}as --32 -o ${TMPFILE}.o ${TMPFILE}; then + TYPE=`${gccprefixes}objdump -p ${TMPFILE}.o | grep "file format"` if [ ${TYPE##* } == "elf${TWIDTH}-${TARCH}" ]; then - GCCPREFIX=$gccprefixes - ASFLAGS=--32 - CFLAGS="-m32 " - LDFLAGS="-b elf32-i386" - break + GCCPREFIX=$gccprefixes + ASFLAGS=--32 + CFLAGS="-m32 " + LDFLAGS="-b elf32-i386" + break fi + fi fi -done -rm -f $TMPFILE ${TMPFILE}.o + done + rm -f $TMPFILE ${TMPFILE}.o -if [ "$GCCPREFIX" = "invalid" ]; then - echo '$(error no suitable gcc found)' - exit 1 -fi - -CC="${GCCPREFIX}gcc" -testcc "$CC" "$CFLAGS-Wa,--divide " && CFLAGS="$CFLAGS-Wa,--divide " -testcc "$CC" "$CFLAGS-fno-stack-protector " && CFLAGS="$CFLAGS-fno-stack-protector " -testcc "$CC" "$CFLAGS-Wl,--build-id=none " && CFLAGS="$CFLAGS-Wl,--build-id=none " - -if which gcc 2>/dev/null >/dev/null; then - HOSTCC=gcc -else - HOSTCC=cc -fi - -cat << EOF + if [ "$GCCPREFIX" != "invalid" ]; then + CC="${GCCPREFIX}gcc" + testcc "$CC" "$CFLAGS-Wa,--divide " && CFLAGS="$CFLAGS-Wa,--divide " + testcc "$CC" "$CFLAGS-fno-stack-protector " && CFLAGS="$CFLAGS-fno-stack-protector " + testcc "$CC" "$CFLAGS-Wl,--build-id=none " && CFLAGS="$CFLAGS-Wl,--build-id=none " + cat << EOF # elf${TWIDTH}-${TARCH} toolchain -AS:=${GCCPREFIX}as ${ASFLAGS} -CC:=${GCCPREFIX}gcc ${CFLAGS} -AR:=${GCCPREFIX}ar -LD:=${GCCPREFIX}ld ${LDFLAGS} -STRIP:=${GCCPREFIX}strip -NM:=${GCCPREFIX}nm -OBJCOPY:=${GCCPREFIX}objcopy -OBJDUMP:=${GCCPREFIX}objdump - -# native toolchain -HOSTCC:=${HOSTCC} +AS_${TARCH}:=${GCCPREFIX}as ${ASFLAGS} +CC_${TARCH}:=${GCCPREFIX}gcc ${CFLAGS} +AR_${TARCH}:=${GCCPREFIX}ar +LD_${TARCH}:=${GCCPREFIX}ld ${LDFLAGS} +STRIP_${TARCH}:=${GCCPREFIX}strip +NM_${TARCH}:=${GCCPREFIX}nm +OBJCOPY_${TARCH}:=${GCCPREFIX}objcopy +OBJDUMP_${TARCH}:=${GCCPREFIX}objdump EOF + else + cat <<EOF +# elf${TWIDTH}-${TARCH} toolchain +NO_${TARCH}_TOOLCHAIN:=1 +EOF + fi +unset AS CC AR LD STRIP NM OBJCOPY OBJDUMP GCCPREFIX ASFLAGS CFLAGS LDFLAGS CARCH + +done Index: Makefile =================================================================== --- Makefile (revision 6567) +++ Makefile (working copy) @@ -101,7 +101,42 @@ include $(HAVE_DOTCONFIG) +# Set the toolchain variables +# FOR X86 +ifeq ($(CONFIG_ARCH_X86),y) +ifeq ($(NO_i386_TOOLCHAIN),1) +$(error No suitable gcc for X86 found) +else ifneq ($(INNER_SCANBUILD),y) +CC:=$(CC_i386) +endif +AS:=$(AS_i386) +AR:=$(AR_i386) +LD:=$(LD_i386) +STRIP:=$(STRIP_i386) +NM:=$(NM_i386) +OBJCOPY:=$(OBJCOPY_i386) +OBJDUMP:=$(OBJDUMP_i386) +endif +endif + +# FOR ARM +ifeq ($(CONFIG_ARCH_ARM),y) +ifeq ($(NO_littlearm_TOOLCHAIN),1) +$(error No suitable gcc for ARM found) +else +CC:=$(CC_littlearm) +AS:=$(AS_littlearm) +AR:=$(AR_littlearm) +LD:=$(LD_littlearm) +STRIP:=$(STRIP_littlearm) +NM:=$(NM_littlearm) +OBJCOPY:=$(OBJCOPY_littlearm) +OBJDUMP:=$(OBJDUMP_littlearm) +endif +endif + +ifneq ($(INNER_SCANBUILD),y) ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) CC:=clang -m32 HOSTCC:=clang -- """ Keep It Simple,Stupid. """ Chinese Name: 白杨 Nick Name: Hamo Homepage: http://hamobai.com/ GPG KEY ID: 0xA4691A33 Key fingerprint = 09D5 2D78 8E2B 0995 CF8E 4331 33C4 3D24 A469 1A33

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[PATCH 7/7] SuperMicro H8SCM support (mainboard)
by Bao, Zheng 25 May '11

25 May '11

Add support for Supermicro H8scm. It is AMD C32 + SR5650 + SP5100. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>

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Chromebook with coreboot?
by Markus Kübler 25 May '11

25 May '11

Hallo, sorry to bother again. The Google Chromebook is supposed to "takes 8 seconds to boot up and use". The hardware is supposed to be some of the new Atoms. Do they utilize coreboot? If somebody wanted to compete with this, coreboot would be the best approach, wouldn't it? Regards, Markus

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state support of a mainboard at http://geizhals.at/deutschland/?cat=mb1ppga_ddr
by Markus Kübler 25 May '11

25 May '11

Hallo if you have a look at this page here: http://geizhals.at/deutschland/?cat=wlanrout you will notice, that you can filter for "DD-WRT". That means, the model is supported by DD-WRT and not necessarily that it is pre-installed! I was wondering, whether the support of coreboot of a model could be stated here: http://geizhals.at/deutschland/?cat=mb1ppga_ddr Under "Besonderheiten:"="Features" I, as a customer, am highly interested in such a filter. Question is, whether you and they (geizhals) are as well. I highly doubt, the people there are willing to check http://www.coreboot.org/Supported_Motherboards whether a product is already supported once a week... Since I represent neither coreboot (obviously) nor geizhals nor DD-WRT, I have no idea how this flow of information could be managed. But I love the idea of having this filter, right before I buy something. They already filter for UEFI, I'd like to be able to filter for coreboot as well. Oh, http://skinflint.co.uk/?cat=mb1ppga_ddr seems to be their english site. Regards, Markus

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[commit] r6612 - trunk/src/arch/x86/include/arch
by repository service 24 May '11

24 May '11

Author: stepan Date: Tue May 24 00:48:13 2011 New Revision: 6612 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6612 Log: We don't have pausing versions of single-IO instructions. Hence remove the wrong comment. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/arch/x86/include/arch/io.h Modified: trunk/src/arch/x86/include/arch/io.h ============================================================================== --- trunk/src/arch/x86/include/arch/io.h Tue May 24 00:43:43 2011 (r6611) +++ trunk/src/arch/x86/include/arch/io.h Tue May 24 00:48:13 2011 (r6612) @@ -6,8 +6,7 @@ /* * This file contains the definitions for the x86 IO instructions * inb/inw/inl/outb/outw/outl and the "string versions" of the same - * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" - * versions of the single-IO instructions (inb_p/inw_p/..). + * (insb/insw/insl/outsb/outsw/outsl). */ #if defined(__ROMCC__) static inline void outb(uint8_t value, uint16_t port)

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[commit] r6611 - in trunk/src/mainboard: getac/p470 intel/eagleheights iwave/iWRainbowG6
by repository service 24 May '11

24 May '11

Author: stepan Date: Tue May 24 00:43:43 2011 New Revision: 6611 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6611 Log: AP_IN_SIPI_WAIT is already defined in the CPU Kconfig of those boards. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/mainboard/getac/p470/Kconfig trunk/src/mainboard/intel/eagleheights/Kconfig trunk/src/mainboard/iwave/iWRainbowG6/Kconfig Modified: trunk/src/mainboard/getac/p470/Kconfig ============================================================================== --- trunk/src/mainboard/getac/p470/Kconfig Mon May 23 19:55:20 2011 (r6610) +++ trunk/src/mainboard/getac/p470/Kconfig Tue May 24 00:43:43 2011 (r6611) @@ -36,7 +36,6 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_SLIC select MMCONF_SUPPORT - select AP_IN_SIPI_WAIT select UDELAY_LAPIC select HAVE_SMI_HANDLER select BOARD_ROMSIZE_KB_1024 Modified: trunk/src/mainboard/intel/eagleheights/Kconfig ============================================================================== --- trunk/src/mainboard/intel/eagleheights/Kconfig Mon May 23 19:55:20 2011 (r6610) +++ trunk/src/mainboard/intel/eagleheights/Kconfig Tue May 24 00:43:43 2011 (r6611) @@ -16,7 +16,6 @@ select HAVE_MP_TABLE select MMCONF_SUPPORT select UDELAY_TSC - select AP_IN_SIPI_WAIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 Modified: trunk/src/mainboard/iwave/iWRainbowG6/Kconfig ============================================================================== --- trunk/src/mainboard/iwave/iWRainbowG6/Kconfig Mon May 23 19:55:20 2011 (r6610) +++ trunk/src/mainboard/iwave/iWRainbowG6/Kconfig Tue May 24 00:43:43 2011 (r6611) @@ -12,7 +12,6 @@ # select HAVE_MP_TABLE select MMCONF_SUPPORT select USE_PRINTK_IN_CAR - select AP_IN_SIPI_WAIT select UDELAY_LAPIC select HAVE_ACPI_TABLES select HAVE_SMI_HANDLER

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[patch] ck804 mmconf
by Jonathan A. Kollasch 23 May '11

23 May '11

Optionally treat ck804 memory-mapped PCI configuration space window as a resource. Not enabled by default because the resource should be non-posted and there's no way to express that to the resource allocator. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net>

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Asus M2N-E
by Julian Shulika 23 May '11

23 May '11

Hi,everyone. I tried to start Asus M2N-E (Socket AM2,ITE IT8716-F,MCP55,Athlon II 250) with coreboot bios dump,mobo works two-three seconds and turns off. I compiled it with no errors with 512K size (SST 49LF004A) and 1024K (SST 49LF0080A) (Fedora 14,kernel 2.6.35 x86,flashrom 0.9.3, coreboot rev. 6569). I have PCI POST card,but nothing data in it,just *-- *signs instead of 00 or FF. What I can do wrong?

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[Fwd: coreboot at Plumbers Conf?]
by Paul Menzel 23 May '11

23 May '11

Dear coreboot folks, not knowing who would want to travel to the USA or through the USA, I am forwarding Lennart’s message to the list. Stefan, Peter, Ron, Scott, Marc, Rudolf, Sven, Patrick and everyone I forgot, it would be great if some of you could make it and contact Lennart as soon as possible. Thanks, Paul

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[commit] r6608 - trunk/src/southbridge/nvidia/ck804
by repository service 23 May '11

23 May '11

Author: jakllsch Date: Sun May 22 17:39:25 2011 New Revision: 6608 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6608 Log: Ensure ck804 romstrap is 16-byte aligned. This alignment seems to be necessary for the chip to recognize it. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Acked-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Modified: trunk/src/southbridge/nvidia/ck804/romstrap.inc Modified: trunk/src/southbridge/nvidia/ck804/romstrap.inc ============================================================================== --- trunk/src/southbridge/nvidia/ck804/romstrap.inc Sun May 22 00:18:59 2011 (r6607) +++ trunk/src/southbridge/nvidia/ck804/romstrap.inc Sun May 22 17:39:25 2011 (r6608) @@ -21,6 +21,7 @@ .section ".romstrap", "a", @progbits + .align 4 .globl __romstrap_start __romstrap_start: rstables:

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coreboot May 2011