coreboot February 2011

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build service results for r6369
by repository service 16 Feb '11

16 Feb '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stuge" checked in revision 6369 to the coreboot repository. This caused the following changes: Change Log: Fix build errors introduced in r6367 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of asus:a8v-e_deluxe has been fixed Compilation of asus:a8v-e_se has been fixed Compilation of asus:m2v has been fixed Compilation of asus:m2v-mx_se has been fixed Compilation of bcom:winnetp680 has been fixed Compilation of jetway:j7f24 has been fixed Compilation of via:epia-cn has been fixed Compilation of via:pc2500e has been fixed If something broke during this checkin please be a pain in stuge's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r6367
by repository service 16 Feb '11

16 Feb '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stuge" checked in revision 6367 to the coreboot repository. This caused the following changes: Change Log: Extended K8T890 driver to include the K8T800 and K8M800 northbridges The K8T800 is almost identical to the K8T800Pro, also added to this patch. The K8T800_OLD is also defined, which is an older version of the K8T800, but which has no driver and early HT code yet. Also extended the K8M890 VGA driver to work for the K8M800 (not tested). According to the datasheet, the K8T890 and K8T800 are similar enough to be able to use the same initialization code. At least for the K8T800, this is sufficient to have a working HT link with the CPU, and to initialise the V-Link to the southbridge. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of asus:a8v-e_deluxe has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6367&device=a8v-e_deluxe&v… Compilation of asus:a8v-e_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6367&device=a8v-e_se&vendo… Compilation of asus:m2v has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6367&device=m2v&vendor=asu… Compilation of asus:m2v-mx_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6367&device=m2v-mx_se&vend… Compilation of bcom:winnetp680 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6367&device=winnetp680&ven… Compilation of jetway:j7f24 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6367&device=j7f24&vendor=j… Compilation of via:epia-cn has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6367&device=epia-cn&vendor… Compilation of via:pc2500e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6367&device=pc2500e&vendor… If something broke during this checkin please be a pain in stuge's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6369 - in trunk/src/southbridge/via: k8t890 vt8237r
by repository service 16 Feb '11

16 Feb '11

Author: stuge Date: Wed Feb 16 18:40:04 2011 New Revision: 6369 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6369 Log: Fix build errors introduced in r6367 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Added: trunk/src/southbridge/via/k8t890/k8x8xx.h Modified: trunk/src/southbridge/via/vt8237r/lpc.c Added: trunk/src/southbridge/via/k8t890/k8x8xx.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/via/k8t890/k8x8xx.h Wed Feb 16 18:40:04 2011 (r6369) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SOUTHBRIDGE_VIA_K8T890_K8X8XX_H +#define SOUTHBRIDGE_VIA_K8T890_K8X8XX_H + +#include "k8t890.h" + +#endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */ Modified: trunk/src/southbridge/via/vt8237r/lpc.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/lpc.c Wed Feb 16 16:04:59 2011 (r6368) +++ trunk/src/southbridge/via/vt8237r/lpc.c Wed Feb 16 18:40:04 2011 (r6369) @@ -300,7 +300,7 @@ pci_write_config8(dev, 0x48, 0x0c); #else - #if CONFIG_SOUTHBRIDGE_VIA_K8T800 + #if defined(CONFIG_SOUTHBRIDGE_VIA_K8T800) /* It seems that when we pair with the K8T800, we need to disable * the A2 mask */

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build service results for r6368
by repository service 16 Feb '11

16 Feb '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "svens" checked in revision 6368 to the coreboot repository. This caused the following changes: Change Log: Add ACPI code for Lenvo X60 It currently supports: - Sleepbutton - AC state - Battery state - Interrupt routing - Display Brightness control - Hotkeys Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of asus:a8v-e_deluxe is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6368&device=a8v-e_deluxe&v… Compilation of asus:a8v-e_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6368&device=a8v-e_se&vendo… Compilation of asus:m2v is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6368&device=m2v&vendor=asu… Compilation of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6368&device=m2v-mx_se&vend… Compilation of bcom:winnetp680 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6368&device=winnetp680&ven… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6368&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6368&device=epia-cn&vendor… Compilation of via:pc2500e is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6368&device=pc2500e&vendor… If something broke during this checkin please be a pain in svens's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6368 - in trunk/src/mainboard/lenovo/x60: . acpi
by repository service 16 Feb '11

16 Feb '11

Author: svens Date: Wed Feb 16 16:04:59 2011 New Revision: 6368 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6368 Log: Add ACPI code for Lenvo X60 It currently supports: - Sleepbutton - AC state - Battery state - Interrupt routing - Display Brightness control - Hotkeys Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Peter Stuge <peter(a)stuge.se> Added: trunk/src/mainboard/lenovo/x60/acpi/ trunk/src/mainboard/lenovo/x60/acpi/ac.asl trunk/src/mainboard/lenovo/x60/acpi/battery.asl trunk/src/mainboard/lenovo/x60/acpi/beep.asl trunk/src/mainboard/lenovo/x60/acpi/ec.asl trunk/src/mainboard/lenovo/x60/acpi/gpe.asl trunk/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl trunk/src/mainboard/lenovo/x60/acpi/ich7_pci_irqs.asl trunk/src/mainboard/lenovo/x60/acpi/lid.asl trunk/src/mainboard/lenovo/x60/acpi/mainboard.asl trunk/src/mainboard/lenovo/x60/acpi/platform.asl - copied, changed from r6367, trunk/src/mainboard/roda/rk886ex/acpi/platform.asl trunk/src/mainboard/lenovo/x60/acpi/sleepbutton.asl trunk/src/mainboard/lenovo/x60/acpi/superio.asl trunk/src/mainboard/lenovo/x60/acpi/thermal.asl trunk/src/mainboard/lenovo/x60/acpi/video.asl trunk/src/mainboard/lenovo/x60/dsdt.asl - copied unchanged from r6367, trunk/src/mainboard/roda/rk886ex/dsdt.asl Modified: trunk/src/mainboard/lenovo/x60/Kconfig Modified: trunk/src/mainboard/lenovo/x60/Kconfig ============================================================================== --- trunk/src/mainboard/lenovo/x60/Kconfig Wed Feb 16 14:43:00 2011 (r6367) +++ trunk/src/mainboard/lenovo/x60/Kconfig Wed Feb 16 16:04:59 2011 (r6368) @@ -21,6 +21,7 @@ select BOARD_ROMSIZE_KB_2048 select CHANNEL_XOR_RANDOMIZATION select HAVE_SMI_HANDLER + select HAVE_ACPI_TABLES config MAINBOARD_DIR string Added: trunk/src/mainboard/lenovo/x60/acpi/ac.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/lenovo/x60/acpi/ac.asl Wed Feb 16 16:04:59 2011 (r6368) @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x46), + , 4, + HPAC, 1 +} + +Device(AC) +{ + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_PSR, 0, NotSerialized) + { + return (HPAC) + } + + Method(_STA, 0, NotSerialized) + { + Return (0x0f) + } +} Added: trunk/src/mainboard/lenovo/x60/acpi/battery.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/lenovo/x60/acpi/battery.asl Wed Feb 16 16:04:59 2011 (r6368) @@ -0,0 +1,296 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x38), + B0ST, 4, /* Battery 0 state */ + , 1, + B0CH, 1, /* Battery 0 charging */ + B0DI, 1, /* Battery 0 discharging */ + B0PR, 1, /* Battery 0 present */ + Offset (0x39), + B1ST, 4, /* Battery 1 state */ + , 1, + B1CH, 1, /* Battery 1 charging, */ + B1DI, 1, /* Battery 1 discharging,*/ + B1PR, 1 /* Battery 1 present */ +} + +/* EC Registers */ +/* PAGE == 0x00 */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BARC, 16, /* Battery remaining capacity */ + BAFC, 16, /* Battery full charge capacity */ + Offset(0xa8), + BAPR, 16, /* Battery present rate */ + BAVO, 16, /* Battery Voltage */ +} + +/* PAGE == 0x01 */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + , 15, + BAMA, 1, +} + +/* PAGE == 0x02 */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BADC, 16, /* Design Capacity */ + BADV, 16, /* Design voltage */ + , 16, + , 16, + , 16, + BASN, 16, +} + +/* PAGE == 0x04: Battery type */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BATY, 32 +} + + +/* PAGE == 0x05: Battery OEM information */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BAOE, 128 +} + +/* PAGE == 0x06: Battery name */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BANA, 128 +} + +/* Arg0: Battery + * Arg1: Battery Status Package + * Arg2: charging + * Arg3: discharging + */ +Method(BSTA, 4, NotSerialized) +{ + Acquire(ECLK, 0xffff) + Store(0, Local0) + Or(1, Arg0, PAGE) + Store(BAMA, Local1) + Store(Arg0, PAGE) /* Battery dynamic information */ + + Store(BAPR, Local2) + + if (Arg2) // charging + { + Or(2, Local0, Local0) + + If (LGreaterEqual (Local2, 0x8000)) { + Store(0, Local2) + } + } + + if (Arg3) // discharging + { + Or(1, Local0, Local0) + Subtract(0x10000, Local2, Local2) + } + + Store(Local0, Index(Arg1, 0x00)) + + if (Local1) { + Multiply (BARC, 10, Index(Arg1, 2)) + Multiply (Local2, BAVO, Local2) + Divide (Local2, 1000, Local3, Index(Arg1, 1)) + } else { + Store(BARC, Index(Arg1, 2)) + Store(Local2, Index(Arg1, 1)) + } + Store(BAVO, Index(Arg1, 3)) + Release(ECLK) + Return (Arg1) +} + +Method(BINF, 2, NotSerialized) +{ + Acquire(ECLK, 0xffff) + Or(1, Arg1, PAGE) /* Battery 0 static information */ + Xor(BAMA, 1, Index(Arg0, 0)) + Store(BAMA, Local0) + Store(Arg1, PAGE) + Store(BAFC, Local2) + Or(2, Arg1, PAGE) + Store(BADC, Local1) + + if (Local0) + { + Multiply (Local1, 10, Local1) + Multiply (Local2, 10, Local2) + } + + Store(Local1, Index(Arg0, 1)) // Design Capacity + Store(Local2, Index(Arg0, 2)) // Last full charge capacity + Store(BADV, Index(Arg0, 4)) // Design Voltage + Divide (Local2, 20, Local0, Index(Arg0, 5)) // Warning capacity + + Store (BASN, Local0) + Name (SERN, Buffer (0x06) { " " }) + Store (4, Local1) + While (Local0) + { + Divide (Local0, 0x0A, Local2, Local0) + Add (Local2, 48, Index (SERN, Local1)) + Decrement (Local1) + } + Store (SERN, Index (Arg0, 10)) // Serial Number + + Or(4, Arg1, PAGE) + Name (TYPE, Buffer() { 0, 0, 0, 0, 0 }) + Store(BATY, TYPE) + Store(TYPE, Index (Arg0, 11)) // Battery type + Or(5, Arg1, PAGE) + Store(BAOE, Index (Arg0, 12)) // OEM information + Or(6, Arg1, PAGE) + Store(BANA, Index (Arg0, 9)) // Model number + Release(ECLK) + Return (Arg0) +} + +Device (BAT0) +{ + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, 0x00) + Name (_PCL, Package () { \_SB }) + + Name (BATS, Package () + { + 0x00, // 0: PowerUnit: Report in mWh + 0xFFFFFFFF, // 1: Design cap + 0xFFFFFFFF, // 2: Last full charge cap + 0x01, // 3: Battery Technology + 10800, // 4: Design Voltage (mV) + 0x00, // 5: Warning design capacity + 200, // 6: Low design capacity + 1, // 7: granularity1 + 1, // 8: granularity2 + "", // 9: Model number + "", // A: Serial number + "", // B: Battery Type + "" // C: OEM information + }) + + Method (_BIF, 0, NotSerialized) + { + Return (BINF(BATS, 0)) + } + + Name (BATI, Package () + { + 0, // Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // Battery present Rate + 0, // Battery remaining capacity + 0 // Battery present voltage + }) + + Method (_BST, 0, NotSerialized) + { + if (B0PR) { + Return (BSTA(0, BATI, B0CH, B0DI)) + } else { + Return (BATS) + } + } + + Method (_STA, 0, NotSerialized) + { + if (B0PR) { + Return (0x1f) + } else { + Return (0x0f) + } + } +} + +Device (BAT1) +{ + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, 0x00) + Name (_PCL, Package () { \_SB }) + + Name (BATS, Package () + { + 0x00, // 0: PowerUnit: Report in mWh + 0xFFFFFFFF, // 1: Design cap + 0xFFFFFFFF, // 2: Last full charge cap + 0x01, // 3: Battery Technology + 10800, // 4: Design Voltage (mV) + 0x00, // 5: Warning design capacity + 200, // 6: Low design capacity + 1, // 7: granularity1 + 1, // 8: granularity2 + "", // 9: Model number + "", // A: Serial number + "", // B: Battery Type + "" // C: OEM information + }) + + Method (_BIF, 0, NotSerialized) + { + Return (BINF(BATS, 0x10)) + } + + Name (BATI, Package () + { + 0, // Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // Battery present Rate + 0, // Battery remaining capacity + 0 // Battery present voltage + }) + + Method (_BST, 0, NotSerialized) + { + if (B1PR) { + Return (BSTA(0x10, BATI, B1CH, B1DI)) + } else { + Return (BATS) + } + } + + Method (_STA, 0, NotSerialized) + { + if (B1PR) { + Return (0x1f) + } else { + Return (0x0f) + } + } +} Added: trunk/src/mainboard/lenovo/x60/acpi/beep.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/lenovo/x60/acpi/beep.asl Wed Feb 16 16:04:59 2011 (r6368) @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x06), + SNDS, 8 /* Write to this register to generate sound */ + +} + +Method(BEEP, 1, NotSerialized) +{ + Store (Arg0, SNDS) +} Added: trunk/src/mainboard/lenovo/x60/acpi/ec.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/lenovo/x60/acpi/ec.asl Wed Feb 16 16:04:59 2011 (r6368) @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + + Name (_GPE, 28) + Mutex (ECLK, 0) + + OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x05), + HSPA, 1, + Offset (0x0C), + LEDS, 8, /* LED state */ + Offset (0x3B), + , 1, + KBLT, 1, /* Keyboard Light */ + Offset (0x81), + PAGE, 8 /* Information Page Selector */ + } + + Method (_CRS, 0) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 1, 1) + IO (Decode16, 0x66, 0x66, 1, 1) + }) + Return (ECMD) + } + + Method (LED, 1, NotSerialized) + { + Store(Arg0, LEDS) + } + + Method (_INI, 0, NotSerialized) + { + } + + /* Sleep Button pressed */ + Method(_Q13, 0, NotSerialized) + { + Notify(\_SB.PCI0.LPCB.EC.SLPB, 0x80) + } + + /* Brightness up GPE */ + Method(_Q14, 0, NotSerialized) + { + \DSPC.BRTU () + } + + /* Brightness down GPE */ + Method(_Q15, 0, NotSerialized) + { + \DSPC.BRTD() + } + + /* AC status change: present */ + Method(_Q26, 0, NotSerialized) + { + Notify (AC, 0x80) + Beep(6) + } + + /* AC status change: not present */ + Method(_Q27, 0, NotSerialized) + { + Notify (AC, 0x80) + Beep(6) + } + + +#include "ac.asl" +#include "battery.asl" +#include "sleepbutton.asl" +#include "lid.asl" +#include "beep.asl" +} Added: trunk/src/mainboard/lenovo/x60/acpi/gpe.asl ============================================================================== Added: trunk/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl Wed Feb 16 16:04:59 2011 (r6368) @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * i945 + */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA + Package() { 0x001bffff, 1, 0, 0x11 }, // Audio + Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge + Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge + Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge + Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge + Package() { 0x001dffff, 0, 0, 0x10 }, // USB + Package() { 0x001dffff, 1, 0, 0x11 }, // USB + Package() { 0x001dffff, 2, 0, 0x12 }, // USB + Package() { 0x001dffff, 3, 0, 0x13 }, // USB + Package() { 0x001fffff, 0, 0, 0x17 }, // LPC + Package() { 0x001fffff, 1, 0, 0x10 }, // IDE + Package() { 0x001fffff, 2, 0, 0x10 } // SATA + }) + } Else { + Return (Package() { + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA + Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 } // SATA + }) + } +} Added: trunk/src/mainboard/lenovo/x60/acpi/ich7_pci_irqs.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/lenovo/x60/acpi/ich7_pci_irqs.asl Wed Feb 16 16:04:59 2011 (r6368) @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 } + }) + } Else { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 } + }) +} Added: trunk/src/mainboard/lenovo/x60/acpi/lid.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/lenovo/x60/acpi/lid.asl Wed Feb 16 16:04:59 2011 (r6368) @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x46), + , 2, + LIDS , 1 +} + +Device(LID) +{ + Name(_HID, "PNP0C0D") + + Method(_LId, 0, NotSerialized) + { + return (LIDS) + } +} Added: trunk/src/mainboard/lenovo/x60/acpi/mainboard.asl ============================================================================== Copied and modified: trunk/src/mainboard/lenovo/x60/acpi/platform.asl (from r6367, trunk/src/mainboard/roda/rk886ex/acpi/platform.asl) ============================================================================== --- trunk/src/mainboard/roda/rk886ex/acpi/platform.asl Wed Feb 16 14:43:00 2011 (r6367, copy source) +++ trunk/src/mainboard/lenovo/x60/acpi/platform.asl Wed Feb 16 16:04:59 2011 (r6368) @@ -127,8 +127,8 @@ } // Notify the Batteries - Notify(BAT1, 0x80) // Execute BAT1 _BST - Notify(BAT2, 0x80) // Execute BAT2 _BST + Notify(\_SB.PCI0.LPCB.EC.BAT0, 0x80) // Execute BAT1 _BST + Notify(\_SB.PCI0.LPCB.EC.BAT1, 0x80) // Execute BAT2 _BST } /* System Bus */ Added: trunk/src/mainboard/lenovo/x60/acpi/sleepbutton.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/lenovo/x60/acpi/sleepbutton.asl Wed Feb 16 16:04:59 2011 (r6368) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device(SLPB) +{ + Name (_HID, EisaId ("PNP0C0E")) +} Added: trunk/src/mainboard/lenovo/x60/acpi/superio.asl ============================================================================== Added: trunk/src/mainboard/lenovo/x60/acpi/thermal.asl ============================================================================== Added: trunk/src/mainboard/lenovo/x60/acpi/video.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/lenovo/x60/acpi/video.asl Wed Feb 16 16:04:59 2011 (r6368) @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (DSPC) +{ + Name (_ADR, 0x00020001) + OperationRegion (DSPC, PCI_Config, 0x00, 0x100) + Field (DSPC, ByteAcc, NoLock, Preserve) + { + Offset (0xf4), + BRTC, 8 + } + + Method(BRTD, 0, NotSerialized) + { + Store(BRTC, Local0) + if (LGreater (Local0, 15)) + { + Subtract(Local0, 16, Local0) + Store(Local0, BRTC) + } + } + + Method(BRTU, 0, NotSerialized) + { + Store (BRTC, Local0) + if (LLess(Local0, 0xff)) + { + Add (Local0, 16, Local0) + Store(Local0, BRTC) + } + } +} Copied: trunk/src/mainboard/lenovo/x60/dsdt.asl (from r6367, trunk/src/mainboard/roda/rk886ex/dsdt.asl) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/lenovo/x60/dsdt.asl Wed Feb 16 16:04:59 2011 (r6368, copy of r6367, trunk/src/mainboard/roda/rk886ex/dsdt.asl) @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + + // General Purpose Events + #include "acpi/gpe.asl" + + // mainboard specific devices + #include "acpi/mainboard.asl" + + // Thermal Zone + #include "acpi/thermal.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include "../../../northbridge/intel/i945/acpi/i945.asl" + #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + } + } + + /* Chipset specific sleep states */ + #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" +}

1 0

[commit] r6367 - in trunk/src: include/device southbridge/via southbridge/via/k8t890 southbridge/via/vt8237r
by repository service 16 Feb '11

16 Feb '11

Author: stuge Date: Wed Feb 16 14:43:00 2011 New Revision: 6367 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6367 Log: Extended K8T890 driver to include the K8T800 and K8M800 northbridges The K8T800 is almost identical to the K8T800Pro, also added to this patch. The K8T800_OLD is also defined, which is an older version of the K8T800, but which has no driver and early HT code yet. Also extended the K8M890 VGA driver to work for the K8M800 (not tested). According to the datasheet, the K8T890 and K8T800 are similar enough to be able to use the same initialization code. At least for the K8T800, this is sufficient to have a working HT link with the CPU, and to initialise the V-Link to the southbridge. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/include/device/pci_ids.h trunk/src/southbridge/via/Makefile.inc trunk/src/southbridge/via/k8t890/Kconfig trunk/src/southbridge/via/k8t890/bridge.c trunk/src/southbridge/via/k8t890/chrome.c trunk/src/southbridge/via/k8t890/ctrl.c trunk/src/southbridge/via/k8t890/dram.c trunk/src/southbridge/via/k8t890/early_car.c trunk/src/southbridge/via/k8t890/error.c trunk/src/southbridge/via/k8t890/host.c trunk/src/southbridge/via/k8t890/host_ctrl.c trunk/src/southbridge/via/k8t890/k8t890.h trunk/src/southbridge/via/k8t890/romstrap.inc trunk/src/southbridge/via/k8t890/traf_ctrl.c trunk/src/southbridge/via/vt8237r/ctrl.c trunk/src/southbridge/via/vt8237r/lpc.c trunk/src/southbridge/via/vt8237r/vt8237r.c Modified: trunk/src/include/device/pci_ids.h ============================================================================== --- trunk/src/include/device/pci_ids.h Wed Feb 16 14:12:41 2011 (r6366) +++ trunk/src/include/device/pci_ids.h Wed Feb 16 14:43:00 2011 (r6367) @@ -1236,6 +1236,7 @@ #define PCI_DEVICE_ID_VIA_K8M800_5 0x5204 #define PCI_DEVICE_ID_VIA_K8M800_6 0x6204 #define PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR 0x7204 +#define PCI_DEVICE_ID_VIA_K8M800_CHROME 0x3108 #define PCI_DEVICE_ID_VIA_K8T800_AGP 0x3188 #define PCI_DEVICE_ID_VIA_K8T800_BR 0xb188 #define PCI_DEVICE_ID_VIA_K8T890CE_0 0x0238 @@ -1259,6 +1260,7 @@ #define PCI_DEVICE_ID_VIA_K8M890CE_4 0x4336 #define PCI_DEVICE_ID_VIA_K8M890CE_5 0x5336 #define PCI_DEVICE_ID_VIA_K8M890CE_7 0x7336 +#define PCI_DEVICE_ID_VIA_K8M890_CHROME 0x3220 #define PCI_DEVICE_ID_VIA_K8T890CE_PEG 0xa238 #define PCI_DEVICE_ID_VIA_K8T890CE_PEX0 0xc238 #define PCI_DEVICE_ID_VIA_K8T890CE_PEX1 0xd238 Modified: trunk/src/southbridge/via/Makefile.inc ============================================================================== --- trunk/src/southbridge/via/Makefile.inc Wed Feb 16 14:12:41 2011 (r6366) +++ trunk/src/southbridge/via/Makefile.inc Wed Feb 16 14:43:00 2011 (r6367) @@ -1,3 +1,7 @@ +subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD) += k8t890 # lspci lists B188 and 3188 +subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T800) += k8t890 # lspci lists 0282, 1282, 2282, 3282, and 7282 +subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T800PRO) += k8t890 # lspci lists 0282, 1282, 2282, 3282, and 7282 +subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8M800) += k8t890 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T890) += k8t890 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8M890) += k8t890 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8231) += vt8231 Modified: trunk/src/southbridge/via/k8t890/Kconfig ============================================================================== --- trunk/src/southbridge/via/k8t890/Kconfig Wed Feb 16 14:12:41 2011 (r6366) +++ trunk/src/southbridge/via/k8t890/Kconfig Wed Feb 16 14:43:00 2011 (r6367) @@ -1,3 +1,15 @@ +config SOUTHBRIDGE_VIA_K8M800 #K8M800 not tested + bool + +config SOUTHBRIDGE_VIA_K8T800_OLD # not tested + bool + +config SOUTHBRIDGE_VIA_K8T800 + bool + +config SOUTHBRIDGE_VIA_K8T800PRO + bool + config SOUTHBRIDGE_VIA_K8M890 bool @@ -40,5 +52,5 @@ config ID_SECTION_OFFSET hex - default 0x80 if SOUTHBRIDGE_VIA_K8M890 || SOUTHBRIDGE_VIA_K8T890 + default 0x80 if SOUTHBRIDGE_VIA_K8M800 || SOUTHBRIDGE_VIA_K8T800_OLD || SOUTHBRIDGE_VIA_K8T800 || SOUTHBRIDGE_VIA_K8T800PRO || SOUTHBRIDGE_VIA_K8M890 || SOUTHBRIDGE_VIA_K8T890 Modified: trunk/src/southbridge/via/k8t890/bridge.c ============================================================================== --- trunk/src/southbridge/via/k8t890/bridge.c Wed Feb 16 14:12:41 2011 (r6366) +++ trunk/src/southbridge/via/k8t890/bridge.c Wed Feb 16 14:43:00 2011 (r6367) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> - * + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -21,12 +21,13 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <console/console.h> -#include "k8t890.h" +#include "k8x8xx.h" static void bridge_enable(struct device *dev) { u8 tmp; print_debug("B188 device dump\n"); + /* VIA recommends this, sorry no known info. */ writeback(dev, 0x40, 0x91); @@ -63,7 +64,11 @@ .ops_pci = 0, }; -static const struct pci_driver northbridge_driver __pci_driver = { +/* + * K8T890 and K8T800 both use device B188 as the bridge, so no need to + * add a separate driver + */ +static const struct pci_driver northbridge_driver_890 __pci_driver = { .ops = &bridge_ops, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CE_BR, Modified: trunk/src/southbridge/via/k8t890/chrome.c ============================================================================== --- trunk/src/southbridge/via/k8t890/chrome.c Wed Feb 16 14:12:41 2011 (r6366) +++ trunk/src/southbridge/via/k8t890/chrome.c Wed Feb 16 14:43:00 2011 (r6367) @@ -23,7 +23,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <string.h> /* for memset */ -#include "k8t890.h" +#include "k8x8xx.h" #if CONFIG_VGA #include <pc80/vga_io.h> @@ -167,8 +167,14 @@ .enable = 0, }; -static const struct pci_driver unichrome_driver __pci_driver = { +static const struct pci_driver unichrome_driver_800 __pci_driver = { .ops = &chrome_ops, - .vendor = 0x1106, - .device = 0x3230, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M800_CHROME, +}; + +static const struct pci_driver unichrome_driver_890 __pci_driver = { + .ops = &chrome_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M890_CHROME, }; Modified: trunk/src/southbridge/via/k8t890/ctrl.c ============================================================================== --- trunk/src/southbridge/via/k8t890/ctrl.c Wed Feb 16 14:12:41 2011 (r6366) +++ trunk/src/southbridge/via/k8t890/ctrl.c Wed Feb 16 14:43:00 2011 (r6367) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +23,7 @@ #include <device/pci_ops.h> #include <device/pci_ids.h> #include <console/console.h> +#include "k8x8xx.h" /* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1) @@ -32,20 +34,31 @@ u8 regm, regm3; device_t devfun3; - + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); + PCI_DEVICE_ID_VIA_K8T800_DRAM, 0); + + if (!devfun3) + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); if (!devfun3) devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_3, 0); + + if (!devfun3) + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_3, 0); if (!devfun3) devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_3, 0); + + if(!devfun3) + die("\n vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n"); pci_write_config8(dev, 0x70, 0xc2); - + /* PCI Control */ pci_write_config8(dev, 0x72, 0xee); pci_write_config8(dev, 0x73, 0x01); @@ -87,6 +100,7 @@ /* Shadow page F + memhole copy */ regm = pci_read_config8(devfun3, 0x83); pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F)); + } @@ -143,8 +157,10 @@ pci_write_config8(dev, 0x48, 0xa3); } -static void ctrl_init(struct device *dev) { +static void ctrl_init(struct device *dev) +{ + print_debug("K8x8xx: Initializing V-Link to VT8237R sb: "); /* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0] should to 1 */ @@ -161,7 +177,13 @@ if (devsb) { vt8237r_vlink_init(dev); vt8237r_cfg(dev, devsb); + } else { + print_debug("VT8237R LPC not found !\n"); + return; } + print_debug(" Done\n"); + print_debug(" VIA_X_7 device dump:\n"); + dump_south(dev); } @@ -173,19 +195,31 @@ .ops_pci = 0, }; -static const struct pci_driver northbridge_driver_t __pci_driver = { +static const struct pci_driver northbridge_driver_t800 __pci_driver = { + .ops = &ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, +}; + +static const struct pci_driver northbridge_driver_m800 __pci_driver = { + .ops = &ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, +}; + +static const struct pci_driver northbridge_driver_t890 __pci_driver = { .ops = &ctrl_ops, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CE_7, }; -static const struct pci_driver northbridge_driver_tcf __pci_driver = { +static const struct pci_driver northbridge_driver_t890cf __pci_driver = { .ops = &ctrl_ops, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CF_7, }; -static const struct pci_driver northbridge_driver_m __pci_driver = { +static const struct pci_driver northbridge_driver_m890 __pci_driver = { .ops = &ctrl_ops, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8M890CE_7, Modified: trunk/src/southbridge/via/k8t890/dram.c ============================================================================== --- trunk/src/southbridge/via/k8t890/dram.c Wed Feb 16 14:12:41 2011 (r6366) +++ trunk/src/southbridge/via/k8t890/dram.c Wed Feb 16 14:43:00 2011 (r6367) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,7 +26,7 @@ #include <cpu/amd/mtrr.h> #include <pc80/mc146818rtc.h> #include <bitops.h> -#include "k8t890.h" +#include "k8x8xx.h" static void dram_enable(struct device *dev) { @@ -34,9 +35,9 @@ /* * Enable Lowest Interrupt arbitration for APIC, enable NB APIC - * decoding, MSI support,�no SMRAM, compatible SMM. + * decoding, MSI support, no SMRAM, compatible SMM. */ - pci_write_config8(dev, 0x86, 0x39); + pci_write_config8(dev, 0x86, 0x19); /* * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if @@ -64,6 +65,9 @@ /* The Address Next to the Last Valid DRAM Address */ pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); + + print_debug(" VIA_X_3 device dump:\n"); + dump_south(dev); } @@ -110,6 +114,8 @@ k8m890_host_fb_size_get(void) { struct device *dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); + if(!dev) dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_3, 0); unsigned char tmp; @@ -164,19 +170,31 @@ .ops_pci = 0, }; -static const struct pci_driver northbridge_driver_t __pci_driver = { +static const struct pci_driver northbridge_driver_t800 __pci_driver = { + .ops = &dram_ops_t, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_DRAM, +}; + +static const struct pci_driver northbridge_driver_m800 __pci_driver = { + .ops = &dram_ops_m, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M800_DRAM, +}; + +static const struct pci_driver northbridge_driver_t890 __pci_driver = { .ops = &dram_ops_t, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CE_3, }; -static const struct pci_driver northbridge_driver_tcf __pci_driver = { +static const struct pci_driver northbridge_driver_t890cf __pci_driver = { .ops = &dram_ops_t, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CF_3, }; -static const struct pci_driver northbridge_driver_m __pci_driver = { +static const struct pci_driver northbridge_driver_m890 __pci_driver = { .ops = &dram_ops_m, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8M890CE_3, Modified: trunk/src/southbridge/via/k8t890/early_car.c ============================================================================== --- trunk/src/southbridge/via/k8t890/early_car.c Wed Feb 16 14:12:41 2011 (r6366) +++ trunk/src/southbridge/via/k8t890/early_car.c Wed Feb 16 14:43:00 2011 (r6367) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,7 +26,7 @@ #include <stdlib.h> #include <cbmem.h> #include <arch/io.h> -#include "k8t890.h" +#include "k8x8xx.h" /* The 256 bytes of NVRAM for S3 storage, 256B aligned */ #define K8T890_NVRAM_IO_BASE 0xf00 @@ -36,6 +37,8 @@ /* This functions sets KT890 link frequency and width to same values as * it has been setup on K8 side, by AMD NB init. + * This will not work for K8T800_OLD, which has a slightly different + * register arrangement (device 3188) */ u8 k8t890_early_setup_ht(void) @@ -66,7 +69,17 @@ ldtnr = 2; } +#if defined(CONFIG_SOUTHBRIDGE_VIA_K8M800) + print_debug("K8M800 found at LDT "); +#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T800) + print_debug("K8T800 found at LDT "); +#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T800PRO) + print_debug("K8T800 Pro found at LDT "); +#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8M890) + print_debug("K8M890 found at LDT "); +#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T890) print_debug("K8T890 found at LDT "); +#endif print_debug_hex8(ldtnr); /* get the maximum widths for both sides */ Modified: trunk/src/southbridge/via/k8t890/error.c ============================================================================== --- trunk/src/southbridge/via/k8t890/error.c Wed Feb 16 14:12:41 2011 (r6366) +++ trunk/src/southbridge/via/k8t890/error.c Wed Feb 16 14:43:00 2011 (r6367) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,9 +22,11 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <console/console.h> +#include "k8x8xx.h" static void error_enable(struct device *dev) { + print_debug(" K8x8xx: Enabling NB error reporting: "); /* * bit0 - Enable V-link parity error reporting in 0x50 bit0 (RWC) * bit6 - Parity Error/SERR# Report Through V-Link to SB @@ -31,7 +34,11 @@ */ pci_write_config8(dev, 0x58, 0x81); + print_debug("Done\n"); /* TODO: enable AGP errors reporting on K8M890 */ + + print_debug(" VIA_X_1 device dump:\n"); + dump_south(dev); } static const struct device_operations error_ops = { @@ -42,7 +49,19 @@ .ops_pci = 0, }; -static const struct pci_driver northbridge_driver_t __pci_driver = { +static const struct pci_driver northbridge_driver_t800 __pci_driver = { + .ops = &error_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_ERR, +}; + +static const struct pci_driver northbridge_driver_m800 __pci_driver = { + .ops = &error_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M800_ERR, +}; + +static const struct pci_driver northbridge_driver_t890 __pci_driver = { .ops = &error_ops, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CE_1, Modified: trunk/src/southbridge/via/k8t890/host.c ============================================================================== --- trunk/src/southbridge/via/k8t890/host.c Wed Feb 16 14:12:41 2011 (r6366) +++ trunk/src/southbridge/via/k8t890/host.c Wed Feb 16 14:43:00 2011 (r6367) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,13 +23,15 @@ #include <device/pci_ops.h> #include <device/pci_ids.h> #include <console/console.h> -#include "k8t890.h" +#include "k8x8xx.h" static void host_enable(struct device *dev) { /* Multiple function control */ pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01); + print_debug(" VIA_X_0 device dump:\n"); + dump_south(dev); } @@ -70,19 +73,31 @@ .ops_pci = 0, }; -static const struct pci_driver northbridge_driver_t __pci_driver = { +static const struct pci_driver northbridge_driver_t800 __pci_driver = { + .ops = &host_ops_t, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_HT_AGP_CTR, +}; + +static const struct pci_driver northbridge_driver_m800 __pci_driver = { + .ops = &host_ops_m, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M800_HT_AGP_CTR, +}; + +static const struct pci_driver northbridge_driver_t890 __pci_driver = { .ops = &host_ops_t, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CE_0, }; -static const struct pci_driver northbridge_driver_tcf __pci_driver = { +static const struct pci_driver northbridge_driver_t890cf __pci_driver = { .ops = &host_ops_t, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CF_0, }; -static const struct pci_driver northbridge_driver_m __pci_driver = { +static const struct pci_driver northbridge_driver_m890 __pci_driver = { .ops = &host_ops_m, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8M890CE_0, Modified: trunk/src/southbridge/via/k8t890/host_ctrl.c ============================================================================== --- trunk/src/southbridge/via/k8t890/host_ctrl.c Wed Feb 16 14:12:41 2011 (r6366) +++ trunk/src/southbridge/via/k8t890/host_ctrl.c Wed Feb 16 14:43:00 2011 (r6367) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,15 +25,13 @@ #include <console/console.h> #include <cbmem.h> #include <arch/io.h> -#include "k8t890.h" +#include "k8x8xx.h" /* this may be later merged */ /* This fine tunes the HT link settings, which were loaded by ROM strap. */ -static void host_ctrl_enable_k8t890(struct device *dev) +static void host_ctrl_enable_k8t8xx(struct device *dev) { - dump_south(dev); - /* * Bit 4 is reserved but set by AW. Set PCI to HT outstanding * requests to 3. @@ -85,11 +84,12 @@ writeback(dev, 0xc4, 0x50); writeback(dev, 0xc5, 0x50); + print_debug(" VIA_X_2 device dump:\n"); dump_south(dev); } /* This fine tunes the HT link settings, which were loaded by ROM strap. */ -static void host_ctrl_enable_k8m890(struct device *dev) { +static void host_ctrl_enable_k8m8xx(struct device *dev) { /* * Set PCI to HT outstanding requests to 03. @@ -126,7 +126,7 @@ .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = host_ctrl_enable_k8t890, + .enable = host_ctrl_enable_k8t8xx, .ops_pci = 0, }; @@ -134,17 +134,29 @@ .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = host_ctrl_enable_k8m890, + .enable = host_ctrl_enable_k8m8xx, .ops_pci = 0, }; -static const struct pci_driver northbridge_driver_t __pci_driver = { +static const struct pci_driver northbridge_driver_t800 __pci_driver = { + .ops = &host_ctrl_ops_t, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_HOST_CTR, +}; + +static const struct pci_driver northbridge_driver_m800 __pci_driver = { + .ops = &host_ctrl_ops_m, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M800_HOST_CTR, +}; + +static const struct pci_driver northbridge_driver_t890 __pci_driver = { .ops = &host_ctrl_ops_t, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CE_2, }; -static const struct pci_driver northbridge_driver_m __pci_driver = { +static const struct pci_driver northbridge_driver_m890 __pci_driver = { .ops = &host_ctrl_ops_m, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8M890CE_2, Modified: trunk/src/southbridge/via/k8t890/k8t890.h ============================================================================== --- trunk/src/southbridge/via/k8t890/k8t890.h Wed Feb 16 14:12:41 2011 (r6366) +++ trunk/src/southbridge/via/k8t890/k8t890.h Wed Feb 16 14:43:00 2011 (r6367) @@ -41,6 +41,7 @@ #ifdef __PRE_RAM__ u8 k8t890_early_setup_ht(void); +#define k8x8xx_early_setup_ht() k8t890_early_setup_ht() #else #include <device/device.h> #if 0 Modified: trunk/src/southbridge/via/k8t890/romstrap.inc ============================================================================== --- trunk/src/southbridge/via/k8t890/romstrap.inc Wed Feb 16 14:12:41 2011 (r6366) +++ trunk/src/southbridge/via/k8t890/romstrap.inc Wed Feb 16 14:43:00 2011 (r6367) @@ -33,6 +33,27 @@ * Below are some Dev0 Func2 HT control registers values, * depending on strap pin, one of below lines is used. */ +#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 + +tblpointer: +.long 0x50220000, 0X619707C2 +.long 0x50220000, 0X619707C2 +.long 0x50220000, 0X619707C2 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 + +#elif CONFIG_SOUTHBRIDGE_VIA_K8M890 || CONFIG_SOUTHBRIDGE_VIA_K8T890 + tblpointer: .long 0x504400AA, 0x61970FC2 //;200M .long 0x504400AA, 0x61970FC2 //;400M @@ -50,6 +71,7 @@ .long 0x0 .long 0x0 +#endif /* * The pointer to above table should be at 0xffffd, * the table itself MUST be aligned to 128B it seems! Modified: trunk/src/southbridge/via/k8t890/traf_ctrl.c ============================================================================== --- trunk/src/southbridge/via/k8t890/traf_ctrl.c Wed Feb 16 14:12:41 2011 (r6366) +++ trunk/src/southbridge/via/k8t890/traf_ctrl.c Wed Feb 16 14:43:00 2011 (r6367) @@ -138,6 +138,9 @@ .ops_pci = 0, }; +/* K8X800 chipsets have no APIC; no 800 PCI ids here */ + + static const struct pci_driver northbridge_driver_t __pci_driver = { .ops = &traf_ctrl_ops_t, .vendor = PCI_VENDOR_ID_VIA, Modified: trunk/src/southbridge/via/vt8237r/ctrl.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/ctrl.c Wed Feb 16 14:12:41 2011 (r6366) +++ trunk/src/southbridge/via/vt8237r/ctrl.c Wed Feb 16 14:43:00 2011 (r6367) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -32,7 +33,13 @@ device_t devfun3; devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); + PCI_DEVICE_ID_VIA_K8T800_DRAM, 0); + if (!devfun3) + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); + if (!devfun3) + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_3, 0); if (!devfun3) devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_3, 0); @@ -108,7 +115,13 @@ device_t devfun7; devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_7, 0); + PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_7, 0); if (!devfun7) devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_7, 0); @@ -117,7 +130,10 @@ PCI_DEVICE_ID_VIA_K8T890CF_7, 0); /* No pairing NB was found. */ if (!devfun7) + { + print_debug("vt8237s_vlink_init: No pairing NB was found.\n"); return; + } /* * This init code is valid only for the VT8237S! For different @@ -174,7 +190,13 @@ device_t devfun7; devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_7, 0); + PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_7, 0); if (!devfun7) devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_7, 0); @@ -183,7 +205,10 @@ PCI_DEVICE_ID_VIA_K8T890CF_7, 0); /* No pairing NB was found. */ if (!devfun7) + { + print_debug("vt8237a_vlink_init: No pairing NB was found.\n"); return; + } /* * This init code is valid only for the VT8237A! For different Modified: trunk/src/southbridge/via/vt8237r/lpc.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/lpc.c Wed Feb 16 14:12:41 2011 (r6366) +++ trunk/src/southbridge/via/vt8237r/lpc.c Wed Feb 16 14:43:00 2011 (r6367) @@ -299,11 +299,20 @@ */ pci_write_config8(dev, 0x48, 0x0c); #else + + #if CONFIG_SOUTHBRIDGE_VIA_K8T800 + /* It seems that when we pair with the K8T800, we need to disable + * the A2 mask + */ + pci_write_config8(dev, 0x48, 0x0c); + #else /* * Set Read Pass Write Control Enable * (force A2 from APIC FSB to low). */ pci_write_config8(dev, 0x48, 0x8c); + #endif + #endif southbridge_init_common(dev); @@ -319,6 +328,8 @@ #endif printk(BIOS_SPEW, "Leaving %s.\n", __func__); + printk(BIOS_SPEW, "And taking a dump:\n"); + dump_south(dev); } static void vt8237a_init(struct device *dev) @@ -469,6 +480,7 @@ * Bit | Meaning * ------------- * 3 | Bypass APIC De-Assert Message (1=Enable) + * 2 | APIC HyperTransport Mode (1=Enable) * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI" * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) @@ -485,12 +497,13 @@ pci_write_config8(dev, 0x4c, 0x44); /* ROM memory cycles go to LPC. */ - pci_write_config8(dev, 0x59, 0x80); + pci_write_config8(dev, 0x59, 0x80); /* * Bit | Meaning * ------------- * 3 | Bypass APIC De-Assert Message (1=Enable) + * 2 | APIC HyperTransport Mode (1=Enable) * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI" * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) Modified: trunk/src/southbridge/via/vt8237r/vt8237r.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r.c Wed Feb 16 14:12:41 2011 (r6366) +++ trunk/src/southbridge/via/vt8237r/vt8237r.c Wed Feb 16 14:43:00 2011 (r6367) @@ -40,9 +40,9 @@ if (regval != what) { print_debug("Writeback to "); print_debug_hex8(where); - print_debug("failed "); + print_debug(" failed "); print_debug_hex8(regval); - print_debug("\n "); /* TODO: Drop the space? */ + print_debug("\n"); } } #else

1 0

[PATCH] X60: enable SMI handler
by Sven Schnelle 16 Feb '11

16 Feb '11

Hi List, this patch enables SMI Support for the Thinkpad X60. Signed-off-by: Sven Schnelle <svens(a)stackframe.org>

2 1

[commit] r6366 - trunk/src/mainboard/lenovo/x60
by repository service 16 Feb '11

16 Feb '11

Author: stuge Date: Wed Feb 16 14:12:41 2011 New Revision: 6366 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6366 Log: Lenovo ThinkPad X60: Enable SMI handler Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/lenovo/x60/Kconfig trunk/src/mainboard/lenovo/x60/romstage.c Modified: trunk/src/mainboard/lenovo/x60/Kconfig ============================================================================== --- trunk/src/mainboard/lenovo/x60/Kconfig Tue Feb 15 14:07:32 2011 (r6365) +++ trunk/src/mainboard/lenovo/x60/Kconfig Wed Feb 16 14:12:41 2011 (r6366) @@ -20,6 +20,7 @@ select GFXUMA select BOARD_ROMSIZE_KB_2048 select CHANNEL_XOR_RANDOMIZATION + select HAVE_SMI_HANDLER config MAINBOARD_DIR string Modified: trunk/src/mainboard/lenovo/x60/romstage.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/romstage.c Tue Feb 15 14:07:32 2011 (r6365) +++ trunk/src/mainboard/lenovo/x60/romstage.c Wed Feb 16 14:12:41 2011 (r6366) @@ -224,6 +224,14 @@ /* Disable unused devices */ RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD; RCBA32(0x3418) |= (1 << 0); // Required. + + /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ + RCBA32(0x1e84) = 0x00020001; + RCBA32(0x1e80) = 0x0000fe01; + + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA32(0x1e9c) = 0x000200f0; + RCBA32(0x1e98) = 0x000c0801; } static void early_ich7_init(void)

1 0

receiving serial port bytes
by ali hagigat 16 Feb '11

16 Feb '11

I want to capture every single byte of the serial port, ttyS0(or com1) of my Linux (Fedora 12) box . I wonder if anybody knows about a good tool for it. Regards

3 2

Free (possibly recoverable?) Gigabyte GA-MA785GMT-UD2H
by Benjamin Cook 16 Feb '11

16 Feb '11

Hello all, I recently made my first attempt at installing coreboot. I happened to mess up. While trying to jump across the appropriate pins to engage DualBIOS recovery, my jumper slipped and I shorted out. The mainboard is not completely broken. It succeeds at progressing to the point where the backup BIOS engages and tries to rewrite the main BIOS, but the system reboots during the rewrite. I've been speaking with mrnuke on the IRC channel and he mentioned two things: 1) There might be some clever strategy to recover the board, and 2) even if I'm not interested in trying that, someone in the community might be. I am open to either outcome, though I don't have a lot of time to spend on option 1. I am willing to ship at my own expense if someone thinks that they can use this board to further the project. --Ben Cook, aka Canar on IRC.

3 2

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coreboot February 2011