coreboot September 2010

coreboot@coreboot.org

58 participants
324 discussions

Toshiba Satellite U205-S5002
by NOMADICUS 16 Sep '10

16 Sep '10

Hello Corebooters, I was on the #coreboot last night grilling people about what they know of coreboot. I was advised to create some logs for my laptop. It is a Toshiba Satellite u205-S5002. I followed the instructions on http://www.coreboot.org/Laptop#HOWTO_to_find_a_way and I wrote a script to automate the process. The script is mostly working, at least the critical parts of making the scripts. Downloading and installing all the necessary tools, well some of the dependencies are not all sorted out yet. So I suspect that these logs will provide useful information and that someone can give me a clue as to what I should do next. I had a great time learning and I am patient to learn more. The name of the script is 'coreboot.check'.

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SeaBIOS self relocation code
by Kevin O'Connor 16 Sep '10

16 Sep '10

Hi, I completed some code that enables SeaBIOS to relocate itself to high memory. The technique may be of interest to coreboot. The full patch series that enables SeaBIOS relocation can be seen at: http://www.seabios.org/pipermail/seabios/2010-September/000919.html Most of the patch series does cleanups and seabios specific work. The run-time code, which may be of interest to coreboot, is at: http://www.seabios.org/pipermail/seabios/2010-September/000922.html The general idea is to have the build store linker "relocation" information (see _reloc_* symbols) into the final executable, and then have the run-time code use this information so that it can self-modify all code that depends on code position. The SeaBIOS code only relocates part of itself, so the runtime relocation code is slightly more complex. A code blob that was fully relocated would be a little simpler (it would need only one call to updateRelocs). -Kevin

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Unsupported software interrupt #0x42
by Tadas S 15 Sep '10

15 Sep '10

Hello, > 02.238: Calling Option ROM... > 03.227: Unsupported software interrupt #0x42 eax 0x7 > 03.232: int42 call returned error. > 04.804: ... Option ROM returned. > It's coreboot serial output with timestamps. Since I don't know much here, I would like to ask if int0x42 is the same as int0x10 and if we could assume the same handler for both of them to avoid such error? Thanks, Tadas S.

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[PATCH] make I/O APIC IDs and processor APIC IDs unique (asus/m4a785-m)
by Scott Duplichan 15 Sep '10

15 Sep '10

For the AMD SB700 projects, the SB ioapic id is being assigned the same value as one of the processor core local apic ids. Apparently this is not such a serious problem as I had once thought. On the other hand, AMD recommends using a unique value for each apic id. Assigning a unique id to the SB ioapic is not as simple as choosing the next biggest available value, because the ioapic is traditionally a 4-bit value. Though the south bridge has an option for an 8-bit ioapic id, using such a value might confuse older operating systems. Choosing the next available id value for the ioapic works when the number of processor cores is small, and that is what the AMD BKDG recommends. If this would result in an ioapic id that exceeds 4 bits, the recommendation is to lift the processor local apic id numbering so that ioapics can be assigned values starting at zero. The patch below attempts to implement these recommendations. The case of lifting local apic ids has not been tested. In order to meet the 4-bit ioapic id limit without lifting the processor local apic id values, the patch reduces MAX_PHYSICAL_CPUS from 2 to 1, which is consistent with the currently supported boards and processors. The patch is for asus/m4a785-m, but can be adapted for other supported sb700 desktop projects. Tested by booting amd/m4a785-m/seabios to win7 on simnow. The initial and final ioapic id, as well as the value in the acpi apic table, are 8. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Index: src/southbridge/amd/sb700/sb700_sm.c =================================================================== --- src/southbridge/amd/sb700/sb700_sm.c (revision 5814) +++ src/southbridge/amd/sb700/sb700_sm.c (working copy) @@ -57,12 +57,20 @@ printk(BIOS_INFO, "sm_init().\n"); ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */ - /* Don't rename APIC ID */ - /* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8. - * We need to check out why and change back. */ + clear_ioapic(ioapic_base); + /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ + #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) + /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ + setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); + #elif (CONFIG_APIC_ID_OFFSET > 0) + /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ + setup_ioapic(ioapic_base, 0); + #else + #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" + #endif - /* 2.10 Interrupt Routing/Filtering */ + /* 2.10 Interrupt Routing/Filtering */ dword = pci_read_config8(dev, 0x62); dword |= 3; pci_write_config8(dev, 0x62, dword); Index: src/mainboard/asus/m4a785-m/Kconfig =================================================================== --- src/mainboard/asus/m4a785-m/Kconfig (revision 5814) +++ src/mainboard/asus/m4a785-m/Kconfig (working copy) @@ -49,7 +49,7 @@ config MAX_PHYSICAL_CPUS int - default 2 + default 1 config HW_MEM_HOLE_SIZE_AUTO_INC bool Index: src/mainboard/asus/m4a785-m/acpi_tables.c =================================================================== --- src/mainboard/asus/m4a785-m/acpi_tables.c (revision 5814) +++ src/mainboard/asus/m4a785-m/acpi_tables.c (working copy) @@ -70,7 +70,13 @@ current = acpi_create_madt_lapics(current); /* Write SB700 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, + #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) + #define IO_APIC_ID (CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS) + #else + #define IO_APIC_ID 0 + #endif + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + IO_APIC_ID, IO_APIC_ADDR, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)

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Re: [coreboot] Ali m1541
by anders＠jenbo.dk 15 Sep '10

15 Sep '10

Its slot1 old ;) Mvh Anders ----- Reply message ----- Fra: "Luc Verhaegen" <libv(a)skynet.be> Dato: ons., sep. 15, 2010 14:27 Emne: [coreboot] Ali m1541 Til: "Anders Jenbo" <anders(a)jenbo.dk> Cc: "coreboot(a)coreboot.org" <coreboot(a)coreboot.org> On Wed, Sep 15, 2010 at 01:51:37PM +0200, Anders Jenbo wrote: > What is the Lilly hood of porting coreboot to a mb based on the Ali m1541 chipset? > > - Anders How old is that board that you are talking about? My Asus P5A is 12years old, at least, and barely wants to boot still. Maybe ali chipsets are not worth ones time any more. Luc Verhaegen.

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Ali m1541
by Anders Jenbo 15 Sep '10

15 Sep '10

What is the Lilly hood of porting coreboot to a mb based on the Ali m1541 chipset? - Anders

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coreboot and win7
by Scott Duplichan 14 Sep '10

14 Sep '10

I am able to boot Win7 using coreboot+seabios on a couple of AMD SB700 systems. Testing so far is with simnow only. Hopefully someone else can try the changes on a real board. I am still building with UMA disabled and using external PCI video instead, to avoid a payload/acpi table overlap problem. I have tested with Tilapia family 10h and Mahogany family 10h on simnow using Win7 PE edition (see attached). Usually a pass with this setup means real hardware will work, and other Win7 editions will work as well. Here are the changes: 1) Fix BSOD about "this bios is not fully acpi compliant". Windows makes this BSOD because DRAM is reported both by E820 and by SB ACPI _CRS. Also, there is a reference to undefined ACPI object TOM2. Removing the reporting of DRAM from ACPI _CRS solves these problems. 2) SB I/O APIC ID: Coreboot programs ID zero, which conflicts with processor cores. ACPI reports ID 2, which conflicts with processor cores. Win7 reprograms to match ACPI. The conflict seems harmless, at least with simnow testing. I gave the I/O APIC a unique ID just to be sure. 3) PS/2 KB and mouse were missing from ACPI which causes Win7 to ignore them. I added them. Other patches I used, unrelated to Win7: 1) Avoid an essentially infinite PCI bus scan when a bad dev_fn value is passed in from hypertransport.c. It is not clear if this can happen only on simnow. 2) Patch to allow use of gcc 4.5.0. I looked briefly at the Cheetah Win7 BSOD with coreboot+seabios. Win7 sees ACPI SCI_EN is zero, telling it to enable ACPI mode. But SMI_CMD is zero, so it can't enable ACPI mode. The BSOD results. Setting SCI_EN before Win7 launch avoids the BSOD, but causes the animated logo phase to not complete in a reasonable amount of time. I may not debug this one further because the chipset is no longer current. Thanks, Scott

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[PATCH] correct 'Fix for Erratum 343 for AMD Fam10h CPUs'
by Scott Duplichan 14 Sep '10

14 Sep '10

This patch corrects a coding error in the original implementation of 'Erratum 343 for AMD Fam10h CPUs' (rev 4345). The original code sets msr c001_102a bit 3 when bit 35 was intended. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Index: src/cpu/amd/car/cache_as_ram.inc =================================================================== --- src/cpu/amd/car/cache_as_ram.inc (revision 5813) +++ src/cpu/amd/car/cache_as_ram.inc (working copy) @@ -129,8 +129,8 @@ /* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */ rdmsr - /* Set bit 35 to 1 in EAX */ - bts $35, %eax + /* Set bit 35 to 1 in EDX:EAX */ + bts $35-32, %edx /* write back the modified register EDX:EAX to the MSR specified in ECX */ wrmsr

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[commit] r5814 - trunk/src/cpu/amd/car
by repository service 14 Sep '10

14 Sep '10

Author: mjones Date: Tue Sep 14 19:28:41 2010 New Revision: 5814 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5814 Log: This patch corrects a coding error in the original implementation of 'Erratum 343 for AMD Fam10h CPUs' (rev 4345). The original code sets msr c001_102a bit 3 when bit 35 was intended. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/car/cache_as_ram.inc Modified: trunk/src/cpu/amd/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/car/cache_as_ram.inc Mon Sep 13 21:31:21 2010 (r5813) +++ trunk/src/cpu/amd/car/cache_as_ram.inc Tue Sep 14 19:28:41 2010 (r5814) @@ -129,8 +129,8 @@ /* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */ rdmsr - /* Set bit 35 to 1 in EAX */ - bts $35, %eax + /* Set bit 35 to 1 in EAX:EDX */ + bts $35-32, %edx /* write back the modified register EDX:EAX to the MSR specified in ECX */ wrmsr

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flashrom patch: add support for Abit AB-BM6 board
by Tim ter Laak 13 Sep '10

13 Sep '10

Hello all, This patch adds support for the Abit AB-BM6 mainboard to flashrom. The biggest part is a generic function to lower a GPIO line on the PIIX4E southbridge, copied and adapted from its ich_gpio_raise() counterpart (mostly lower instead of raise, followed names from the PIIX4E datasheet). The board specific function then uses this to lower GPO 26. Signed-off-by: Tim ter Laak <timl(a)scintilla.utwente.nl> --- The patch was made from the flashrom subdir, because svn diff from the top-level coreboot dir (as per the directions in the Development Guidelines on the wiki) didn't seem to work for me. Probably because flashrom is fetched externally when checking out coreboot? Anyway, I hope this is okay. If you really prefer a diff from the top-level dir just let me know, and I'll regenerate it with gnu diff. Kind regards, Tim. Index: board_enable.c =================================================================== --- board_enable.c (revision 3559) +++ board_enable.c (working copy) @@ -349,6 +349,58 @@ } /** + * Set the specified GPIO on the specified PIIX4 southbridge to low. + * + * @param name The name of this board. + * @param piix_vendor PCI vendor ID of the specified PIIX4 southbridge. (0x8086) + * @param piix_device PCI device ID of the specified PIIX4 southbridge, function Power Management (0x7113 for PIIX4E) + * @param pmbase_reg PMBASE register offset in the bridge. (0x40 for PIIX4E) + * @param pmbase_mask PMBASE bitmask (0xFFC0) + * @param gporeg Offset of GPOREG register in I/O space, relative to GPIOBASE. (0x34) + * @param gpio_bit The bit (GPIO) which shall be set to low. + * @return If the write-enable was successful return 0, otherwise return -1. + */ +static int piix4_gpio_lower(const char *name, uint16_t piix_vendor, + uint16_t piix_device, uint8_t pmbase_reg, + uint8_t gporeg, uint32_t pmbase_mask, + unsigned int gpio_bit) +{ + struct pci_dev *dev; + uint16_t pmbar; + uint32_t reg32; + + dev = pci_dev_find(piix_vendor, piix_device); /* Intel PIIX4 ACPI function */ + if (!dev) { + fprintf(stderr, "\nERROR: PIIX4 dev %4x:%4x not found.\n", + piix_vendor, piix_device); + return -1; + } + + /* Use PMBASE register to find the I/O space for GPIO. */ + pmbar = pci_read_word(dev, pmbase_reg) & pmbase_mask; + + /* Set specified GPIO to high. */ + reg32 = INL(pmbar + gporeg); + OUTB(0x00, 0xEB); /* dummy write to unused port as delay */ + + reg32 &= ~(1 << gpio_bit); + OUTL(reg32, pmbar + gporeg); + OUTB(0x00, 0xEB); /* another delay */ + + return 0; +} + +/** + * Suited for Abit AB-BM6. + */ +static int piix4_gpio26_lower(const char *name) +{ + return piix4_gpio_lower(name, 0x8086, 0x7113, 0x40, 0x34, 0xffc0, 26); +} + + + +/** * Suited for Acorp 6A815EPD. */ static int board_acorp_6a815epd(const char *name) @@ -672,6 +724,8 @@ NULL, NULL, "GIGABYTE GA-7VT600", board_biostar_p4m80_m4}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI K8T Neo2", w83627thf_gpio4_4_raise_2e}, + {0x8086, 0x7190, 0x0000, 0x0000, 0x8086, 0x7110, 0x0000, 0x0000, + "abit", "ab-bm6", "Abit AB-BM6", piix4_gpio26_lower}, {0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */ };

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coreboot September 2010