coreboot June 2010

coreboot@coreboot.org

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222 discussions

Porting to Asus M4A785-M
by Juhana Helovuo 26 Aug '10

26 Aug '10

Hello, I am trying to get coreboot working on Asus M4A785-M with Athlon II X2 240e CPU (Socket AM3). So far there is no success. The mainboard is based on AMD785G + SB710 chipset, which has integrated ATI VGA. http://www.asus.com/product.aspx?P_ID=ef0qgvMIwOUagAVl&templete=2 The super IO chip is labeled ITE IT8712F-S. Please see the listings at the end of this post for details. There is only pin header connector for COM1 serial port on the mainboard. The back panel DB9 connector with cable to attach to the mainboard must be bought separately. (The one I got has too short cable to reach the PCI slot openings. And it was supposed to be an original Asus part!) The BIOS ROM is Macronix MX25L8005PC-15G, 1 MByte, DIP-8, mounted in a socket. Flashrom 0.9.1 recognizes the chip and is able to read and write it. I have built a small circuit board where I have two BIOS chips and can select between them with a switch. The board is sitting in the BIOS socket. This makes it easier to recover after flashing something non-bootable. I have tried with coreboot revision 5631 from SVN. First, I connected the board via a null-modem cable to another Linux machine, started getty at ttyS0, 115200 bps at the target machine and minicom at the other machine. I get login prompt and can log in via ttyS0, so the serial connection works. Then I tried to build coreboot for ASRock 939A785GMH/128M, since it is based on the same chip set. Flashing succeeds, but booting does not work. Power light comes on, fans start, but otherwise there is no sign of life, nothing on the serial port. Then I noticed that the super IO type is different, make a new directory under src/mainboard/asus for this board type, copy the contents from the ASRock board, and change the references to the super I/O from a Winbond chip to the ITE IT8712F. There seemed to be a some code in the romstage.c that toggled the GPIO pins in the super I/O chip, in function sio_init(). I made a guess that this was something specific to the Winbond chip, so I commented those out. The guess was based on #define -lines after the #include -section. Also I generated a new irq_tables.c with the utility provided with coreboot sources. Now, when attempting to boot, I get the following from the serial port: coreboot-4.0-r5631M Mon Jun 14 04:56:01 EEST 2010 starting... bsp_apicid=0x0 Enabling routing table for node 00 done. Enabling SMP settings coreboot-4.0-r5631M Mon Jun 14 04:56:01 EEST 2010 starting... bsp_apicid=0x0 Enabling routing table for node 00 done. Enabling SMP settings coreboot-4.0-r5631M Mon Jun 14 04:56:01 EEST 2010 starting... bsp_apicid=0x0 Enabling routing table for node 00 done. Enabling SMP settings [...the same repeats...] Now what to do next? The wiki documentation left me wondering what exactly are the necessary steps to port coreboot, provided that all the basic components are already supported. Which board-specific files are needed, and which ones can be auto-generated vs. manually coded? Best regards, Juhana Helovuo $ lspci -tvnn > -[0000:00]-+-00.0 Advanced Micro Devices [AMD] RS780 Host Bridge Alternate [1022:9601] > +-01.0-[0000:01]--+-05.0 ATI Technologies Inc Device [1002:9710] > | \-05.1 ATI Technologies Inc Device [1002:970f] > +-0a.0-[0000:02]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] > +-11.0 ATI Technologies Inc SB700/SB800 SATA Controller [IDE mode] [1002:4390] > +-12.0 ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] > +-12.1 ATI Technologies Inc SB700 USB OHCI1 Controller [1002:4398] > +-12.2 ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] > +-13.0 ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] > +-13.1 ATI Technologies Inc SB700 USB OHCI1 Controller [1002:4398] > +-13.2 ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] > +-14.0 ATI Technologies Inc SBx00 SMBus Controller [1002:4385] > +-14.1 ATI Technologies Inc SB700/SB800 IDE Controller [1002:439c] > +-14.2 ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383] > +-14.3 ATI Technologies Inc SB700/SB800 LPC host controller [1002:439d] > +-14.4-[0000:03]-- > +-14.5 ATI Technologies Inc SB700/SB800 USB OHCI2 Controller [1002:4399] > +-18.0 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] HyperTransport Configuration [1022:1200] > +-18.1 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Address Map [1022:1201] > +-18.2 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] DRAM Controller [1022:1202] > +-18.3 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Miscellaneous Control [1022:1203] > \-18.4 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Link Control [1022:1204] All the PCI(-E) slots are empty. Everything in the above listing is integrated to the mainboard. > # ./superiotool -d > superiotool r5549 > Found ITE IT8712F (id=0x8712, rev=0x8) at 0x2e > Register dump: > idx 20 21 22 23 24 2b > val 87 12 08 00 00 00 > def 87 12 08 00 00 00 > LDN 0x00 (Floppy) > idx 30 60 61 70 74 f0 f1 > val 00 03 f0 06 02 00 00 > def 00 03 f0 06 02 00 00 > LDN 0x01 (COM1) > idx 30 60 61 70 f0 f1 f2 f3 > val 01 03 f8 04 00 50 00 7f > def 00 03 f8 04 00 50 00 7f > LDN 0x02 (COM2) > idx 30 60 61 70 f0 f1 f2 f3 > val 00 02 f8 03 00 50 00 7f > def 00 02 f8 03 00 50 00 7f > LDN 0x03 (Parallel port) > idx 30 60 61 62 63 70 74 f0 > val 01 03 78 00 00 07 04 00 > def 00 03 78 07 78 07 03 03 > LDN 0x04 (Environment controller) > idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 > val 01 02 90 02 30 00 00 00 00 00 00 00 ff > def 00 02 90 02 30 09 00 00 00 00 00 NA NA > LDN 0x05 (Keyboard) > idx 30 60 61 62 63 70 71 f0 > val 01 00 60 00 64 01 02 04 > def 01 00 60 00 64 01 02 08 > LDN 0x06 (Mouse) > idx 30 70 71 f0 > val 01 0c 02 00 > def 00 0c 02 00 > LDN 0x07 (GPIO) > idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd > val c0 23 00 00 00 00 1f 00 00 03 00 00 00 00 01 00 38 00 00 00 00 00 00 00 00 00 00 00 00 00 c0 23 00 00 00 c0 23 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1a 00 00 00 00 00 00 00 > def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 > LDN 0x08 (MIDI port) > idx 30 60 61 70 f0 > val 00 03 00 0a 00 > def 00 03 00 0a 00 > LDN 0x09 (Game port) > idx 30 60 61 > val 00 02 01 > def 00 02 01 > LDN 0x0a (Consumer IR) > idx 30 60 61 70 f0 > val 00 03 10 0b 06 > def 00 03 10 0b 00 >

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filo and usb boot
by Masoud Fatollahy 18 Aug '10

18 Aug '10

Hi, Why is it problem to boot from an usb port when we are using linuxbios and filo. as I can see all usb code are there, what is missing? Thanks, /Masoud

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[patch] DDR3 support of AMD Family 10
by Bao, Zheng 11 Aug '10

11 Aug '10

DDR3 supporting is added. More testing need to be done. But we don't have boards that cover all the options. Features that have been tested. The socket AM3 and ASB2. Single rank and double rank DIMM. Features that need to be tested. Socket C32 and G34, I don't know if it is DDR3. Quad rank. Registered DIMM, which is quite complicated and I am not confident about. The tilapia board is the demo that shows the way to use DDR3. It is quite close to mahogany, except tilapia uses AM3. For a new board, just specify the socket type in Kconfig the devicetree.cb. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>

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ASUS M4A77TD-PRO. First step: buy spare flash chips...
by xdrudis 03 Aug '10

03 Aug '10

Hello. I finally bought the hardware I told you and installed gnewsense 3 with a custom linux-libre 2.6.34 : mainboard Asus M4A77TD-PRO http://www.asus.com/product.aspx?P_ID=0AvsBb7WBZe2i9zK CPU AMD Phenom X4 910e stepping c3 AMD 770 AMD SB710 RAM 2 x 4Gb dual channel non-ECC G.Skill DDR3-1333 PC3 10666 F3-10666CL9D-8GBRL superio ITE IT8712F (clearly marked on the chip and detected) lan: RTL8112L audio VIA VT1708S I've put a graphics card by MSI, Nvidia GeForce 8400GS passively cooled (no fan) on the PCIExpress 2.0 slot. I'll attachs the lspci and superiotool r3125 outputs (versions from gNewSense) and flashrom 0.9.2 downloaded and compiled from release tarball. Btw. The readme in flashrom 0.9.2 says to use make DESTDIR=/usr install if you don't want it in /usr/local, but this will install it in /usr/usr/local/sbin. To have it in /usr/sbin you need to run makePREFIX=/usr install. It's slightly confusing for me, I've had to look at the Makefile. Now, the first thing I want to do is to buy spare flash chips. But I'm not sure what chips or where to buy them. It's a socket with an eight pin chip (DIP-8?) (4 pins per side), roughly 5mm x 9mm I'd say it's by Macronix (and flashrom agrees). But I doubt about the specific model. The motherboard manual says "8Mb Flash ROM". The letters on the chip are very small and there's some marking over them that keeps me from reading them all . I'll copy here what I can read (i mark the most dubious letters with ?). (top left is a logo MX) - - - - -- -- - - = v = = = b09?714 = = = = 25L5???5PC-15G 3C153600 TAIWAN Looking at catalogues from macronix I think 25L is the family (SPI serial flash) 5?? should be the size (I'm not sure how many digits are there, not even 100% sure it's a 5) ?5 would be normal, write protected, duplex,etc. PC might be the process ( xx micrometers), -15 would be frequency of 66 Mhz and G something about lead free or environmental regulations. but flashrom says its a Macronix MX25L8005 . http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Ind… Now, the question is should I buy some MX25L8005 ? (apparently its end of life is 2010-11-30, so it should be available, but where in small quantities ? ) According to http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Ind… maybe I could try Mx25L8006EPI-12G Where do you get your spare EEPROMs ? Thank you.

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#154: Flashing BIOSes from Fujitsu/Siemens is not supported
by coreboot 25 Jul '10

25 Jul '10

#154: Flashing BIOSes from Fujitsu/Siemens is not supported ---------------------------------------+------------------------------------ Reporter: johannesobermayr@… | Owner: carldani Type: enhancement | Status: new Priority: major | Milestone: Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------------+------------------------------------ As summary says I cannot flash BIOSes provided by Fujitsu/Siemens. You can see BIOS architecture from Fujitsu/Siemens if you download for example this BIOS package (for D1326): http://dl- extern3.treiberupdate.de/download2/123525.EXE I also could not find a suitable converter... -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/154> coreboot <http://www.coreboot.org/>

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#134: flashrom crashes acer aspire one laptop
by coreboot 23 Jul '10

23 Jul '10

#134: flashrom crashes acer aspire one laptop -----------------------------------------------------------+---------------- Reporter: Timo Juhani Lindfors <timo.lindfors@…> | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: flashrom | Version: v2 Keywords: aspire laptop | Dependencies: Patchstatus: there is no patch | -----------------------------------------------------------+---------------- I ran the "flashrom" command on my acer aspire one laptop. The display turned black and the system did not respond to even sysrq after that. (Fortunately the system boots after powercycling.) This is debian stable with flashrom package that has version "0.0+r3397-1". -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/134> coreboot <http://www.coreboot.org/>

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[RFC] Network console for coreboot
by Rudolf Marek 16 Jul '10

16 Jul '10

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello all, Maybe this story should be for coreboot blog ;) I have a very short serial cable and therefore I had to always connect the coreboot machine to the notebook which is bit annoying if I use my workstation for development. You may ask how send packets if we have no RAM? Good question so far I know two answers: 1) use some card with internal SRAM I know only one... RTL 8029AS which is a NE 2000 compatible PCI card. It has like 16kb SRAM which is only accessible through PIO. 2) Use some other PCI card with a memory space for packet descriptors, maybe the sideport memory could work - this is just an idea not tested Rest was relatively simple. I took the PCI NE2000 driver from gpxe sources, made it bit more simple (b.c) all routines takes as an argument the IO address of the card. How it works: 1) before uart init call net_init() which just setup the BAR0 on card to IOport 0xe00 enable the IO decoding of the card 2) in uart_tx_byte write the byte to card SRAM 3) after the print is done, construct the packet, with fixed MAC and fixed IP, variable length. The IP payload is UDP packet (src port 6667 dest 6666) The UDP payload is our text which is already there. Thefore invoke the transmit jut to transmit it ;) 4) If the PCI slot with the card is bellow some bridge, then situation does not differ too much. In my case, the first part of the boot is the card on BUS0 but later the PCI slot bus is moved to separate bus (chipset has some bit for this). Because the bridge has subtractive decoding, the output still works regardless of the IO forwarding range. The only problem is if coreboot wants to write new address to BAR0. I solved that by simple hack - I did small PCI driver which just tells coreboot the card has fixed and assigned IO resource. Here is how it looks in linux: 00:13.1 PCI bridge: VIA Technologies, Inc. VT8237A PCI to PCI Bridge (prog-if 01 [Subtractive decode]) Bus: primary=00, secondary=05, subordinate=05, sec-latency=0 I/O behind bridge: 00001000-00001fff Memory behind bridge: f1200000-f12fffff 05:06.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8029(AS) Flags: medium devsel, IRQ 16 I/O ports at 0e00 [size=32] Kernel driver in use: ne2k-pci Kernel modules: ne2k-pci And here how it looks if I catch the output with netcat: $nc -u -l -p 6666 TEST coreboot-4.0-r5577M Sun May 30 20:21:52 CEST 2010 starting... now booting... INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- Issuing SOFT_RESET... soft reset TEST coreboot-4.0-r5577M Sun May 30 20:21:52 CEST 2010 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done <---- snip ----> Post relocation: addr: 0x00000000000eca00 memsz: 0x0000000000013600 filesz: 0x0000000000009a8e using LZMA [ 0x00000000000eca00, 0000000000100000, 0x0000000000100000) <- 00000000fff97c70 dest 000eca00, end 00100000, bouncebuffer 1def0000 Loaded segments Jumping to boot code at fdfae entry = 0x000fdfae lb_start = 0x00100000 lb_size = 0x00080000 adjust = 0x1de70000 buffer = 0x1def0000 elf_boot_notes = 0x00118ab0 adjusted_boot_notes = 0x1df88ab0 It goes allright through the boot. Now some questions: 5) The b.c file is from GPXE project and this particular file is under two Clause BSD license which is compatible with GPL. Can we include this or some other rewrite needs to be done? 6) SMP? I think we will need some locking ? 7) In case you are wondering where to get RTL8029AS pci card. I asked one big czech ISP and they found like 20 of this cards. If some of coreboot developers wants some I can mail it to you with a price of the mail and paypal fee. 8) Someone has free time to fix this patch to something more pretty? Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkwCvaEACgkQ3J9wPJqZRNWngQCePOCPktBDBv2VP4SDSrLxFa/N 44MAoJe+hgnp8ZJicifwfFgnZSkJw+dW =BQN9 -----END PGP SIGNATURE-----

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Re: [coreboot] Mobo Support
by Anders Jenbo 10 Jul '10

10 Jul '10

Ok that is a Hynix chip, no other chips of that bran is currently supported, but the data-sheet is available here: http://www.datasheetcatalog.org/datasheet/hynix/HY29F002TT-55.pdf So it shouldn't be to much trouble to get it working. It is a 256KB 5v PLCC32. I think it is parallel but you should check with the flashrom developers to confirm this. You probably want to desolder it and solder on a PLCC32 socket and get a compatible spare to experiment with, so that you do not brick you board. If you are no skilled with a solder iron i highly recommend paying some one who is. -Anders On Mon 07/06/10 01:16 , David Borg <borg.db(a)gmail.com> wrote: > Hey Anders, thanks for the reply. > Good to hear that progress is being made =] I should have some free > time available in the coming summer holidays, so I'll try to help > out > then. > Regarding the rom chip, I got its number (HY29F002TC-90). I'll > contact > the flashrom developers about support for it. > Cheers, > David > On 7 June 2010 00:20, Anders Jenbo wrote: > > Hallo David > > > > I am currently working on the chip-set that your board uses. So > support is in progress. I have debug console running via serial and i > am about a 1/3 in to getting the ram initialized. If you think you can > help (time is the only real skill required) coding in the support you > are more then welcome. > > > > You should get in contact with the flashrom developers to get > support for your flash chip. Remove the AMI BIOS lable from the rom > chip and read the fist number on the actual chip, should be some thing > similar to these http://www.flashrom.org/Supported_hardware. You can > find the flashrom developers at freenode.net #flashrom, or . > > > > Good luck > > -Anders > > > > > > On Sun 06/06/10 19:17 , David Borg wrote: > > > >> Hey all, I was thinking of trying out coreboot on my old desktop > pc > >> and would like to check whether the motherboard is supported, as > it is > >> not in the list of supported motherboards. > >> System description: > >> Board vendor : GigabyteBoard name : GA-6VX7-4XCPU : Intel Celeron > >> 633MHz > >> Northbridge : VT82C694X > >> (URL: > http://www.datasheetarchive.com/pdf-datasheets/Datasheets-23/DSA-446 > >> 497.pdf[1]) Southbridge : VT82C686A > >> (URL: http://www.charmed.com/PDF/VT82C686A.pdf [2]) > >> > >> The output of lspci -tvnn is attached (lscpi.txt). Note:-0b.0 > >> Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ > [10ec:8139] > >> > >> Links: > >> ------ > >> [1] > >> > http://www.datasheetarchive.com/pdf-datasheets/Datasheets-23/DSA-446497.pdf > >> [2] http://www.charmed.com/PDF/VT82C686A.pdf > >> [3] > >> > http://www.gigabyte.com/products/product-page.aspx?pid=1415&dl=#sp > >> > >> > > ---- Msg sent via @Mail - http://atmail.com/ > > > > ---- Msg sent via @Mail - http://atmail.com/

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Re: [coreboot] PATCH: Fix CMOS Tables support for all boards.
by Myles Watson 08 Jul '10

08 Jul '10

On Thu, Jun 24, 2010 at 7:08 AM, Edwin Beasant <edwin_beasant(a)virtensys.com> wrote: > Re-integrated the “USE_OPTION_TABLE” code so that it will compile for all > boards that define it at configure time. > > Made USE_OPTION_TABLE dependant on HAVE_OPTION_TABLE > > Signed-off-by: Edwin Beasant edwin_beasant(a)virtensys.com I updated your patch to: - Have a default value for USE_OPTION_TABLE even when HAVE_OPTION_TABLE isn't defined - Pass abuild with USE_OPTION_TABLE defaulting to y or n use_options.diff: Your patch, slightly modified options_fixup.diff: Fix boards to include the .h file instead of the .c file have_option_polarity.diff: Default to no cmos.layout file so it can be selected (like most other options) Patch for testing with USE_OPTION_TABLE defaulting to y use_option_default.diff I think it would make sense to default to using the option table if it is present. A next step might be to remove the "default" parameter from read_option and make it get the default from option_table.h. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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coreboot on Dell c600
by palito＠o2.pl 30 Jun '10

30 Jun '10

Did any progress was made in the matter of coreboot on laptops and with Dell C600 Latitude? As I am googling the net and the mailing list I see that my chipset is supported but still I am bit afraid to flash it with coreboot. Any suggestion except mounting a socket for changeable chips?

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coreboot June 2010