coreboot March 2010

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build service results for r5308
by coreboot information 28 Mar '10

28 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5308 to the coreboot repository. This caused the following changes: Change Log: drop post_code() Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of msi:ms9652_fam10 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r5307
by coreboot information 28 Mar '10

28 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5307 to the coreboot repository. This caused the following changes: Change Log: drop unneeded __ROMCC__ checks when the check for __PRE_RAM__ is more appropriate. Also, factor out post_code() for __PRE_RAM__ code and drop it from some mainboards. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of asus:a8n_e has been fixed Compilation of asus:p2b-f has been fixed Compilation of asus:p2b-ls has been fixed Compilation of asus:p3b-f has been fixed Compilation of msi:ms9652_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5307&device=ms9652_fam10&v… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5308 - trunk/src/mainboard/msi/ms9652_fam10
by repository service 28 Mar '10

28 Mar '10

Author: stepan Date: Sun Mar 28 23:30:23 2010 New Revision: 5308 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5308 Log: drop post_code() Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Sun Mar 28 23:26:54 2010 (r5307) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Sun Mar 28 23:30:23 2010 (r5308) @@ -49,11 +49,6 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" - -static void post_code(u8 value) { - outb(value, 0x80); -} - #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"

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[commit] r5307 - in trunk/src: arch/i386/include/arch arch/i386/lib include include/cpu/amd include/cpu/x86 mainboard/amd/mahogany_fam10 mainboard/amd/serengeti_cheetah_fam10 mainboard/dell/s1850 m...
by repository service 28 Mar '10

28 Mar '10

Author: stepan Date: Sun Mar 28 23:26:54 2010 New Revision: 5307 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5307 Log: drop unneeded __ROMCC__ checks when the check for __PRE_RAM__ is more appropriate. Also, factor out post_code() for __PRE_RAM__ code and drop it from some mainboards. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/arch/i386/include/arch/cpu.h trunk/src/arch/i386/include/arch/hlt.h trunk/src/arch/i386/include/arch/io.h trunk/src/arch/i386/lib/console.c trunk/src/arch/i386/lib/console_print.c trunk/src/include/cpu/amd/dualcore.h trunk/src/include/cpu/amd/mtrr.h trunk/src/include/cpu/amd/quadcore.h trunk/src/include/cpu/x86/cache.h trunk/src/include/cpu/x86/lapic.h trunk/src/include/cpu/x86/msr.h trunk/src/include/cpu/x86/mtrr.h trunk/src/include/cpu/x86/tsc.h trunk/src/include/stdlib.h trunk/src/include/string.h trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/dell/s1850/reset.c trunk/src/mainboard/intel/eagleheights/reset.c trunk/src/mainboard/intel/jarrell/reset.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/supermicro/x6dai_g/reset.c trunk/src/mainboard/supermicro/x6dhe_g/reset.c trunk/src/mainboard/supermicro/x6dhe_g2/reset.c trunk/src/mainboard/supermicro/x6dhr_ig/reset.c trunk/src/mainboard/supermicro/x6dhr_ig2/reset.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/northbridge/via/cn400/cn400.h trunk/src/northbridge/via/cn700/cn700.h trunk/src/northbridge/via/vx800/vx800.h Modified: trunk/src/arch/i386/include/arch/cpu.h ============================================================================== --- trunk/src/arch/i386/include/arch/cpu.h Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/arch/i386/include/arch/cpu.h Sun Mar 28 23:26:54 2010 (r5307) @@ -104,7 +104,7 @@ #define X86_VENDOR_SIS 10 #define X86_VENDOR_UNKNOWN 0xff -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) && defined( __GNUC__) +#if !defined(__PRE_RAM__) #include <device/device.h> Modified: trunk/src/arch/i386/include/arch/hlt.h ============================================================================== --- trunk/src/arch/i386/include/arch/hlt.h Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/arch/i386/include/arch/hlt.h Sun Mar 28 23:26:54 2010 (r5307) @@ -1,7 +1,7 @@ #ifndef ARCH_HLT_H #define ARCH_HLT_H -#if defined( __ROMCC__) && !defined(__PRE_RAM__) && !defined(__GNUC__) +#if defined(__ROMCC__) static void hlt(void) { __builtin_hlt(); Modified: trunk/src/arch/i386/include/arch/io.h ============================================================================== --- trunk/src/arch/i386/include/arch/io.h Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/arch/i386/include/arch/io.h Sun Mar 28 23:26:54 2010 (r5307) @@ -9,7 +9,7 @@ * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" * versions of the single-IO instructions (inb_p/inw_p/..). */ -#if defined( __ROMCC__ ) && !defined (__GNUC__) +#if defined(__ROMCC__) static inline void outb(uint8_t value, uint16_t port) { __builtin_outb(value, port); @@ -42,7 +42,6 @@ return __builtin_inl(port); } #else - static inline void outb(uint8_t value, uint16_t port) { __asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port)); @@ -78,8 +77,7 @@ __asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port)); return value; } - -#endif /* __ROMCC__ && !__GNUC__*/ +#endif /* __ROMCC__ */ static inline void outsb(uint16_t port, const void *addr, unsigned long count) { @@ -136,6 +134,7 @@ ); } +#if 0 /* XXX XXX XXX This is a story from the evil API from hell XXX XXX XXX * We have different functions for memory access in pre-ram stage and ram * stage. Those in pre-ram stage are called write32 and expect the address @@ -173,6 +172,7 @@ { return *(volatile uint32_t *) addr; } +#endif #if !defined(__PRE_RAM__) static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr) Modified: trunk/src/arch/i386/lib/console.c ============================================================================== --- trunk/src/arch/i386/lib/console.c Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/arch/i386/lib/console.c Sun Mar 28 23:26:54 2010 (r5307) @@ -19,6 +19,19 @@ print_info(console_test); } + +void post_code(u8 value) +{ +#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0 +#if CONFIG_SERIAL_POST==1 + print_emerg("POST: 0x"); + print_emerg_hex8(value); + print_emerg("\r\n"); +#endif + outb(value, 0x80); +#endif +} + void die(const char *str) { print_emerg(str); Modified: trunk/src/arch/i386/lib/console_print.c ============================================================================== --- trunk/src/arch/i386/lib/console_print.c Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/arch/i386/lib/console_print.c Sun Mar 28 23:26:54 2010 (r5307) @@ -62,10 +62,6 @@ } } -/* Actually this should say defined(__ROMCC__) but that define is explicitly - * set in some romstage.c files to trigger the simple device_t version to be used. - * So __GNUCC__ does the right thing here. - */ #if defined (__ROMCC__) #define STATIC #else Modified: trunk/src/include/cpu/amd/dualcore.h ============================================================================== --- trunk/src/include/cpu/amd/dualcore.h Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/include/cpu/amd/dualcore.h Sun Mar 28 23:26:54 2010 (r5307) @@ -15,7 +15,7 @@ struct node_core_id get_node_core_id(unsigned int nb_cfg_54); #endif -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) struct device; unsigned get_apicid_base(unsigned ioapic_num); void amd_sibling_init(struct device *cpu); Modified: trunk/src/include/cpu/amd/mtrr.h ============================================================================== --- trunk/src/include/cpu/amd/mtrr.h Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/include/cpu/amd/mtrr.h Sun Mar 28 23:26:54 2010 (r5307) @@ -31,8 +31,8 @@ #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) -#if !defined( __ROMCC__ ) && !defined (ASSEMBLY) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) && !defined(ASSEMBLY) void amd_setup_mtrrs(void); -#endif /* __ROMCC__ */ +#endif #endif /* CPU_AMD_MTRR_H */ Modified: trunk/src/include/cpu/amd/quadcore.h ============================================================================== --- trunk/src/include/cpu/amd/quadcore.h Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/include/cpu/amd/quadcore.h Sun Mar 28 23:26:54 2010 (r5307) @@ -34,7 +34,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54); #endif -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) struct device; u32 get_apicid_base(u32 ioapic_num); void amd_sibling_init(struct device *cpu); Modified: trunk/src/include/cpu/x86/cache.h ============================================================================== --- trunk/src/include/cpu/x86/cache.h Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/include/cpu/x86/cache.h Sun Mar 28 23:26:54 2010 (r5307) @@ -41,8 +41,8 @@ wbinvd(); } -#if !defined( __ROMCC__) && !defined(__PRE_RAM__) && defined (__GNUC__) +#if !defined(__PRE_RAM__) void x86_enable_cache(void); -#endif /* !__ROMCC__ */ +#endif #endif /* CPU_X86_CACHE */ Modified: trunk/src/include/cpu/x86/lapic.h ============================================================================== --- trunk/src/include/cpu/x86/lapic.h Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/include/cpu/x86/lapic.h Sun Mar 28 23:26:54 2010 (r5307) @@ -69,7 +69,7 @@ void stop_this_cpu(void); #endif -#if ! defined (__ROMCC__) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr)))) @@ -106,7 +106,6 @@ return x; } - static inline void lapic_write_atomic(unsigned long reg, unsigned long v) { xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg), v); @@ -150,14 +149,11 @@ void setup_lapic(void); - #if CONFIG_SMP == 1 struct device; int start_cpu(struct device *cpu); - #endif /* CONFIG_SMP */ - -#endif /* !__ROMCC__ && !__PRE_RAM__ */ +#endif /* !__PRE_RAM__ */ #endif /* CPU_X86_LAPIC_H */ Modified: trunk/src/include/cpu/x86/msr.h ============================================================================== --- trunk/src/include/cpu/x86/msr.h Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/include/cpu/x86/msr.h Sun Mar 28 23:26:54 2010 (r5307) @@ -1,7 +1,7 @@ #ifndef CPU_X86_MSR_H #define CPU_X86_MSR_H -#if defined( __ROMCC__) +#if defined(__ROMCC__) typedef __builtin_msr_t msr_t; @@ -45,5 +45,4 @@ #endif /* __ROMCC__ */ - #endif /* CPU_X86_MSR_H */ Modified: trunk/src/include/cpu/x86/mtrr.h ============================================================================== --- trunk/src/include/cpu/x86/mtrr.h Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/include/cpu/x86/mtrr.h Sun Mar 28 23:26:54 2010 (r5307) @@ -32,18 +32,15 @@ #define MTRRfix4K_F8000_MSR 0x26f -#if !defined(__ROMCC__) && !defined (ASSEMBLY) && !defined(__PRE_RAM__) - +#if !defined (ASSEMBLY) && !defined(__PRE_RAM__) #include <device/device.h> - void enable_fixed_mtrr(void); void x86_setup_var_mtrrs(unsigned address_bits); void x86_setup_mtrrs(unsigned address_bits); int x86_mtrr_check(void); void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res); void x86_setup_fixed_mtrrs(void); - -#endif /* __ROMCC__ */ +#endif #endif /* CPU_X86_MTRR_H */ Modified: trunk/src/include/cpu/x86/tsc.h ============================================================================== --- trunk/src/include/cpu/x86/tsc.h Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/include/cpu/x86/tsc.h Sun Mar 28 23:26:54 2010 (r5307) @@ -17,7 +17,8 @@ return res; } -#if !defined( __ROMCC__ ) && !defined (__PRE_RAM__) +#if !defined(__ROMCC__) +/* Too many registers for ROMCC */ static inline unsigned long long rdtscll(void) { unsigned long long val; Modified: trunk/src/include/stdlib.h ============================================================================== --- trunk/src/include/stdlib.h Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/include/stdlib.h Sun Mar 28 23:26:54 2010 (r5307) @@ -11,7 +11,7 @@ #define MIN(a,b) ((a) < (b) ? (a) : (b)) #define MAX(a,b) ((a) > (b) ? (a) : (b)) -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) void *malloc(size_t size); void free(void *ptr); #endif Modified: trunk/src/include/string.h ============================================================================== --- trunk/src/include/string.h Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/include/string.h Sun Mar 28 23:26:54 2010 (r5307) @@ -8,7 +8,7 @@ void *memmove(void *dest, const void *src, size_t n); void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) int sprintf(char * buf, const char *fmt, ...); #endif @@ -41,7 +41,7 @@ return 0; } -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) static inline char *strdup(const char *s) { size_t sz = strlen(s) + 1; Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Sun Mar 28 23:26:54 2010 (r5307) @@ -52,12 +52,6 @@ #include <cpu/x86/lapic.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" - -/* FIXME: Use console.c post_code function */ -static void post_code(u8 value) { - outb(value, 0x80); -} - #include "arch/i386/lib/console.c" #include "pc80/serial.c" #include "lib/ramtest.c" Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Sun Mar 28 23:26:54 2010 (r5307) @@ -52,12 +52,6 @@ #include <cpu/x86/lapic.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" - -/* FIXME: Use console.c post_code function */ -static void post_code(u8 value) { - outb(value, 0x80); -} - #include "arch/i386/lib/console.c" #include "pc80/serial.c" #include "lib/ramtest.c" Modified: trunk/src/mainboard/dell/s1850/reset.c ============================================================================== --- trunk/src/mainboard/dell/s1850/reset.c Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/mainboard/dell/s1850/reset.c Sun Mar 28 23:26:54 2010 (r5307) @@ -1,18 +1,6 @@ #include <arch/io.h> #include <reset.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#if !defined (__ROMCC__) && !defined (__PRE_RAM__) -#include <device/pci.h> -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) -#define PCI_DEV_INVALID 0 - -static inline device_t pci_locate_device(unsigned pci_id, device_t from) -{ - return dev_find_device(pci_id >> 16, pci_id & 0xffff, from); -} -#else +#if defined (__PRE_RAM__) #include <arch/romcc_io.h> #endif @@ -20,6 +8,7 @@ { outb(0x04, 0xcf9); } + void hard_reset(void) { outb(0x02, 0xcf9); Modified: trunk/src/mainboard/intel/eagleheights/reset.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/reset.c Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/mainboard/intel/eagleheights/reset.c Sun Mar 28 23:26:54 2010 (r5307) @@ -21,20 +21,8 @@ #include <arch/io.h> #include <reset.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#if !defined (__ROMCC__) && !defined (__PRE_RAM__) -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) -#define PCI_DEV_INVALID 0 - -static inline device_t pci_locate_device(unsigned pci_id, device_t from) -{ - return dev_find_device(pci_id >> 16, pci_id & 0xffff, from); -} +#if defined (__PRE_RAM__) +#include <arch/romcc_io.h> #endif void soft_reset(void) Modified: trunk/src/mainboard/intel/jarrell/reset.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/reset.c Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/mainboard/intel/jarrell/reset.c Sun Mar 28 23:26:54 2010 (r5307) @@ -1,42 +1,25 @@ #include <arch/io.h> #include <reset.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#if !defined (__ROMCC__) && !defined (__PRE_RAM__) -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) -#define PCI_DEV_INVALID 0 - -static inline device_t pci_locate_device(unsigned pci_id, device_t from) -{ - return dev_find_device(pci_id >> 16, pci_id & 0xffff, from); -} -#endif +#include <arch/romcc_io.h> void soft_reset(void) { outb(0x04, 0xcf9); } + void hard_reset(void) { outb(0x02, 0xcf9); outb(0x06, 0xcf9); } + void full_reset(void) { - device_t dev; /* Enable power on after power fail... */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_LPC), 0); - if (dev != PCI_DEV_INVALID) { - unsigned byte; - byte = pci_read_config8(dev, 0xa4); - byte &= 0xfe; - pci_write_config8(dev, 0xa4, byte); - - } + unsigned byte; + byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + byte &= 0xfe; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, byte); outb(0x0e, 0xcf9); } Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Sun Mar 28 23:26:54 2010 (r5307) @@ -49,11 +49,6 @@ // for enable the FAN #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" - -static void post_code(u8 value) { - outb(value, 0x80); -} - #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sun Mar 28 23:26:54 2010 (r5307) @@ -50,10 +50,6 @@ // for enable the FAN #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" -static void post_code(u8 value) { - outb(value, 0x80); -} - #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" Modified: trunk/src/mainboard/supermicro/x6dai_g/reset.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/reset.c Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/mainboard/supermicro/x6dai_g/reset.c Sun Mar 28 23:26:54 2010 (r5307) @@ -1,20 +1,5 @@ #include <arch/io.h> #include <reset.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#if !defined (__ROMCC__) && !defined (__PRE_RAM__) -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) -#define PCI_DEV_INVALID 0 - -static inline device_t pci_locate_device(unsigned pci_id, device_t from) -{ - return dev_find_device(pci_id >> 16, pci_id & 0xffff, from); -} -#endif void soft_reset(void) { Modified: trunk/src/mainboard/supermicro/x6dhe_g/reset.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/reset.c Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/mainboard/supermicro/x6dhe_g/reset.c Sun Mar 28 23:26:54 2010 (r5307) @@ -1,25 +1,11 @@ #include <arch/io.h> #include <reset.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#if !defined (__ROMCC__) && !defined (__PRE_RAM__) -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) -#define PCI_DEV_INVALID 0 - -static inline device_t pci_locate_device(unsigned pci_id, device_t from) -{ - return dev_find_device(pci_id >> 16, pci_id & 0xffff, from); -} -#endif void soft_reset(void) { outb(0x04, 0xcf9); } + void hard_reset(void) { outb(0x02, 0xcf9); Modified: trunk/src/mainboard/supermicro/x6dhe_g2/reset.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/reset.c Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/mainboard/supermicro/x6dhe_g2/reset.c Sun Mar 28 23:26:54 2010 (r5307) @@ -1,25 +1,11 @@ #include <arch/io.h> #include <reset.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#if !defined (__ROMCC__) && !defined (__PRE_RAM__) -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) -#define PCI_DEV_INVALID 0 - -static inline device_t pci_locate_device(unsigned pci_id, device_t from) -{ - return dev_find_device(pci_id >> 16, pci_id & 0xffff, from); -} -#endif void soft_reset(void) { outb(0x04, 0xcf9); } + void hard_reset(void) { outb(0x02, 0xcf9); Modified: trunk/src/mainboard/supermicro/x6dhr_ig/reset.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/reset.c Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/mainboard/supermicro/x6dhr_ig/reset.c Sun Mar 28 23:26:54 2010 (r5307) @@ -1,25 +1,11 @@ #include <arch/io.h> #include <reset.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#if !defined (__ROMCC__) && !defined (__PRE_RAM__) -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) -#define PCI_DEV_INVALID 0 - -static inline device_t pci_locate_device(unsigned pci_id, device_t from) -{ - return dev_find_device(pci_id >> 16, pci_id & 0xffff, from); -} -#endif void soft_reset(void) { outb(0x04, 0xcf9); } + void hard_reset(void) { outb(0x02, 0xcf9); Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/reset.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/reset.c Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/reset.c Sun Mar 28 23:26:54 2010 (r5307) @@ -1,25 +1,11 @@ #include <arch/io.h> #include <reset.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#if !defined (__ROMCC__) && !defined (__PRE_RAM__) -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) -#define PCI_DEV_INVALID 0 - -static inline device_t pci_locate_device(unsigned pci_id, device_t from) -{ - return dev_find_device(pci_id >> 16, pci_id & 0xffff, from); -} -#endif void soft_reset(void) { outb(0x04, 0xcf9); } + void hard_reset(void) { outb(0x02, 0xcf9); Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sun Mar 28 23:26:54 2010 (r5307) @@ -48,11 +48,6 @@ #include <cpu/x86/lapic.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" - -static void post_code(u8 value) { - outb(value, 0x80); -} - #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT Modified: trunk/src/northbridge/via/cn400/cn400.h ============================================================================== --- trunk/src/northbridge/via/cn400/cn400.h Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/northbridge/via/cn400/cn400.h Sun Mar 28 23:26:54 2010 (r5307) @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ static void cn400_noop(void) { } Modified: trunk/src/northbridge/via/cn700/cn700.h ============================================================================== --- trunk/src/northbridge/via/cn700/cn700.h Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/northbridge/via/cn700/cn700.h Sun Mar 28 23:26:54 2010 (r5307) @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if !defined (__ROMCC__) && !defined (__PRE_RAM__) +#if !defined (__PRE_RAM__) static void cn700_noop() { } Modified: trunk/src/northbridge/via/vx800/vx800.h ============================================================================== --- trunk/src/northbridge/via/vx800/vx800.h Sun Mar 28 17:11:56 2010 (r5306) +++ trunk/src/northbridge/via/vx800/vx800.h Sun Mar 28 23:26:54 2010 (r5307) @@ -20,7 +20,7 @@ #ifndef VX800_H #define VX800_H 1 -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ static void vx800_noop() { }

1 0

build service results for r5306
by coreboot information 28 Mar '10

28 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5306 to the coreboot repository. This caused the following changes: Change Log: drop __ROMCC__ define checks.. __PRE_RAM__ is what the code should be looking for. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of asus:a8n_e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5306&device=a8n_e&vendor=a… Compilation of asus:p2b-f is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5306&device=p2b-f&vendor=a… Compilation of asus:p2b-ls is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5306&device=p2b-ls&vendor=… Compilation of asus:p3b-f is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5306&device=p3b-f&vendor=a… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5306 - in trunk/src/southbridge: amd/cs5530 intel/i82371eb intel/i82801ax intel/i82801bx intel/i82801cx intel/i82801dx intel/i82801gx
by repository service 28 Mar '10

28 Mar '10

Author: stepan Date: Sun Mar 28 17:11:56 2010 New Revision: 5306 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5306 Log: drop __ROMCC__ define checks.. __PRE_RAM__ is what the code should be looking for. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/southbridge/amd/cs5530/cs5530.h trunk/src/southbridge/intel/i82371eb/i82371eb.h trunk/src/southbridge/intel/i82801ax/i82801ax.h trunk/src/southbridge/intel/i82801bx/i82801bx.h trunk/src/southbridge/intel/i82801cx/i82801cx.h trunk/src/southbridge/intel/i82801dx/i82801dx.h trunk/src/southbridge/intel/i82801gx/i82801gx.h Modified: trunk/src/southbridge/amd/cs5530/cs5530.h ============================================================================== --- trunk/src/southbridge/amd/cs5530/cs5530.h Sat Mar 27 18:36:39 2010 (r5305) +++ trunk/src/southbridge/amd/cs5530/cs5530.h Sun Mar 28 17:11:56 2010 (r5306) @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_AMD_CS5530_CS5530_H #define SOUTHBRIDGE_AMD_CS5530_CS5530_H -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) #include "chip.h" void cs5530_enable(device_t dev); #endif Modified: trunk/src/southbridge/intel/i82371eb/i82371eb.h ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb.h Sat Mar 27 18:36:39 2010 (r5305) +++ trunk/src/southbridge/intel/i82371eb/i82371eb.h Sun Mar 28 17:11:56 2010 (r5306) @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) #include "chip.h" void i82371eb_enable(device_t dev); void i82371eb_hard_reset(void); Modified: trunk/src/southbridge/intel/i82801ax/i82801ax.h ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax.h Sat Mar 27 18:36:39 2010 (r5305) +++ trunk/src/southbridge/intel/i82801ax/i82801ax.h Sun Mar 28 17:11:56 2010 (r5306) @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H #define SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) #include "chip.h" extern void i82801ax_enable(device_t dev); #endif Modified: trunk/src/southbridge/intel/i82801bx/i82801bx.h ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx.h Sat Mar 27 18:36:39 2010 (r5305) +++ trunk/src/southbridge/intel/i82801bx/i82801bx.h Sun Mar 28 17:11:56 2010 (r5306) @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H #define SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) #include "chip.h" extern void i82801bx_enable(device_t dev); #endif Modified: trunk/src/southbridge/intel/i82801cx/i82801cx.h ============================================================================== --- trunk/src/southbridge/intel/i82801cx/i82801cx.h Sat Mar 27 18:36:39 2010 (r5305) +++ trunk/src/southbridge/intel/i82801cx/i82801cx.h Sun Mar 28 17:11:56 2010 (r5306) @@ -1,7 +1,7 @@ #ifndef I82801CX_H #define I82801CX_H -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) #include "chip.h" extern void i82801cx_enable(device_t dev); #endif Modified: trunk/src/southbridge/intel/i82801dx/i82801dx.h ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx.h Sat Mar 27 18:36:39 2010 (r5305) +++ trunk/src/southbridge/intel/i82801dx/i82801dx.h Sun Mar 28 17:11:56 2010 (r5306) @@ -31,7 +31,7 @@ #ifndef I82801DX_H #define I82801DX_H -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) #include "chip.h" extern void i82801dx_enable(device_t dev); #endif Modified: trunk/src/southbridge/intel/i82801gx/i82801gx.h ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx.h Sat Mar 27 18:36:39 2010 (r5305) +++ trunk/src/southbridge/intel/i82801gx/i82801gx.h Sun Mar 28 17:11:56 2010 (r5306) @@ -39,10 +39,7 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -/* __ROMCC__ is set by romstage.c to make sure - * none of the stage2 data structures are included. - */ -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) #include "chip.h" extern void i82801gx_enable(device_t dev); #endif

1 0

[FILO] r114 - in trunk/filo: . include/grub main/grub
by repository service 27 Mar '10

27 Mar '10

Author: stepan Date: Fri Mar 26 12:57:34 2010 New Revision: 114 URL: http://tracker.coreboot.org/trac/filo/changeset/114 Log: grub interface update - add support for "default" (aka grubonce) support through cmos - add dumpmem command - add isolinux parser Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/filo/Config.in trunk/filo/include/grub/shared.h trunk/filo/main/grub/builtins.c trunk/filo/main/grub/grub.c Modified: trunk/filo/Config.in ============================================================================== --- trunk/filo/Config.in Fri Mar 26 12:55:18 2010 (r113) +++ trunk/filo/Config.in Fri Mar 26 12:57:34 2010 (r114) @@ -79,6 +79,14 @@ help Time in second before booting AUTOBOOT_FILE +config ISOLINUX_PARSER + bool "Support for parsing isolinux.cfg config files" + default n + depends on USE_GRUB + help + If you enable this function, FILO will be able to parse isolinux.cfg + config files in addition to filo.lst/menu.lst files. + endmenu menu "Drivers" Modified: trunk/filo/include/grub/shared.h ============================================================================== --- trunk/filo/include/grub/shared.h Fri Mar 26 12:55:18 2010 (r113) +++ trunk/filo/include/grub/shared.h Fri Mar 26 12:57:34 2010 (r114) @@ -132,7 +132,6 @@ MAX_ERR_NUM } grub_error_t; -extern int saved_entryno; extern char config_file[]; /* GUI interface variables. */ Modified: trunk/filo/main/grub/builtins.c ============================================================================== --- trunk/filo/main/grub/builtins.c Fri Mar 26 12:55:18 2010 (r113) +++ trunk/filo/main/grub/builtins.c Fri Mar 26 12:57:34 2010 (r114) @@ -2,7 +2,7 @@ * This file is part of FILO. * * Copyright (C) 1999,2000,2001,2002,2004 Free Software Foundation, Inc. - * Copyright (C) 2005-2008 coresystems GmbH + * Copyright (C) 2005-2010 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,6 +20,8 @@ #include <libpayload-config.h> #include <libpayload.h> +#include <getopt.h> + #include <config.h> #include <fs.h> #include <lib.h> @@ -45,7 +47,6 @@ // other.. unsigned long install_partition = 0x20000; unsigned long boot_drive = 0; -int saved_entryno = 0; char config_file[128] = "\0"; kernel_t kernel_type; @@ -336,6 +337,15 @@ /* default */ static int default_func(char *arg, int flags) { + unsigned char buf[1]; + if (get_option(buf, "boot_default")) + buf[0] = 0xff; + + if ((unsigned char)buf[0] != 0xff) { + printf("Default override by CMOS.\n"); + return 0; + } + if (!safe_parse_maxint(&arg, &default_entry)) return 1; @@ -354,7 +364,47 @@ }; #if CONFIG_DEVELOPER_TOOLS -/* default */ +/* dumpmem */ +static int dumpmem_func(char *arg, int flags) +{ + int ret = string_to_args("dumpmem", arg); + unsigned int mem_base, mem_len; + void *i; + + if(ret || (string_argc != 3)) { + errnum = ERR_BAD_ARGUMENT; + return 1; + } + + // FIXME + if (!safe_parse_maxint(&string_argv[1], &mem_base)) + return 1; + if (!safe_parse_maxint(&string_argv[2], &mem_len)) + return 1; + + grub_printf("Dumping memory at 0x%08x (0x%x bytes)\n", + mem_base, mem_len); + + for (i=phys_to_virt(mem_base); i<phys_to_virt(mem_base + mem_len); i++) { + if (((unsigned long)i & 0x0f) == 0) + grub_printf("\n%08x:", i); + unsigned char val = *((unsigned char *)i); + grub_printf(" %02x", val); + } + grub_printf("\n"); + + return 0; +} + +static struct builtin builtin_dumpmem = { + "dumpmem", + dumpmem_func, + BUILTIN_CMDLINE | BUILTIN_HELP_LIST, + "dumpmem", + "Dump memory" +}; + +/* dumppm */ static int dumppm_func(char *arg, int flags) { u16 pmbase; @@ -651,9 +701,16 @@ } if (disk == -1) { - /* The user did specify a FILO name already */ - // grub_printf("No drive.\n"); - len = 0; // just copy the drive name + int cnt = 0; + len = 0; + while ((arg[cnt] != 0) && (arg[cnt+1] != 0)) { + if (arg[cnt] == ':' && arg[cnt+1] == '/') { + /* The user did specify a FILO name already */ + len = cnt; + break; + } + cnt++; + } } else { if (part == -1) { // No partition sprintf(devicename, "%s%c:", drivername, disk + 'a'); @@ -895,7 +952,7 @@ for (i=0; i<lspci_indent; i++) grub_printf("| "); - grub_printf("|- %x:%x.%x [%x:%x]\n", bus, slot, func, + grub_printf("|- %02x:%02x.%x [%04x:%04x]\n", bus, slot, func, val & 0xffff, val >> 16); /* If this is a bridge, then follow it. */ @@ -1704,6 +1761,7 @@ &builtin_configfile, &builtin_default, #ifdef CONFIG_DEVELOPER_TOOLS + &builtin_dumpmem, &builtin_dumppm, #endif #ifdef CONFIG_EXPERIMENTAL Modified: trunk/filo/main/grub/grub.c ============================================================================== --- trunk/filo/main/grub/grub.c Fri Mar 26 12:55:18 2010 (r113) +++ trunk/filo/main/grub/grub.c Fri Mar 26 12:57:34 2010 (r114) @@ -32,6 +32,9 @@ char PASSWORD_BUF[PASSWORD_BUFLEN]; /* The buffer for the password. */ char DEFAULT_FILE_BUF[DEFAULT_FILE_BUFLEN]; /* THe buffer for the filename of "/boot/grub/default". */ char CMDLINE_BUF[CMDLINE_BUFLEN]; /* The buffer for the command-line. */ +#ifdef CONFIG_ISOLINUX_PARSER +char CMDLINE_TMP[CMDLINE_BUFLEN]; /* The buffer for the command-line. */ +#endif char HISTORY_BUF[HISTORY_BUFLEN]; /* The history buffer for the command-line. */ char COMPLETION_BUF[COMPLETION_BUFLEN]; /* The buffer for the completion. */ char UNIQUE_BUF[UNIQUE_BUFLEN]; /* The buffer for the unique string. */ @@ -173,6 +176,12 @@ return; if (probe_menulst(bootdevice, "/boot/menu.lst")) return; +#ifdef CONFIG_ISOLINUX_PARSER + if (probe_menulst(bootdevice, "/boot/isolinux/isolinux.cfg")) + return; + if (probe_menulst(bootdevice, "/isolinux/isolinux.cfg")) + return; +#endif } } while (bootdevice); @@ -871,6 +880,88 @@ return pos; } +#ifdef CONFIG_ISOLINUX_PARSER +static int rewrite_isolinux_config(void) +{ + /* TODO implement "default" */ + /* TODO implement "timeout" */ + if (!memcmp(CMDLINE_BUF, "LABEL ", 6) || + !memcmp(CMDLINE_BUF, "label ", 6)) { + strcpy(CMDLINE_TMP, "title "); + strlcat(CMDLINE_TMP, CMDLINE_BUF + 6, NEW_HEAPSIZE - 6); + memcpy(CMDLINE_BUF, CMDLINE_TMP, NEW_HEAPSIZE); + } else + if (!memcmp(CMDLINE_BUF, "KERNEL ", 7) || + !memcmp(CMDLINE_BUF, "kernel ", 7)) { + char *spos; + int pstart = 7, plen = 0; + strcpy(CMDLINE_TMP, "kernel "); + + /* Find path of kernel */ + if (strstr(CMDLINE_BUF, " /")) { + // Our kernel has an absolute path, so + // we only grab the device portion of the + // config file + + // (hd0,0)/configfile.cfg or hda1:/configfile.cfg + spos = strchr(config_file, '/'); + if (!spos) { + // (hd0,0)configfile.cfg + spos = strchr(config_file, ')'); + if (spos) spos++; + } + if (!spos) { + // hda1:configfile.cfg + spos = strchr(config_file, ':'); + if (spos) spos++; + } + } else { + spos = strrchr(config_file, '/'); + if (spos) spos++; + } + + if (spos) { + char sback = spos[0]; + spos[0]=0; + strlcat(CMDLINE_TMP, config_file, NEW_HEAPSIZE); + plen = strlen(CMDLINE_TMP) - pstart; // path name len + spos[0]=sback; + } + + /* copy kernel name */ + strlcat(CMDLINE_TMP, CMDLINE_BUF + 7, NEW_HEAPSIZE); + + /* recalculate the new kernel path length, + * we're going to need this for initrd + */ + plen = strrchr(CMDLINE_TMP, '/') - (CMDLINE_TMP + 7) + 1; + + /* read APPEND line */ + get_line_from_config(CMDLINE_BUF, NEW_HEAPSIZE, 1); + if (!memcmp(CMDLINE_BUF, "APPEND ", 7) || + !memcmp(CMDLINE_BUF, "append ", 7)) { + /* append APPEND line */ + strlcat(CMDLINE_TMP, " ", NEW_HEAPSIZE); + strlcat(CMDLINE_TMP, CMDLINE_BUF + 7, NEW_HEAPSIZE); + spos = strstr(CMDLINE_TMP, "initrd=") + 7; + if (spos && plen) { + strncpy(spos, CMDLINE_TMP + pstart, plen); + spos[plen] = 0; + spos = strstr(CMDLINE_BUF, "initrd=") + 7; + strlcat(CMDLINE_TMP, spos, NEW_HEAPSIZE); + } + } + + /* copy temp string to real string */ + memcpy(CMDLINE_BUF, CMDLINE_TMP, NEW_HEAPSIZE); + } else { + // printf("skip: %s\n", CMDLINE_BUF); + return 1; + } + return 0; +} +#endif + int is_opened = 0, is_preset = 0; /* This is the starting function in C. */ @@ -912,6 +1003,7 @@ /* Never return. */ for (;;) { + char buf[10]; /* This is good enough. */ char *default_file = (char *) DEFAULT_FILE_BUF; int i; @@ -920,34 +1012,41 @@ /* Here load the configuration file. */ /* Get a saved default entry if possible. */ - saved_entryno = 0; *default_file = 0; - strncat(default_file, config_file, DEFAULT_FILE_BUFLEN); - for (i = strlen(default_file); i >= 0; i--) - if (default_file[i] == '/') { - i++; - break; - } - default_file[i] = 0; - strncat(default_file + i, "default", DEFAULT_FILE_BUFLEN - i); - if (file_open(default_file)) { - char buf[10]; /* This is good enough. */ - char *p = buf; - int len; - - len = file_read(buf, sizeof(buf)); - if (len > 0) { - buf[sizeof(buf) - 1] = 0; - safe_parse_maxint(&p, &saved_entryno); - } + /* Look into CMOS first */ + if (!get_option(buf, "boot_default")) { + default_entry = ((unsigned char)buf[0] != 0xff) ? + (unsigned char)buf[0] : 0; + } else { + strncat(default_file, config_file, DEFAULT_FILE_BUFLEN); + for (i = strlen(default_file); i >= 0; i--) + if (default_file[i] == '/') { + i++; + break; + } + default_file[i] = 0; + strncat(default_file + i, "default", DEFAULT_FILE_BUFLEN - i); + if (file_open(default_file)) { + char *p = buf; + int len; + + len = file_read(buf, sizeof(buf)); + if (len > 0) { + buf[sizeof(buf) - 1] = 0; + safe_parse_maxint(&p, &default_entry); + } - file_close(); + file_close(); + } } errnum = ERR_NONE; do { +#ifdef CONFIG_ISOLINUX_PARSER + int isolinux_cfg = 0; +#endif /* STATE 0: Before any title command. STATE 1: In a title command. STATE >1: In a entry after a title command. */ @@ -960,6 +1059,12 @@ if (!is_opened) { is_opened = file_open(config_file); errnum = ERR_NONE; +#ifdef CONFIG_ISOLINUX_PARSER + if (strstr(config_file, "isolinux.cfg")) { + printf("detected isolinux.cfg\n"); + isolinux_cfg = 1; + } +#endif } if (!is_opened) { @@ -975,6 +1080,12 @@ cmdline = (char *) CMDLINE_BUF; while (get_line_from_config(cmdline, NEW_HEAPSIZE, !is_preset)) { struct builtin *builtin; +#ifdef CONFIG_ISOLINUX_PARSER + if (isolinux_cfg) { + if (rewrite_isolinux_config()) + continue; + } +#endif /* Get the pointer to the builtin structure. */ builtin = find_command(cmdline);

3 2

GIGABYTE GA-K8NXP-SLI support
by Ştefan-Daniel Mihăilă 27 Mar '10

27 Mar '10

Hello, Do I have any chance of using coreboot (now or in the future) with my GIGABYTE GA-K8NXP-SLI motherboard? mainboard: GIGABYTE GA-K8NXP-SLI CPU: AMD Athlon64 3500+ (Socket 939) The official specifications say "NVIDIA nForce4 SLI chipset", but seems to be NVIDIA nForce4 SLI x16 northbridge and NVIDIA CK804 southbridge url: http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ClassVal… I updated the original proprietary BIOS before. -------------------------------------------------------------------------------- $ lspci -tvnn -[0000:00]-+-00.0 nVidia Corporation CK804 Memory Controller [10de:005e] +-01.0 nVidia Corporation CK804 ISA Bridge [10de:0050] +-01.1 nVidia Corporation CK804 SMBus [10de:0052] +-02.0 nVidia Corporation CK804 USB Controller [10de:005a] +-02.1 nVidia Corporation CK804 USB Controller [10de:005b] +-04.0 nVidia Corporation CK804 AC'97 Audio Controller [10de:0059] +-06.0 nVidia Corporation CK804 IDE [10de:0053] +-07.0 nVidia Corporation CK804 Serial ATA Controller [10de:0054] +-09.0-[0000:01]----07.0 RaLink RT2500 802.11g Cardbus/mini-PCI [1814:0201] +-0b.0-[0000:02]----00.0 Marvell Technology Group Ltd. 88E8053 PCI-E Gigabit Ethernet Controller [11ab:4362] +-0c.0-[0000:03]-- +-0d.0-[0000:04]-- +-0e.0-[0000:05]----00.0 nVidia Corporation NV43 [GeForce 6600 GT] [10de:0140] +-18.0 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] +-18.1 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] +-18.2 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] \-18.3 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103] -------------------------------------------------------------------------------- # superiotool -dV Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Found ITE IT8712F (id=0x8712, rev=0x5) at 0x2e Register dump: idx 20 21 22 23 24 2b val 87 12 05 41 00 00 def 87 12 08 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 00 00 00 00 04 00 00 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 f2 f3 val 01 03 f8 04 00 50 00 7f def 00 03 f8 04 00 50 00 7f LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 00 00 00 00 40 50 01 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0 val 00 00 00 00 00 00 04 08 def 00 03 78 07 78 07 03 03 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 02 90 00 00 00 08 00 0a 00 0a 03 01 def 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 68 def 01 00 60 00 64 01 02 08 LDN 0x06 (Mouse) idx 30 70 71 f0 val 01 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd val de 22 20 01 08 00 00 00 00 08 00 00 00 00 31 80 05 04 04 00 00 00 00 00 0c 00 20 01 00 00 d2 22 00 00 08 40 00 00 00 00 00 00 00 00 00 10 40 00 00 00 00 1d 00 00 00 00 00 06 00 def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x08 (MIDI port) idx 30 60 61 70 f0 val 00 03 00 0a 00 def 00 03 00 0a 00 LDN 0x09 (Game port) idx 30 60 61 val 00 02 01 def 00 02 01 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 00 00 00 06 def 00 03 10 0b 00 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff -------------------------------------------------------------------------------- # flashrom -V flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: " " DMI string system-product-name: " " DMI string system-version: " " DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd." DMI string baseboard-product-name: "GA-K8NXP-SLI" DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found ITE Super I/O, id 8712 Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Disabling flash write protection for board "GIGABYTE GA-K8N-SLI"... OK. Calibrating delay loop... 619M loops per second, 100 myus = 179 us. OK. Probing for AMD Am29F010A/B, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec_common: id1 0x24, id2 0xcd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec_common: id1 0x24, id2 0xcd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C010A, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C040A, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N), 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x24, id2 0xcd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x24, id2 0xcd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for EMST F49B002UA, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Eon EN25B05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec_common: id1 0x24, id2 0xcd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec_common: id1 0x24, id2 0xcd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec_common: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec_common: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x49, id2 0x44 Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x49, id2 0x44 Probing for Intel 28F001BX-B, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Intel 28F001BX-T, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Intel 28F004S5, 512 KB: probe_82802ab: id1 0x49, id2 0x4d Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x49, id2 0x4d Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x24, id2 0xcd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x24, id2 0xcd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x24, id2 0xcd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x24, id2 0xcd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: probe_82802ab: id1 0x49, id2 0x4d Probing for SST SST29EE010, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29LE010, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29EE020A, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29LE020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF512, 64 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF010A, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF020A, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF040, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF512, 64 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF010, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF040, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF080, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x49, id2 0x4d Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: probe_jedec_common: id1 0x24, id2 0xcd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 KB: probe_jedec_common: id1 0x24, id2 0xcd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x49, id2 0x44 Probing for ST M29W010B, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 KB: probe_jedec_common: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 KB: probe_jedec_common: id1 0xe9, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x49, id2 0x4d Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x49, id2 0x4d Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0x24, id2 0xcd Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x49, id2 0x4d Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SyncMOS S29C31004T, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51001T, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51002T, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51004T, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for TI TMS29F002RB, 256 KB: probe_jedec_common: id1 0x24, id2 0xcd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 KB: probe_jedec_common: id1 0x24, id2 0xcd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25x10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29C020C, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29C040P, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === No operations were specified. -------------------------------------------------------------------------------- Thanks! -- Stefan

2 1

build service results for r5305
by coreboot information 27 Mar '10

27 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5305 to the coreboot repository. This caused the following changes: Change Log: ccache and scan-build actually work together, so remove the restriction that tells Kconfig not to allow that setup. It's not particularily useful, as scan-build totally dominates the gcc runtime, but well.. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Build Log: Compilation of asus:p2b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5305&device=p2b-f&vendor=a… Compilation of asus:p2b-ls has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5305&device=p2b-ls&vendor=… Compilation of asus:p3b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5305&device=p3b-f&vendor=a… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5305 - trunk/src
by repository service 27 Mar '10

27 Mar '10

Author: oxygene Date: Sat Mar 27 18:36:39 2010 New Revision: 5305 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5305 Log: ccache and scan-build actually work together, so remove the restriction that tells Kconfig not to allow that setup. It's not particularily useful, as scan-build totally dominates the gcc runtime, but well.. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/Kconfig Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Sat Mar 27 18:18:39 2010 (r5304) +++ trunk/src/Kconfig Sat Mar 27 18:36:39 2010 (r5305) @@ -62,7 +62,6 @@ config SCANBUILD_ENABLE bool "Build with scan-build for static analysis" default n - depends on !CCACHE help Changes the build process to scan-build is used. Requires scan-build in path.

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coreboot March 2010