coreboot February 2010

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Re: [coreboot] AMD HT link frequency limit configuration patch
by Timothy Pearson 24 Feb '10

24 Feb '10

Here is a new patch that utilizes KConfig in expert mode. Also, the HT width is now configurable as well. This patch is critical for the MSI MS-9652 mainboard and Barcelona CPUs; without limiting the HT link the system was completely unstable due to bad PCB layout. --- Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Timothy Pearson Raptor Engineering

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[commit] r5158 - in trunk/src: mainboard mainboard/winent mainboard/winent/pl6064 superio/winbond/w83627hf
by repository service 24 Feb '10

24 Feb '10

Author: oxygene Date: Wed Feb 24 17:36:56 2010 New Revision: 5158 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5158 Log: Add Win Enterprises' PL6064 board Signed-off-by: Anish K. Patel <anishp(a)win-ent.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Added: trunk/src/mainboard/winent/ trunk/src/mainboard/winent/Kconfig trunk/src/mainboard/winent/pl6064/ trunk/src/mainboard/winent/pl6064/Kconfig trunk/src/mainboard/winent/pl6064/Makefile.inc trunk/src/mainboard/winent/pl6064/chip.h trunk/src/mainboard/winent/pl6064/cmos.layout trunk/src/mainboard/winent/pl6064/devicetree.cb trunk/src/mainboard/winent/pl6064/irq_tables.c trunk/src/mainboard/winent/pl6064/mainboard.c trunk/src/mainboard/winent/pl6064/romstage.c Modified: trunk/src/mainboard/Kconfig trunk/src/superio/winbond/w83627hf/superio.c Modified: trunk/src/mainboard/Kconfig ============================================================================== --- trunk/src/mainboard/Kconfig Wed Feb 24 14:58:23 2010 (r5157) +++ trunk/src/mainboard/Kconfig Wed Feb 24 17:36:56 2010 (r5158) @@ -94,6 +94,8 @@ bool "Tyan" config VENDOR_VIA bool "VIA" +config VENDOR_WINENT + bool "Win Enterprises" endchoice @@ -352,6 +354,11 @@ default 0x1019 depends on VENDOR_VIA +config MAINBOARD_VENDOR + string + default "Win Enterprise" + depends on VENDOR_WINENT + source "src/mainboard/a-trend/Kconfig" source "src/mainboard/abit/Kconfig" source "src/mainboard/advantech/Kconfig" @@ -397,6 +404,7 @@ source "src/mainboard/thomson/Kconfig" source "src/mainboard/tyan/Kconfig" source "src/mainboard/via/Kconfig" +source "src/mainboard/winent/Kconfig" config BOARD_ROMSIZE_KB_128 bool Added: trunk/src/mainboard/winent/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/winent/Kconfig Wed Feb 24 17:36:56 2010 (r5158) @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_WINENT + +source "src/mainboard/winent/pl6064/Kconfig" + +endchoice + Added: trunk/src/mainboard/winent/pl6064/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/winent/pl6064/Kconfig Wed Feb 24 17:36:56 2010 (r5158) @@ -0,0 +1,38 @@ +config BOARD_WINENT_PL6064 + bool "PL6064" + select ARCH_X86 + select CPU_AMD_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR + select BOARD_ROMSIZE_KB_512 + +config MAINBOARD_DIR + string + default winent/pl6064 + depends on BOARD_WINENT_PL6064 + +config MAINBOARD_PART_NUMBER + string + default "PL6064" + depends on BOARD_WINENT_PL6064 + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_WINENT_PL6064 + +config IRQ_SLOT_COUNT + int + default 7 + depends on BOARD_WINENT_PL6064 + +config RAMBASE + hex + default 0x4000 + depends on BOARD_WINENT_PL6064 Added: trunk/src/mainboard/winent/pl6064/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/winent/pl6064/Makefile.inc Wed Feb 24 17:36:56 2010 (r5158) @@ -0,0 +1,21 @@ +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +crt0s := $(src)/cpu/x86/16bit/entry16.inc +crt0s += $(src)/cpu/x86/32bit/entry32.inc +crt0s += $(src)/cpu/x86/16bit/reset16.inc +crt0s += $(src)/arch/i386/lib/id.inc +crt0s += $(src)/cpu/amd/model_lx/cache_as_ram.inc +crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc + +ldscripts := $(src)/arch/i386/init/ldscript_fallback_cbfs.lb +ldscripts += $(src)/cpu/x86/16bit/entry16.lds +ldscripts += $(src)/cpu/x86/16bit/reset16.lds +ldscripts += $(src)/arch/i386/lib/id.lds +ldscripts += $(src)/arch/i386/lib/failover.lds + Added: trunk/src/mainboard/winent/pl6064/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/winent/pl6064/chip.h Wed Feb 24 17:36:56 2010 (r5158) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config { + int nothing; +}; Added: trunk/src/mainboard/winent/pl6064/cmos.layout ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/winent/pl6064/cmos.layout Wed Feb 24 17:36:56 2010 (r5158) @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + Added: trunk/src/mainboard/winent/pl6064/devicetree.cb ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/winent/pl6064/devicetree.cb Wed Feb 24 17:36:56 2010 (r5158) @@ -0,0 +1,81 @@ +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x0000105a" + register "lpc_serirq_polarity" = "0x0000EFA5" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "1" # 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3F8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2F8" + register "com2_irq" = "3" + register "unwanted_vpci[0]" = "0" # End of list has a zero + + device pci d.0 on end # Ethernet 4 + device pci a.0 on end # Ethernet 1 + device pci b.0 on end # Ethernet 2 + device pci c.0 on end # Ethernet 3 + device pci e.0 on end # Slot1 + device pci f.0 on # ISA Bridge + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a on # ACPI + irq 0x70 = 9 + end + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + end + end + end + device pci f.2 on end # IDE Controller + device pci f.3 off end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end +end + Added: trunk/src/mainboard/winent/pl6064/irq_tables.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/winent/pl6064/irq_tables.c Wed Feb 24 17:36:56 2010 (r5158) @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Win Enterprises, Inc (anishp(a)win-ent.com) + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/pirq_routing.h> +#include "../../../southbridge/amd/cs5536/cs5536.h" + +/* Platform IRQs */ +#define PIRQA 11 +#define PIRQB 10 +#define PIRQC 5 +#define PIRQD 10 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + 0x100B, /* Vendor */ + 0x002B, /* Device */ + 0, /* Crap (miniport) */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ + {0x00, (0x09 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 0*/ + {0x00, (0x0A << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 1*/ + {0x00, (0x0B << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 2*/ + {0x00, (0x0C << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 3 on 65 - shared switch on 64*/ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, /* slot1 */ + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/src/mainboard/winent/pl6064/mainboard.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/winent/pl6064/mainboard.c Wed Feb 24 17:36:56 2010 (r5158) @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Win Enterprises, Inc. (anishp(a)win-ent.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include "chip.h" + +static void init(struct device *dev) +{ + printk_debug("Win Enterprises PL-6064/65 ENTER %s\n", __func__); + printk_debug("Win Enterprises PL-6064/65 EXIT %s\n", __func__); +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("Win Enterprises PL-6064/65 Mainboard") + .enable_dev = enable_dev, +}; Added: trunk/src/mainboard/winent/pl6064/romstage.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/winent/pl6064/romstage.c Wed Feb 24 17:36:56 2010 (r5158) @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Win Enterprises, Inc (anishp(a)win-ent.com) + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 +#define __PRE_RAM__ + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "lib/ramtest.c" +#include "cpu/x86/bist.h" +#include "cpu/x86/msr.h" +#include <cpu/amd/lxdef.h> +#include <cpu/amd/geode_post_code.h> +#include "southbridge/amd/cs5536/cs5536.h" + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) +#define POST_CODE(x) outb(x, 0x80) +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +#include "southbridge/amd/cs5536/cs5536_early_smbus.c" +#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#define ManualConf 0 /* Do automatic strapped PLL config */ +#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ +#define PLLMSRlo 0x02000030 +#define DIMM0 0xA0 +#define DIMM1 0xA2 + +#include "northbridge/amd/lx/raminit.h" +#include "northbridge/amd/lx/pll_reset.c" +#include "northbridge/amd/lx/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/model_lx/cpureginit.c" +#include "cpu/amd/model_lx/syspreinit.c" + +struct msrinit { + u32 msrnum; + msr_t msr; + }; + +static const struct msrinit msr_table[] = +{ + {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB. + * Rom Properties: Write Serialize, WriteProtect. + * RomBase: 0xFFFC0 + * SysTop to RomBase Properties: Write Serialize, Cache Disable. + * SysTop: 0x000A0 + * System Memory Properties: (Write Back) */ + {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */ + {CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */ + {CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */ + + /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */ + {MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF + {MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF + {MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF + {MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF + {MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF + {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF +}; + + +static void msr_init(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(msr_table); i++) + wrmsr(msr_table[i].msrnum, msr_table[i].msr); +} + +static void mb_gpio_init(void) +{ + /* Early mainboard specific GPIO setup. */ +} + +void cache_as_ram_main(void) +{ + POST_CODE(0x01); + + static const struct mem_controller memctrl[] = { + {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + /* Note: must do this AFTER the early_setup! It is counting on some + * early MSR setup for CS5536. + */ + w83627hf_set_clksel_48(SERIAL_DEV); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + mb_gpio_init(); + uart_init(); + console_init(); + + pll_reset(ManualConf); + + cpuRegInit(); + + sdram_initialize(1, memctrl); + + /* Check memory. */ + /* ram_check(0x00000000, 640 * 1024); */ + + /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ + return; +} Modified: trunk/src/superio/winbond/w83627hf/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627hf/superio.c Wed Feb 24 14:58:23 2010 (r5157) +++ trunk/src/superio/winbond/w83627hf/superio.c Wed Feb 24 17:36:56 2010 (r5158) @@ -4,6 +4,7 @@ * Copyright (C) 2000 AG Electronics Ltd. * Copyright (C) 2003-2004 Linux Networx * Copyright (C) 2004 Tyan By LYH change from PC87360 + * Copyright (C) 2010 Win Enterprises (anishp(a)win-ent.com) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -56,6 +57,16 @@ return inb(port_base + 1); } +static void w83627hf_16_bit_addr_qual(device_t dev) +{ + int port = dev->path.pnp.port >> 8; + pnp_enter_ext_func_mode(dev); + outb(0x24, port); + /* enable 16 bit address qualification */ + outb(inb(port + 1) | 0x80, port + 1); + pnp_exit_ext_func_mode(dev); +} + static void enable_hwm_smbus(device_t dev) { /* set the pin 91,92 as I2C bus */

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RCC chipset support?
by Jochum Doring 24 Feb '10

24 Feb '10

Dear Coreboot, I am following this project for a while now and i am thinking about using coreboot on an old server i have. It is an HP Visualize X-class (A1280) with an RCC Serverset III WS chipset. I noticed it wasn't listed as supported, but i was still wondering if this could work. Thanks in advance. Cheers, Jochum

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Re: [coreboot] MP table multicore patch
by Timothy Pearson 24 Feb '10

24 Feb '10

> tpearson at raptorengineeringinc.com wrote: > > I have patched src/arch/i386/smp/mpspec.c to write a correct, multi-core > > MP table under amdfam10. > > I think this is very desirable and a great functionality improvement! > Thanks! > > But this code is not nice at all. You're right, it is quite complex for what it does. It was hacked together over a period of about 30 minutes just to get my board working. Also, I wasn't sure if there would be any interest in such a feature when I submitted the patch. > Could you shift it around so that it uses continue aggressively, and > has shorter variable names? Sure thing. > It looks like that could reduce > indentation two or three levels, and then the code might actually be > visible in my terminal... Heh. I have the same problem in my Webmail client! > Is this romcc code? If not, maybe it could even be recursive.. Not sure, but I know it is very sensitive. Running printk here reliably crashed coreboot, so the stack may be limited; I didn't want to risk recursion causing some problem later on for anyone else. > > //Peter I probably won't be able to get to this for a couple weeks, as the board I was working with has already entered production. I should have an identical board in a week or two that I can experiment with. Timothy Pearson Raptor Engineering

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[commit] r5157 - in trunk/src/arch/i386: . include init
by repository service 24 Feb '10

24 Feb '10

Author: oxygene Date: Wed Feb 24 14:58:23 2010 New Revision: 5157 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5157 Log: Enable user selectable bootblocks, and provide a bootblock that selects between "fallback" and "normal", in addition to the already present "fallback"-only bootblock. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/src/arch/i386/Makefile.bootblock.inc - copied, changed from r5156, trunk/src/arch/i386/Makefile.tinybootblock.inc trunk/src/arch/i386/include/bootblock_common.h - copied, changed from r5156, trunk/src/arch/i386/init/bootblock.c trunk/src/arch/i386/init/bootblock_normal.c - copied, changed from r5156, trunk/src/arch/i386/init/bootblock.c trunk/src/arch/i386/init/bootblock_simple.c - copied, changed from r5156, trunk/src/arch/i386/init/bootblock.c Deleted: trunk/src/arch/i386/Makefile.tinybootblock.inc trunk/src/arch/i386/init/bootblock.c Modified: trunk/src/arch/i386/Kconfig trunk/src/arch/i386/Makefile.inc Modified: trunk/src/arch/i386/Kconfig ============================================================================== --- trunk/src/arch/i386/Kconfig Wed Feb 24 14:18:01 2010 (r5156) +++ trunk/src/arch/i386/Kconfig Wed Feb 24 14:58:23 2010 (r5157) @@ -49,6 +49,24 @@ default n if TINY_BOOTBLOCK default y +choice + prompt "Bootblock behaviour" + default BOOTBLOCK_SIMPLE + depends on TINY_BOOTBLOCK + +config BOOTBLOCK_SIMPLE + bool "Always load fallback" + +config BOOTBLOCK_NORMAL + bool "Switch to normal if CMOS says so" + +endchoice + +config BOOTBLOCK_SOURCE + string + default "bootblock_simple.c" if BOOTBLOCK_SIMPLE + default "bootblock_normal.c" if BOOTBLOCK_NORMAL + config UPDATE_IMAGE bool "Update existing coreboot.rom image" default n Copied and modified: trunk/src/arch/i386/Makefile.bootblock.inc (from r5156, trunk/src/arch/i386/Makefile.tinybootblock.inc) ============================================================================== --- trunk/src/arch/i386/Makefile.tinybootblock.inc Wed Feb 24 14:18:01 2010 (r5156, copy source) +++ trunk/src/arch/i386/Makefile.bootblock.inc Wed Feb 24 14:58:23 2010 (r5157) @@ -63,7 +63,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.c $(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@ -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/i386/init/bootblock.c $(obj)/romcc +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/i386/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(obj)/romcc $(obj)/romcc $(bootblock_romccflags) -O2 $(ROMCCFLAGS) $(INCLUDES) $< -o $@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld Modified: trunk/src/arch/i386/Makefile.inc ============================================================================== --- trunk/src/arch/i386/Makefile.inc Wed Feb 24 14:18:01 2010 (r5156) +++ trunk/src/arch/i386/Makefile.inc Wed Feb 24 14:58:23 2010 (r5157) @@ -95,7 +95,7 @@ endif ifeq ($(CONFIG_TINY_BOOTBLOCK),y) -include $(src)/arch/i386/Makefile.tinybootblock.inc +include $(src)/arch/i386/Makefile.bootblock.inc else include $(src)/arch/i386/Makefile.bigbootblock.inc endif Copied and modified: trunk/src/arch/i386/include/bootblock_common.h (from r5156, trunk/src/arch/i386/init/bootblock.c) ============================================================================== --- trunk/src/arch/i386/init/bootblock.c Wed Feb 24 14:18:01 2010 (r5156, copy source) +++ trunk/src/arch/i386/include/bootblock_common.h Wed Feb 24 14:58:23 2010 (r5157) @@ -31,17 +31,3 @@ { asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist)); } - -static void main(unsigned long bist) -{ - if (boot_cpu()) { - bootblock_northbridge_init(); - bootblock_southbridge_init(); - } - const char* target1 = "fallback/romstage"; - unsigned long entry; - entry = findstage(target1); - if (entry) call(entry, bist); - asm volatile ("1:\n\thlt\n\tjmp 1b\n\t"); -} - Copied and modified: trunk/src/arch/i386/init/bootblock_normal.c (from r5156, trunk/src/arch/i386/init/bootblock.c) ============================================================================== --- trunk/src/arch/i386/init/bootblock.c Wed Feb 24 14:18:01 2010 (r5156, copy source) +++ trunk/src/arch/i386/init/bootblock_normal.c Wed Feb 24 14:58:23 2010 (r5157) @@ -1,36 +1,8 @@ -#define __PRE_RAM__ -#if CONFIG_LOGICAL_CPUS && \ - (defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT)) -#include <cpu/x86/lapic/boot_cpu.c> -#else -#define boot_cpu(x) 1 -#endif - -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#else -static void bootblock_northbridge_init(void) { } -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#else -static void bootblock_southbridge_init(void) { } -#endif +#include <bootblock_common.h> -static unsigned long findstage(char* target) -{ - unsigned long entry; - asm volatile ( - "mov $1f, %%esp\n\t" - "jmp walkcbfs\n\t" - "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi", "esp"); - return entry; -} - -static void call(unsigned long addr, unsigned long bist) -{ - asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist)); -} +#include <arch/io.h> +#include "arch/romcc_io.h" +#include "pc80/mc146818rtc_early.c" static void main(unsigned long bist) { @@ -38,10 +10,20 @@ bootblock_northbridge_init(); bootblock_southbridge_init(); } - const char* target1 = "fallback/romstage"; + unsigned long entry; - entry = findstage(target1); + if (do_normal_boot()) + entry = findstage("normal/romstage"); + else + entry = findstage("fallback/romstage"); + if (entry) call(entry, bist); + + /* run fallback if normal can't be found */ + entry = findstage("fallback/romstage"); + if (entry) call(entry, bist); + + /* duh. we're stuck */ asm volatile ("1:\n\thlt\n\tjmp 1b\n\t"); } Copied and modified: trunk/src/arch/i386/init/bootblock_simple.c (from r5156, trunk/src/arch/i386/init/bootblock.c) ============================================================================== --- trunk/src/arch/i386/init/bootblock.c Wed Feb 24 14:18:01 2010 (r5156, copy source) +++ trunk/src/arch/i386/init/bootblock_simple.c Wed Feb 24 14:58:23 2010 (r5157) @@ -1,36 +1,4 @@ -#define __PRE_RAM__ -#if CONFIG_LOGICAL_CPUS && \ - (defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT)) -#include <cpu/x86/lapic/boot_cpu.c> -#else -#define boot_cpu(x) 1 -#endif - -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#else -static void bootblock_northbridge_init(void) { } -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#else -static void bootblock_southbridge_init(void) { } -#endif - -static unsigned long findstage(char* target) -{ - unsigned long entry; - asm volatile ( - "mov $1f, %%esp\n\t" - "jmp walkcbfs\n\t" - "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi", "esp"); - return entry; -} - -static void call(unsigned long addr, unsigned long bist) -{ - asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist)); -} +#include <bootblock_common.h> static void main(unsigned long bist) {

1 0

[commit] r5154 - trunk/src/mainboard/supermicro/h8qme_fam10
by repository service 24 Feb '10

24 Feb '10

Author: oxygene Date: Wed Feb 24 09:48:35 2010 New Revision: 5154 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5154 Log: Several fixes to the supermicro/h8qme_fam10 board, so it builds and boots correctly. Signed-off-by: Knut Kujat <knuku(a)gap.upv.es> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig trunk/src/mainboard/supermicro/h8qme_fam10/devicetree.cb trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Modified: trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig Tue Feb 23 22:43:42 2010 (r5153) +++ trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig Wed Feb 24 09:48:35 2010 (r5154) @@ -4,6 +4,7 @@ select CPU_AMD_SOCKET_F_1207 select NORTHBRIDGE_AMD_AMDFAM10 select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_AMD8132 select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_WINBOND_W83627HF select HAVE_PIRQ_TABLE @@ -49,7 +50,7 @@ config HEAP_SIZE hex - default 0xc0000 + default 0xff000 depends on BOARD_SUPERMICRO_H8QME_FAM10 config APIC_ID_OFFSET @@ -134,10 +135,15 @@ config SERIAL_CPU_INIT bool - default n + default y depends on BOARD_SUPERMICRO_H8QME_FAM10 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x1511 depends on BOARD_SUPERMICRO_H8QME_FAM10 + +config STACK_SIZE + hex + default 0x10000 + depends on BOARD_SUPERMICRO_H8QME_FAM10 Modified: trunk/src/mainboard/supermicro/h8qme_fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/devicetree.cb Tue Feb 23 22:43:42 2010 (r5153) +++ trunk/src/mainboard/supermicro/h8qme_fam10/devicetree.cb Wed Feb 24 09:48:35 2010 (r5154) @@ -27,7 +27,7 @@ io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 + device pnp 2e.3 off # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end @@ -54,52 +54,10 @@ end end end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM + device pci 1.1 on end device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master MCP55 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave MCP55 PCI-E -# device i2c 55 on end -# end +# chip drivers/generic/generic #MAC EEPROM device i2c 51 on end end @@ -111,20 +69,13 @@ device pci 5.0 on end # SATA 0 device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 6.0 on end - end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on #nec pci-x - end - device pci 0.1 on #nec pci-x - device pci 4.0 on end #scsi - device pci 4.1 on end #scsi - end + device pci 6.1 off end # AZA + device pci 7.0 on + device pci 1.0 on end end + device pci 8.0 off end + device pci 9.0 off end + device pci a.0 on end # PCI E 5 device pci b.0 on end # PCI E 4 device pci c.0 on end # PCI E 3 device pci d.0 on end # PCI E 2 @@ -142,6 +93,18 @@ device pci 18.3 on end device pci 18.4 on end device pci 19.0 on end + device pci 19.0 on end + device pci 19.0 on + chip southbridge/amd/amd8132 + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + device pci 3.0 on end + device pci 3.1 on end + end + device pci 1.1 on end + end #amd8132 + end #device pci 19.0 device pci 19.1 on end device pci 19.2 on end device pci 19.3 on end Modified: trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c Tue Feb 23 22:43:42 2010 (r5153) +++ trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c Wed Feb 24 09:48:35 2010 (r5154) @@ -94,20 +94,10 @@ pci_write_config32(dev, 0x80, dword); dword = 0xa000000b; - dword = 0x10000002; pci_write_config32(dev, 0x84, dword); } - /* 8132_1 */ - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3,1)); - res = find_resource(dev,PCI_BASE_ADDRESS_0); - smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base); - - /* 8132_2 */ - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3+1,1)); - res = find_resource(dev,PCI_BASE_ADDRESS_0); - smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base); } @@ -125,7 +115,7 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus! Not correctly assign!!*/ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0xb); /* 11 USB, OK */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0xa); /* 10 USB, OK */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x5); /* 5 IDE, OK*/ Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Tue Feb 23 22:43:42 2010 (r5153) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Wed Feb 24 09:48:35 2010 (r5154) @@ -118,8 +118,8 @@ #include "cpu/amd/quadcore/quadcore.c" #define MCP55_NUM 1 -#define MCP55_USE_NIC 1 -#define MCP55_USE_AZA 1 +#define MCP55_USE_NIC 0 +#define MCP55_USE_AZA 0 #define MCP55_PCI_E_X_0 4

4 3

Kconfig Fix for H8QME-2+.
by Knut Kujat 24 Feb '10

24 Feb '10

The attached patch does several fixes so the H8QME-2+ boards builds and boots successfully with Kconfig. I also corrected some issues regarding mptables. /Signed-off-by: Knut Kujat <knuku(a)gap.upv.es> --- /Thats all :) thx, Knut Kujat

3 3

[PATCH]fallback/normal for kconfig, selectable tinybootblock handler
by Patrick Georgi 24 Feb '10

24 Feb '10

Hi, The attached patch allows the user to select one of multiple tinybootblock handlers. It also adds a new handler that provides fallback/normal behaviour (run normal iff CMOS says so and is present). The handler doesn't work yet (at least in my tests), but should be close. I mostly push this to start a discussion on how we want that part of coreboot to work. The idea would be to install the "normal" handler and fallback images in one pass, and normal images in a later pass using the already commited update feature. More special operations in tinybootblock become possible, too - maybe "run flashrom_romstage if GPIO x is triggered", or "run images X if cpuid is X, images Y if cpuid is Y". To apply the patch, src/arch/i386/init/bootblock.c must be copied to src/arch/i386/include/tinybootblock_common.h src/arch/i386/init/tinybootblock_normal.c src/arch/i386/init/tinybootblock_simple.c and bootblock.c itself be removed (the patch does that, but your patch(1) might not delete the file properly). Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

2 1

[commit] r5156 - in trunk: . src/arch/i386
by repository service 24 Feb '10

24 Feb '10

Author: stepan Date: Wed Feb 24 14:18:01 2010 New Revision: 5156 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5156 Log: This patch fixes an issue with the wrong build rules being selected. Make is free to choose any fitting rule for a target, and so some obj-y files were compiled with initobj flags. This patch also fixes the behavior for objects being both in initobj and obj. At the moment all object rules are the same, but if we start not including all .c files in romstage.c anymore we need to define __PRE_RAM__ in the initobj rule and that's when things start breaking. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/Makefile trunk/src/arch/i386/Makefile.bigbootblock.inc trunk/src/arch/i386/Makefile.tinybootblock.inc Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Wed Feb 24 14:09:09 2010 (r5155) +++ trunk/Makefile Wed Feb 24 14:18:01 2010 (r5156) @@ -126,6 +126,10 @@ subdirs:=$(PLATFORM-y) $(BUILD-y) $(eval $(call evaluate_subdirs, modify)) +initobjs:=$(addsuffix .initobj.o, $(basename $(initobjs))) +drivers:=$(addsuffix .driver.o, $(basename $(drivers))) +smmobjs:=$(addsuffix .smmobj.o, $(basename $(smmobjs))) + allobjs:=$(foreach var, $(addsuffix s,$(types)), $($(var))) alldirs:=$(sort $(abspath $(dir $(allobjs)))) source_with_ext=$(patsubst $(obj)/%.o,src/%.$(1),$(allobjs)) @@ -160,37 +164,37 @@ endef define initobjs_c_template -$(obj)/$(1)%.o: src/$(1)%.c $(obj)/config.h +$(obj)/$(1)%.initobj.o: src/$(1)%.c $(obj)/config.h @printf " CC $$(subst $$(obj)/,,$$(@))\n" $(CC) -m32 $$(CFLAGS) -c -o $$@ $$< endef define initobjs_S_template -$(obj)/$(1)%.o: src/$(1)%.S $(obj)/config.h +$(obj)/$(1)%.initobj.o: src/$(1)%.S $(obj)/config.h @printf " CC $$(subst $$(obj)/,,$$(@))\n" $(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$< endef define drivers_c_template -$(obj)/$(1)%.o: src/$(1)%.c $(obj)/config.h +$(obj)/$(1)%.driver.o: src/$(1)%.c $(obj)/config.h @printf " CC $$(subst $$(obj)/,,$$(@))\n" $(CC) -m32 $$(CFLAGS) -c -o $$@ $$< endef define drivers_S_template -$(obj)/$(1)%.o: src/$(1)%.S +$(obj)/$(1)%.driver.o: src/$(1)%.S @printf " CC $$(subst $$(obj)/,,$$(@))\n" $(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$< endef define smmobjs_c_template -$(obj)/$(1)%.o: src/$(1)%.c +$(obj)/$(1)%.smmobj.o: src/$(1)%.c @printf " CC $$(subst $$(obj)/,,$$(@))\n" $(CC) -m32 $$(CFLAGS) -c -o $$@ $$< endef define smmobjs_S_template -$(obj)/$(1)%.o: src/$(1)%.S +$(obj)/$(1)%.smmobj.o: src/$(1)%.S @printf " CC $$(subst $$(obj)/,,$$(@))\n" $(CC) -m32 $$(CFLAGS) -c -o $$@ $$< endef Modified: trunk/src/arch/i386/Makefile.bigbootblock.inc ============================================================================== --- trunk/src/arch/i386/Makefile.bigbootblock.inc Wed Feb 24 14:09:09 2010 (r5155) +++ trunk/src/arch/i386/Makefile.bigbootblock.inc Wed Feb 24 14:18:01 2010 (r5156) @@ -22,7 +22,7 @@ @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach crt0,config.h $(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@ -$(obj)/mainboard/$(MAINBOARDDIR)/crt0.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.initobj.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $(a))/crt0.disasm $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(src)/arch/i386/init/crt0.S.lb $(obj)/crt0_includes.h Modified: trunk/src/arch/i386/Makefile.tinybootblock.inc ============================================================================== --- trunk/src/arch/i386/Makefile.tinybootblock.inc Wed Feb 24 14:09:09 2010 (r5155) +++ trunk/src/arch/i386/Makefile.tinybootblock.inc Wed Feb 24 14:18:01 2010 (r5156) @@ -95,7 +95,7 @@ mkdir -p $(obj)/romstage printf '$(foreach crt0,config.h $(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@ -$(obj)/mainboard/$(MAINBOARDDIR)/crt0.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.initobj.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $(a))/crt0.disasm $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(src)/arch/i386/init/crt0.S.lb $(obj)/romstage/crt0_includes.h

1 0

[commit] r5155 - trunk/src/northbridge/intel/e7501
by repository service 24 Feb '10

24 Feb '10

Author: stepan Date: Wed Feb 24 14:09:09 2010 New Revision: 5155 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5155 Log: Remove register pressure from e7501 driver by not indirectly referencing 0:0.0 through a struct passed all through the code. This behavior makes a lot of sense for CPUs with a memory controller built-in. But this is not the case for the e7501. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/northbridge/intel/e7501/raminit.c Modified: trunk/src/northbridge/intel/e7501/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7501/raminit.c Wed Feb 24 09:48:35 2010 (r5154) +++ trunk/src/northbridge/intel/e7501/raminit.c Wed Feb 24 14:09:09 2010 (r5155) @@ -807,8 +807,7 @@ //---------------------------------------------------------------------------------- // Function: do_ram_command -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard +// Parameters: // command - specifies the command to be sent to the DIMMs: // RAM_COMMAND_NOP - No Operation // RAM_COMMAND_PRECHARGE - Precharge all banks @@ -821,8 +820,7 @@ // Return Value: None // Description: Send the specified command to all DIMMs. // -static void do_ram_command(const struct mem_controller *ctrl, uint8_t command, - uint16_t jedec_mode_bits) +static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) { int i; uint32_t dram_controller_mode; @@ -830,10 +828,10 @@ uint16_t e7501_mode_bits = jedec_mode_bits; // Configure the RAM command - dram_controller_mode = pci_read_config32(ctrl->d0, DRC); + dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); dram_controller_mode &= 0xFFFFFF8F; dram_controller_mode |= command; - pci_write_config32(ctrl->d0, DRC, dram_controller_mode); + pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); // RAM_COMMAND_NORMAL is an exception. // It affects only the memory controller and does not need to be "sent" to the DIMMs. @@ -865,7 +863,7 @@ for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) { - uint8_t dimm_end_64M_multiple = pci_read_config8(ctrl->d0, DRB_ROW_0 + i); + uint8_t dimm_end_64M_multiple = pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i); if (dimm_end_64M_multiple > dimm_start_64M_multiple) { // This code assumes DRAM row boundaries are all set below 4 GB @@ -890,19 +888,17 @@ //---------------------------------------------------------------------------------- // Function: set_ram_mode -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// jedec_mode_bits - for mode register set & extended mode register set -// commands, bits 0-12 contain the register value in JEDEC format. +// Parameters: jedec_mode_bits - for mode register set & extended mode register set +// commands, bits 0-12 contain the register value in JEDEC format. // Return Value: None // Description: Set the mode register of all DIMMs. The proper CAS# latency // setting is added to the mode bits specified by the caller. // -static void set_ram_mode(const struct mem_controller *ctrl, uint16_t jedec_mode_bits) +static void set_ram_mode(uint16_t jedec_mode_bits) { ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK)); - uint32_t dram_cas_latency = pci_read_config32(ctrl->d0, DRT) & DRT_CAS_MASK; + uint32_t dram_cas_latency = pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK; switch (dram_cas_latency) { case DRT_CAS_2_5: @@ -918,7 +914,7 @@ break; } - do_ram_command(ctrl, RAM_COMMAND_MRS, jedec_mode_bits); + do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits); } /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ @@ -927,8 +923,7 @@ //---------------------------------------------------------------------------------- // Function: configure_dimm_row_boundaries -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard +// Parameters: // dimm_log2_num_bits - log2(number of bits) for each side of the DIMM // total_dram_64M_multiple - total DRAM in the system (as a // multiple of 64 MB) for DIMMs < dimm_index @@ -938,7 +933,7 @@ // Description: Configure the E7501's DRAM Row Boundary registers for the memory // present in the specified DIMM. // -static uint8_t configure_dimm_row_boundaries(const struct mem_controller *ctrl, +static uint8_t configure_dimm_row_boundaries( struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index) @@ -967,7 +962,7 @@ total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29)); // Configure the boundary address for the row on side 1 - pci_write_config8(ctrl->d0, DRB_ROW_0+(dimm_index<<1), total_dram_64M_multiple); + pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0+(dimm_index<<1), total_dram_64M_multiple); // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair // (as a multiple of 64 MB) to the total capacity of the system @@ -975,14 +970,14 @@ total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side2 - 29)); // Configure the boundary address for the row (if any) on side 2 - pci_write_config8(ctrl->d0, DRB_ROW_1+(dimm_index<<1), total_dram_64M_multiple); + pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1+(dimm_index<<1), total_dram_64M_multiple); // Update boundaries for rows subsequent to these. // These settings will be overridden by a subsequent call if a populated physical slot exists for(i=dimm_index+1; i<MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { - pci_write_config8(ctrl->d0, DRB_ROW_0+(i<<1), total_dram_64M_multiple); - pci_write_config8(ctrl->d0, DRB_ROW_1+(i<<1), total_dram_64M_multiple); + pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0+(i<<1), total_dram_64M_multiple); + pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1+(i<<1), total_dram_64M_multiple); } return total_dram_64M_multiple; @@ -1008,8 +1003,8 @@ // Configure the E7501's DRAM row boundaries // Start by zeroing out the temporary initial configuration - pci_write_config32(ctrl->d0, DRB_ROW_0, 0); - pci_write_config32(ctrl->d0, DRB_ROW_4, 0); + pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_0, 0); + pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_4, 0); for(i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { @@ -1030,7 +1025,7 @@ if (sz.side1 == 0) die("Bad SPD value\r\n"); - total_dram_64M_multiple = configure_dimm_row_boundaries(ctrl, sz, total_dram_64M_multiple, i); + total_dram_64M_multiple = configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i); } // Configure the Top Of Low Memory (TOLM) in the E7501 @@ -1064,7 +1059,7 @@ // Convert to high 16 bits of address uint16_t top_of_low_memory = total_dram_128M_multiple << 11; - pci_write_config16(ctrl->d0, TOLM, top_of_low_memory); + pci_write_config16(PCI_DEV(0, 0, 0), TOLM, top_of_low_memory); } else { @@ -1076,7 +1071,7 @@ // Put TOLM at 3 GB - pci_write_config16(ctrl->d0, TOLM, 0xc000); + pci_write_config16(PCI_DEV(0, 0, 0), TOLM, 0xc000); // Define a remap window to make the RAM that would appear from 3 GB - 4 GB // visible just beyond 4 GB or the end of physical memory, whichever is larger @@ -1089,25 +1084,24 @@ remap_limit = 0x40 + (total_dram_64M_multiple - 0x30) - 1; } - pci_write_config16(ctrl->d0, REMAPBASE, remap_base); - pci_write_config16(ctrl->d0, REMAPLIMIT, remap_limit); + pci_write_config16(PCI_DEV(0, 0, 0), REMAPBASE, remap_base); + pci_write_config16(PCI_DEV(0, 0, 0), REMAPLIMIT, remap_limit); } } //---------------------------------------------------------------------------------- // Function: initialize_ecc -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard +// Parameters: None // Return Value: None // Description: If we're configured to use ECC, initialize the SDRAM and // clear the E7501's ECC error flags. // -static void initialize_ecc(const struct mem_controller *ctrl) +static void initialize_ecc(void) { uint32_t dram_controller_mode; /* Test to see if ECC support is enabled */ - dram_controller_mode = pci_read_config32(ctrl->d0, DRC); + dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); dram_controller_mode >>= 20; dram_controller_mode &= 3; if (dram_controller_mode == 2) { @@ -1116,28 +1110,28 @@ RAM_DEBUG_MESSAGE("Initializing ECC state...\r\n"); /* Initialize ECC bits , use ECC zero mode (new to 7501)*/ - pci_write_config8(ctrl->d0, MCHCFGNS, 0x06); - pci_write_config8(ctrl->d0, MCHCFGNS, 0x07); + pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x06); + pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x07); // Wait for scrub cycle to complete do { - byte = pci_read_config8(ctrl->d0, MCHCFGNS); + byte = pci_read_config8(PCI_DEV(0, 0, 0), MCHCFGNS); } while ( (byte & 0x08 ) == 0); - pci_write_config8(ctrl->d0, MCHCFGNS, byte & 0xfc); + pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc); RAM_DEBUG_MESSAGE("ECC state initialized.\r\n"); /* Clear the ECC error bits */ - pci_write_config8(ctrl->d0f1, DRAM_FERR, 0x03); - pci_write_config8(ctrl->d0f1, DRAM_NERR, 0x03); + pci_write_config8(PCI_DEV(0, 0, 1), DRAM_FERR, 0x03); + pci_write_config8(PCI_DEV(0, 0, 1), DRAM_NERR, 0x03); // Clear DRAM Interface error bits (write-one-clear) - pci_write_config32(ctrl->d0f1, FERR_GLOBAL, 1<<18); - pci_write_config32(ctrl->d0f1, NERR_GLOBAL, 1<<18); + pci_write_config32(PCI_DEV(0, 0, 1), FERR_GLOBAL, 1<<18); + pci_write_config32(PCI_DEV(0, 0, 1), NERR_GLOBAL, 1<<18); // Start normal ECC scrub - pci_write_config8(ctrl->d0, MCHCFGNS, 5); + pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 5); } } @@ -1161,7 +1155,7 @@ uint8_t slowest_row_precharge = 0; uint8_t slowest_ras_cas_delay = 0; uint8_t slowest_active_to_precharge_delay = 0; - uint32_t current_cas_latency = pci_read_config32(ctrl->d0, DRT) & DRT_CAS_MASK; + uint32_t current_cas_latency = pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK; // CAS# latency must be programmed beforehand ASSERT((current_cas_latency == DRT_CAS_2_0) || (current_cas_latency == DRT_CAS_2_5)); @@ -1200,7 +1194,7 @@ // At 133 MHz, 1 clock == 7.52 ns /* Read the initial state */ - dram_timing = pci_read_config32(ctrl->d0, DRT); + dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT); /* Trp */ @@ -1260,7 +1254,7 @@ if (current_cas_latency == DRT_CAS_2_0) dram_timing |= (1<<28); // 4 clocks - pci_write_config32(ctrl->d0, DRT, dram_timing); + pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing); return; @@ -1351,10 +1345,10 @@ * cas latency I can use. */ - dram_timing = pci_read_config32(ctrl->d0, DRT); + dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT); dram_timing &= ~(DRT_CAS_MASK); - maybe_dram_read_timing = pci_read_config16(ctrl->d0, MAYBE_DRDCTL); + maybe_dram_read_timing = pci_read_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL); maybe_dram_read_timing &= 0xF00C; if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) { @@ -1363,7 +1357,7 @@ } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) { - uint32_t dram_row_attributes = pci_read_config32(ctrl->d0, DRA); + uint32_t dram_row_attributes = pci_read_config32(PCI_DEV(0, 0, 0), DRA); dram_timing |= DRT_CAS_2_5; @@ -1384,24 +1378,24 @@ else die("No CAS# latencies compatible with all DIMMs!!\r\n"); - pci_write_config32(ctrl->d0, DRT, dram_timing); + pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing); /* set master DLL reset */ - dword = pci_read_config32(ctrl->d0, 0x88); + dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); dword |= (1<<26); - pci_write_config32(ctrl->d0, 0x88, dword); + pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); dword &= 0x0c0007ff; /* patch try register 88 is undocumented tnz */ dword |= 0xd2109800; - pci_write_config32(ctrl->d0, 0x88, dword); + pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); - pci_write_config16(ctrl->d0, MAYBE_DRDCTL, maybe_dram_read_timing); + pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL, maybe_dram_read_timing); - dword = pci_read_config32(ctrl->d0, 0x88); /* reset master DLL reset */ + dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); /* reset master DLL reset */ dword &= ~(1<<26); - pci_write_config32(ctrl->d0, 0x88, dword); + pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); return; @@ -1426,7 +1420,7 @@ int i; // Initial settings - uint32_t controller_mode = pci_read_config32(ctrl->d0, DRC); + uint32_t controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); uint32_t system_refresh_mode = (controller_mode >> 8) & 7; // Code below assumes that most aggressive settings are in @@ -1507,7 +1501,7 @@ controller_mode |= (system_refresh_mode << 8); // Configure the E7501 - pci_write_config32(ctrl->d0, DRC, controller_mode); + pci_write_config32(PCI_DEV(0, 0, 0), DRC, controller_mode); } //---------------------------------------------------------------------------------- @@ -1562,23 +1556,21 @@ } /* Write the new row attributes register */ - pci_write_config32(ctrl->d0, DRA, row_attributes); + pci_write_config32(PCI_DEV(0, 0, 0), DRA, row_attributes); } //---------------------------------------------------------------------------------- // Function: enable_e7501_clocks -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see +// Parameters: dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None // Description: Enable clock signals for populated DIMM sockets and disable them // for unpopulated sockets (to reduce EMI). // -static void enable_e7501_clocks(const struct mem_controller *ctrl, uint8_t dimm_mask) +static void enable_e7501_clocks(uint8_t dimm_mask) { int i; - uint8_t clock_disable = pci_read_config8(ctrl->d0, CKDIS); + uint8_t clock_disable = pci_read_config8(PCI_DEV(0, 0, 0), CKDIS); for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { @@ -1590,7 +1582,7 @@ clock_disable |= socket_mask; // DIMM absent, disable clock } - pci_write_config8(ctrl->d0, CKDIS, clock_disable); + pci_write_config8(PCI_DEV(0, 0, 0), CKDIS, clock_disable); } @@ -1605,22 +1597,21 @@ // Return Value: None // Description: DDR Receive FIFO RE-Sync (?) // -static void RAM_RESET_DDR_PTR(const struct mem_controller *ctrl) +static void RAM_RESET_DDR_PTR(void) { uint8_t byte; - byte = pci_read_config8(ctrl->d0, 0x88); + byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88); byte |= (1 << 4); - pci_write_config8(ctrl->d0, 0x88, byte); + pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte); - byte = pci_read_config8(ctrl->d0, 0x88); + byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88); byte &= ~(1 << 4); - pci_write_config8(ctrl->d0, 0x88, byte); + pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte); } //---------------------------------------------------------------------------------- // Function: ram_set_d0f0_regs -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard +// Parameters: None // Return Value: None // Description: Set E7501 registers that are either independent of DIMM specifics, // or establish default settings that will be overridden when we @@ -1629,7 +1620,7 @@ // on the table 'constant_register_values', which are a triple of // configuration register offset, mask, and bits to set. // -static void ram_set_d0f0_regs(const struct mem_controller *ctrl) +static void ram_set_d0f0_regs(void) { int i; int num_values = ARRAY_SIZE(constant_register_values); @@ -1651,11 +1642,11 @@ // Again, not strictly an error, but flagged as a potential bug ASSERT((bits_to_mask & bits_to_set) == 0); - register_value = pci_read_config32(ctrl->d0, register_offset); + register_value = pci_read_config32(PCI_DEV(0, 0, 0), register_offset); register_value &= bits_to_mask; register_value |= bits_to_set; - pci_write_config32(ctrl->d0, register_offset, register_value); + pci_write_config32(PCI_DEV(0, 0, 0), register_offset, register_value); } } @@ -1678,8 +1669,7 @@ //---------------------------------------------------------------------------------- // Function: ram_set_rcomp_regs -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard +// Parameters: None // Return Value: None // Description: Set the E7501's (undocumented) RCOMP registers. // Per the 855PM datasheet and IXP2800 HW Initialization Reference @@ -1688,7 +1678,7 @@ // Comments below are conjecture based on apparent similarity // between the E7501 and these two chips. // -static void ram_set_rcomp_regs(const struct mem_controller *ctrl) +static void ram_set_rcomp_regs(void) { uint32_t dword; uint8_t maybe_strength_control; @@ -1696,13 +1686,13 @@ RAM_DEBUG_MESSAGE("Setting RCOMP registers.\r\n"); /*enable access to the rcomp bar*/ - dword = pci_read_config32(ctrl->d0, MAYBE_MCHTST); + dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST); dword |= (1<<22); - pci_write_config32(ctrl->d0, MAYBE_MCHTST, dword); + pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword); // Set the RCOMP MMIO base address - pci_write_config32(ctrl->d0, MAYBE_SMRBASE, RCOMP_MMIO); + pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO); // Block RCOMP updates while we configure the registers dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); @@ -1789,9 +1779,9 @@ SLOW_DOWN_IO; /*disable access to the rcomp bar */ - dword = pci_read_config32(ctrl->d0, MAYBE_MCHTST); + dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST); dword &= ~(1<<22); - pci_write_config32(ctrl->d0, MAYBE_MCHTST, dword); + pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword); } @@ -1811,7 +1801,7 @@ // static void sdram_enable(int controllers, const struct mem_controller *ctrl) { - uint8_t dimm_mask = pci_read_config16(ctrl->d0, SKPD); + uint8_t dimm_mask = pci_read_config16(PCI_DEV(0, 0, 0), SKPD); uint32_t dram_controller_mode; if (dimm_mask == 0) @@ -1828,23 +1818,23 @@ /* 3. Apply NOP */ RAM_DEBUG_MESSAGE("Ram Enable 3\r\n"); - do_ram_command(ctrl, RAM_COMMAND_NOP, 0); + do_ram_command(RAM_COMMAND_NOP, 0); EXTRA_DELAY /* 4 Precharge all */ RAM_DEBUG_MESSAGE("Ram Enable 4\r\n"); - do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0); + do_ram_command(RAM_COMMAND_PRECHARGE, 0); EXTRA_DELAY /* wait until the all banks idle state... */ /* 5. Issue EMRS to enable DLL */ RAM_DEBUG_MESSAGE("Ram Enable 5\r\n"); - do_ram_command(ctrl, RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL); + do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL); EXTRA_DELAY /* 6. Reset DLL */ RAM_DEBUG_MESSAGE("Ram Enable 6\r\n"); - set_ram_mode(ctrl, E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET); + set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET); EXTRA_DELAY /* Ensure a 200us delay between the DLL reset in step 6 and the final @@ -1856,42 +1846,42 @@ /* 7 Precharge all */ RAM_DEBUG_MESSAGE("Ram Enable 7\r\n"); - do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0); + do_ram_command(RAM_COMMAND_PRECHARGE, 0); EXTRA_DELAY /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */ RAM_DEBUG_MESSAGE("Ram Enable 8\r\n"); - do_ram_command(ctrl, RAM_COMMAND_CBR, 0); + do_ram_command(RAM_COMMAND_CBR, 0); EXTRA_DELAY - do_ram_command(ctrl, RAM_COMMAND_CBR, 0); + do_ram_command(RAM_COMMAND_CBR, 0); EXTRA_DELAY /* And for good luck 6 more CBRs */ - do_ram_command(ctrl, RAM_COMMAND_CBR, 0); + do_ram_command(RAM_COMMAND_CBR, 0); EXTRA_DELAY - do_ram_command(ctrl, RAM_COMMAND_CBR, 0); + do_ram_command(RAM_COMMAND_CBR, 0); EXTRA_DELAY - do_ram_command(ctrl, RAM_COMMAND_CBR, 0); + do_ram_command(RAM_COMMAND_CBR, 0); EXTRA_DELAY - do_ram_command(ctrl, RAM_COMMAND_CBR, 0); + do_ram_command(RAM_COMMAND_CBR, 0); EXTRA_DELAY - do_ram_command(ctrl, RAM_COMMAND_CBR, 0); + do_ram_command(RAM_COMMAND_CBR, 0); EXTRA_DELAY - do_ram_command(ctrl, RAM_COMMAND_CBR, 0); + do_ram_command(RAM_COMMAND_CBR, 0); EXTRA_DELAY /* 9 mode register set */ RAM_DEBUG_MESSAGE("Ram Enable 9\r\n"); - set_ram_mode(ctrl, E7501_SDRAM_MODE | SDRAM_MODE_NORMAL); + set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL); EXTRA_DELAY /* 10 DDR Receive FIFO RE-Sync */ RAM_DEBUG_MESSAGE("Ram Enable 10\r\n"); - RAM_RESET_DDR_PTR(ctrl); + RAM_RESET_DDR_PTR(); EXTRA_DELAY /* 11 normal operation */ RAM_DEBUG_MESSAGE("Ram Enable 11\r\n"); - do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0); + do_ram_command(RAM_COMMAND_NORMAL, 0); EXTRA_DELAY // Reconfigure the row boundaries and Top of Low Memory @@ -1899,16 +1889,16 @@ configure_e7501_ram_addresses(ctrl, dimm_mask); /* Finally enable refresh */ - dram_controller_mode = pci_read_config32(ctrl->d0, DRC); + dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); dram_controller_mode |= (1 << 29); - pci_write_config32(ctrl->d0, DRC, dram_controller_mode); + pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); EXTRA_DELAY - initialize_ecc(ctrl); + initialize_ecc(); - dram_controller_mode = pci_read_config32(ctrl->d0, DRC); /* FCS_EN */ + dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); /* FCS_EN */ dram_controller_mode |= (1<<17); // NOTE: undocumented reserved bit - pci_write_config32(ctrl->d0, DRC, dram_controller_mode); + pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\r\n"); DUMPNORTH(); @@ -1940,14 +1930,14 @@ print_debug("No usable memory for this controller\r\n"); } else { - enable_e7501_clocks(ctrl, dimm_mask); + enable_e7501_clocks(dimm_mask); RAM_DEBUG_MESSAGE("setting based on SPD data...\r\n"); configure_e7501_row_attributes(ctrl, dimm_mask); configure_e7501_dram_controller_mode(ctrl, dimm_mask); configure_e7501_cas_latency(ctrl, dimm_mask); - RAM_RESET_DDR_PTR(ctrl); + RAM_RESET_DDR_PTR(); configure_e7501_dram_timing(ctrl, dimm_mask); DO_DELAY @@ -1963,7 +1953,7 @@ // Save the dimm_mask for when sdram_enable is called, so it can call // configure_e7501_ram_addresses() without having to regenerate the bitmask // of usable DIMMs. - pci_write_config16(ctrl->d0, SKPD, dimm_mask); + pci_write_config16(PCI_DEV(0, 0, 0), SKPD, dimm_mask); } //---------------------------------------------------------------------------------- @@ -1979,8 +1969,8 @@ RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\r\n"); DUMPNORTH(); - ram_set_rcomp_regs(ctrl); - ram_set_d0f0_regs(ctrl); + ram_set_rcomp_regs(); + ram_set_d0f0_regs(); } /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/

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coreboot February 2010