coreboot January 2010

coreboot@coreboot.org

58 participants
340 discussions

KBuild Report [r5057]
by coresystems autobuild service 26 Jan '10

26 Jan '10

[1/117] a-trend/atc-6220 ok. Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [2/117] a-trend/atc-6240 ok. Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [3/117] abit/be6-ii_v2_0 ok. Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [4/117] advantech/pcm-5820 ok. Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [5/117] amd/db800 ok. Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [6/117] amd/dbm690t ok. Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/amd/dbm690t/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [7/117] amd/norwich ok. Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [8/117] amd/pistachio ok. Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/amd/pistachio/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [9/117] amd/rumba ok. Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [10/117] amd/serengeti_cheetah ok. Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/amd/serengeti_cheetah/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [11/117] amd/serengeti_cheetah_fam10 ok. Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [12/117] arima/hdama ok. Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/arima/hdama/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [13/117] artecgroup/dbe61 ok. Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [14/117] asi/mb_5blgp ok. Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [15/117] asi/mb_5blmp ok. Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [16/117] asus/a8n_e ok. Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/asus/a8n_e/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [17/117] asus/a8v-e_se ok. Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [18/117] asus/m2v-mx_se ok. Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/asus/m2v-mx_se/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x1f00000 +CONFIG_RAMBASE = 0x100000 -CONFIG_RAMTOP = 0x2000000 +CONFIG_RAMTOP = 0x200000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [19/117] asus/mew-am ok. Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [20/117] asus/mew-vm ok. Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [21/117] asus/p2b-d ok. Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [22/117] asus/p2b-ds ok. Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [23/117] asus/p2b-f ok. Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [24/117] asus/p2b ok. Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [25/117] asus/p3b-f ok. Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [26/117] axus/tc320 ok. Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [27/117] azza/pt-6ibd ok. Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [28/117] bcom/winnet100 ok. Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [29/117] bcom/winnetp680 ok. Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/bcom/winnetp680/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 [30/117] biostar/m6tba ok. Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [31/117] broadcom/blast ok. Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [32/117] compaq/deskpro_en_sff_p600 ok. Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [33/117] dell/s1850 ok. Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TTYS0_BAUD = 0x4b00 +CONFIG_TTYS0_BAUD = 0x1c200 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [34/117] digitallogic/adl855pc ok. Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [35/117] digitallogic/msm586seg ok. Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/digitallogic/msm586seg/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [36/117] digitallogic/msm800sev ok. Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [37/117] eaglelion/5bcm ok. Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [38/117] emulation/qemu-x86 ok. Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/emulation/qemu-x86/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_EMULATION_QEMU_X86 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0x8f000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [39/117] gigabyte/ga-6bxc ok. Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [40/117] gigabyte/ga_2761gxdk ok. Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [41/117] gigabyte/m57sli ok. Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/gigabyte/m57sli/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [42/117] hp/dl145_g3 ok. Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [43/117] hp/e_vectra_p2706t ok. Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [44/117] ibm/e325 ok. Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [45/117] ibm/e326 ok. Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/ibm/e326/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [46/117] iei/juki-511p ok. Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/iei/juki-511p/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [47/117] iei/nova4899r ok. Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [48/117] iei/pcisa-lx-800-r10 ok. Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [49/117] intel/d945gclf ok. Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/intel/d945gclf/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xffed8000 +CONFIG_DCACHE_RAM_BASE = 0xffdf8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [50/117] intel/eagleheights ok. Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE2 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [51/117] intel/jarrell ok. Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_REBOOT_CNT = 0x8 +CONFIG_MAX_REBOOT_CNT = 0x3 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [52/117] intel/mtarvon ok. Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [53/117] intel/truxton ok. Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_EP80579 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [54/117] intel/xe7501devkit ok. Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [55/117] iwill/dk8_htx ok. Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/iwill/dk8_htx/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc4000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_SIZE = 0xc000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [56/117] iwill/dk8s2 ok. Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [57/117] iwill/dk8x ok. Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [58/117] jetway/j7f24 ok. Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/jetway/j7f24/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [59/117] kontron/986lcd-m ok. Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/kontron/986lcd-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 [60/117] kontron/kt690 ok. Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/kontron/kt690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [61/117] lippert/frontrunner ok. Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [62/117] lippert/roadrunner-lx ok. Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [63/117] lippert/spacerunner-lx ok. Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [64/117] mitac/6513wu ok. Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [65/117] msi/ms6119 ok. Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [66/117] msi/ms6147 ok. Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [67/117] msi/ms6156 ok. Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [68/117] msi/ms6178 ok. Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [69/117] msi/ms7135 ok. Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/msi/ms7135/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [70/117] msi/ms7260 ok. Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/msi/ms7260/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [71/117] msi/ms9185 ok. Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/msi/ms9185/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [72/117] msi/ms9282 ok. Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/msi/ms9282/Config-abuild.lb ok Creating builddir...ok -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [73/117] nec/powermate2000 ok. Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [74/117] newisys/khepri ok. Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [75/117] nvidia/l1_2pvv ok. Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/nvidia/l1_2pvv/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [76/117] olpc/btest ok. Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [77/117] olpc/rev_a ok. Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [78/117] pcengines/alix1c ok. Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [79/117] rca/rm4100 ok. Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/rca/rm4100/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [80/117] roda/rk886ex ok. Processing mainboard/roda/rk886ex (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/roda/rk886ex/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES = 0x0 [81/117] soyo/sy-6ba-plus-iii ok. Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [82/117] sunw/ultra40 ok. Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [83/117] supermicro/h8dme ok. Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/supermicro/h8dme/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [84/117] supermicro/h8dmr ok. Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/supermicro/h8dmr/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [85/117] supermicro/h8dmr_fam10 ok. Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [86/117] supermicro/x6dai_g ok. Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [87/117] supermicro/x6dhe_g ok. Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [88/117] supermicro/x6dhe_g2 ok. Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [89/117] supermicro/x6dhr_ig ok. Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [90/117] supermicro/x6dhr_ig2 ok. Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [91/117] technexion/tim5690 ok. Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/technexion/tim5690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 [92/117] technexion/tim8690 ok. Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/technexion/tim8690/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [93/117] technologic/ts5300 ok. Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/technologic/ts5300/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 -CONFIG_TTYS0_BASE = 0x2f8 +CONFIG_TTYS0_BASE = 0x3f8 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [94/117] televideo/tc7020 ok. Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [95/117] thomson/ip1000 ok. Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/thomson/ip1000/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [96/117] tyan/s1846 ok. Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [97/117] tyan/s2735 ok. Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x1 +CONFIG_USE_PRINTK_IN_CAR = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [98/117] tyan/s2850 ok. Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [99/117] tyan/s2875 ok. Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [100/117] tyan/s2880 ok. Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [101/117] tyan/s2881 ok. Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [102/117] tyan/s2882 ok. Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [103/117] tyan/s2885 ok. Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [104/117] tyan/s2891 ok. Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/tyan/s2891/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [105/117] tyan/s2892 ok. Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/tyan/s2892/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [106/117] tyan/s2895 ok. Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/tyan/s2895/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 [107/117] tyan/s2912 ok. Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/tyan/s2912/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [108/117] tyan/s2912_fam10 ok. Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/tyan/s2912_fam10/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [109/117] tyan/s4880 ok. Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [110/117] tyan/s4882 ok. Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x2000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [111/117] via/epia-cn ok. Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/via/epia-cn/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [112/117] via/epia-m ok. Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/via/epia-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [113/117] via/epia-m700 ok. Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/via/epia-m700/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_SIZE = 0x2000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HEAP_SIZE = 0x5000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [114/117] via/epia-n ok. Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/via/epia-n/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN400_VIDEO_MB_128MB = 0x0 +CONFIG_CN400_VIDEO_MB_16MB = 0x0 +CONFIG_CN400_VIDEO_MB_32MB = 0x1 +CONFIG_CN400_VIDEO_MB_64MB = 0x0 +CONFIG_CN400_VIDEO_MB_8MB = 0x0 +CONFIG_CN400_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [115/117] via/epia ok. Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [116/117] via/pc2500e ok. Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/via/pc2500e/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_USE_OPTION_TABLE = 0x1 +CONFIG_USE_OPTION_TABLE = 0x0 [117/117] via/vt8454c ok. Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5057/targets/via/vt8454c/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0

1 0

Re: [coreboot] Submit patch to make e/f segment available for SeaBios
by Patrick Georgi 26 Jan '10

26 Jan '10

Am 26.01.2010 13:00, schrieb Edwin Beasant: > This patch adds e- and f-segment as an available RAM area on the AMD > lx-northbridge platforms. > > - Allows SeaBios to become resident correctly > Signed-off-by: Edwin Beasant <edwin_beasant(a)virtensys.com> I commit it with a0000-bffff excluded - not sure if they have to be left unused on geode, but it won't hurt either to do so. Also, whitespace fixes. Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Committed as r5057 Thanks, Patrick

1 0

KBuild Report [r5056]
by coresystems autobuild service 26 Jan '10

26 Jan '10

[1/117] a-trend/atc-6220 ok. Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [2/117] a-trend/atc-6240 ok. Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [3/117] abit/be6-ii_v2_0 ok. Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [4/117] advantech/pcm-5820 ok. Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [5/117] amd/db800 ok. Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [6/117] amd/dbm690t ok. Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/amd/dbm690t/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [7/117] amd/norwich ok. Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [8/117] amd/pistachio ok. Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/amd/pistachio/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [9/117] amd/rumba ok. Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [10/117] amd/serengeti_cheetah ok. Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/amd/serengeti_cheetah/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [11/117] amd/serengeti_cheetah_fam10 ok. Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [12/117] arima/hdama ok. Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/arima/hdama/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [13/117] artecgroup/dbe61 ok. Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [14/117] asi/mb_5blgp ok. Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [15/117] asi/mb_5blmp ok. Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [16/117] asus/a8n_e ok. Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/asus/a8n_e/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [17/117] asus/a8v-e_se ok. Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [18/117] asus/m2v-mx_se ok. Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/asus/m2v-mx_se/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x1f00000 +CONFIG_RAMBASE = 0x100000 -CONFIG_RAMTOP = 0x2000000 +CONFIG_RAMTOP = 0x200000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [19/117] asus/mew-am ok. Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [20/117] asus/mew-vm ok. Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [21/117] asus/p2b-d ok. Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [22/117] asus/p2b-ds ok. Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [23/117] asus/p2b-f ok. Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [24/117] asus/p2b ok. Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [25/117] asus/p3b-f ok. Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [26/117] axus/tc320 ok. Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [27/117] azza/pt-6ibd ok. Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [28/117] bcom/winnet100 ok. Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [29/117] bcom/winnetp680 ok. Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/bcom/winnetp680/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 [30/117] biostar/m6tba ok. Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [31/117] broadcom/blast ok. Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [32/117] compaq/deskpro_en_sff_p600 ok. Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [33/117] dell/s1850 ok. Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TTYS0_BAUD = 0x4b00 +CONFIG_TTYS0_BAUD = 0x1c200 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [34/117] digitallogic/adl855pc ok. Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [35/117] digitallogic/msm586seg ok. Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/digitallogic/msm586seg/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [36/117] digitallogic/msm800sev ok. Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [37/117] eaglelion/5bcm ok. Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [38/117] emulation/qemu-x86 ok. Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/emulation/qemu-x86/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_EMULATION_QEMU_X86 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0x8f000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [39/117] gigabyte/ga-6bxc ok. Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [40/117] gigabyte/ga_2761gxdk ok. Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [41/117] gigabyte/m57sli ok. Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/gigabyte/m57sli/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [42/117] hp/dl145_g3 ok. Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [43/117] hp/e_vectra_p2706t ok. Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [44/117] ibm/e325 ok. Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [45/117] ibm/e326 ok. Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/ibm/e326/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [46/117] iei/juki-511p ok. Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/iei/juki-511p/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [47/117] iei/nova4899r ok. Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [48/117] iei/pcisa-lx-800-r10 ok. Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [49/117] intel/d945gclf ok. Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/intel/d945gclf/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xffed8000 +CONFIG_DCACHE_RAM_BASE = 0xffdf8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [50/117] intel/eagleheights ok. Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE2 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [51/117] intel/jarrell ok. Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_REBOOT_CNT = 0x8 +CONFIG_MAX_REBOOT_CNT = 0x3 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [52/117] intel/mtarvon ok. Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [53/117] intel/truxton ok. Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_EP80579 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [54/117] intel/xe7501devkit ok. Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [55/117] iwill/dk8_htx ok. Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/iwill/dk8_htx/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc4000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_SIZE = 0xc000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [56/117] iwill/dk8s2 ok. Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [57/117] iwill/dk8x ok. Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [58/117] jetway/j7f24 ok. Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/jetway/j7f24/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [59/117] kontron/986lcd-m ok. Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/kontron/986lcd-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 [60/117] kontron/kt690 ok. Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/kontron/kt690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [61/117] lippert/frontrunner ok. Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [62/117] lippert/roadrunner-lx ok. Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [63/117] lippert/spacerunner-lx ok. Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [64/117] mitac/6513wu ok. Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [65/117] msi/ms6119 ok. Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [66/117] msi/ms6147 ok. Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [67/117] msi/ms6156 ok. Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [68/117] msi/ms6178 ok. Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [69/117] msi/ms7135 ok. Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/msi/ms7135/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [70/117] msi/ms7260 ok. Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/msi/ms7260/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [71/117] msi/ms9185 ok. Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/msi/ms9185/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [72/117] msi/ms9282 ok. Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/msi/ms9282/Config-abuild.lb ok Creating builddir...ok -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [73/117] nec/powermate2000 ok. Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [74/117] newisys/khepri ok. Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [75/117] nvidia/l1_2pvv ok. Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/nvidia/l1_2pvv/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [76/117] olpc/btest ok. Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [77/117] olpc/rev_a ok. Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [78/117] pcengines/alix1c ok. Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [79/117] rca/rm4100 ok. Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/rca/rm4100/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [80/117] roda/rk886ex ok. Processing mainboard/roda/rk886ex (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/roda/rk886ex/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES = 0x0 [81/117] soyo/sy-6ba-plus-iii ok. Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [82/117] sunw/ultra40 ok. Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [83/117] supermicro/h8dme ok. Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/supermicro/h8dme/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [84/117] supermicro/h8dmr ok. Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/supermicro/h8dmr/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [85/117] supermicro/h8dmr_fam10 ok. Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [86/117] supermicro/x6dai_g ok. Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [87/117] supermicro/x6dhe_g ok. Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [88/117] supermicro/x6dhe_g2 ok. Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [89/117] supermicro/x6dhr_ig ok. Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [90/117] supermicro/x6dhr_ig2 ok. Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [91/117] technexion/tim5690 ok. Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/technexion/tim5690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 [92/117] technexion/tim8690 ok. Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/technexion/tim8690/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [93/117] technologic/ts5300 ok. Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/technologic/ts5300/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 -CONFIG_TTYS0_BASE = 0x2f8 +CONFIG_TTYS0_BASE = 0x3f8 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [94/117] televideo/tc7020 ok. Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [95/117] thomson/ip1000 ok. Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/thomson/ip1000/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [96/117] tyan/s1846 ok. Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [97/117] tyan/s2735 ok. Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x1 +CONFIG_USE_PRINTK_IN_CAR = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [98/117] tyan/s2850 ok. Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [99/117] tyan/s2875 ok. Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [100/117] tyan/s2880 ok. Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [101/117] tyan/s2881 ok. Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [102/117] tyan/s2882 ok. Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [103/117] tyan/s2885 ok. Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [104/117] tyan/s2891 ok. Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/tyan/s2891/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [105/117] tyan/s2892 ok. Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/tyan/s2892/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [106/117] tyan/s2895 ok. Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/tyan/s2895/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 [107/117] tyan/s2912 ok. Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/tyan/s2912/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [108/117] tyan/s2912_fam10 ok. Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/tyan/s2912_fam10/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [109/117] tyan/s4880 ok. Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [110/117] tyan/s4882 ok. Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x2000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [111/117] via/epia-cn ok. Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/via/epia-cn/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [112/117] via/epia-m ok. Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/via/epia-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [113/117] via/epia-m700 ok. Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/via/epia-m700/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_SIZE = 0x2000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HEAP_SIZE = 0x5000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [114/117] via/epia-n ok. Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/via/epia-n/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN400_VIDEO_MB_128MB = 0x0 +CONFIG_CN400_VIDEO_MB_16MB = 0x0 +CONFIG_CN400_VIDEO_MB_32MB = 0x1 +CONFIG_CN400_VIDEO_MB_64MB = 0x0 +CONFIG_CN400_VIDEO_MB_8MB = 0x0 +CONFIG_CN400_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [115/117] via/epia ok. Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [116/117] via/pc2500e ok. Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/via/pc2500e/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_USE_OPTION_TABLE = 0x1 +CONFIG_USE_OPTION_TABLE = 0x0 [117/117] via/vt8454c ok. Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5056/targets/via/vt8454c/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0

1 0

[commit] r5056 - trunk/util/mptable
by svn＠coreboot.org 26 Jan '10

26 Jan '10

Author: stepan Date: 2010-01-26 15:09:30 +0100 (Tue, 26 Jan 2010) New Revision: 5056 Modified: trunk/util/mptable/Makefile trunk/util/mptable/mptable.c Log: use stdint types for structures, and don't use pointers for fields defined 32bit in the multi processor specification. Also, fix lots of trivial warnings in the code. If you ever wondered, why you get odd or wrong mp tables on your x64 system: It's not because bios vendors neglected mp tables; it's because we neglected 64bit systems. ;-) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/mptable/Makefile =================================================================== --- trunk/util/mptable/Makefile 2010-01-26 11:22:43 UTC (rev 5055) +++ trunk/util/mptable/Makefile 2010-01-26 14:09:30 UTC (rev 5056) @@ -1,6 +1,8 @@ CC=gcc +CFLAGS=-O2 -Wall -Wextra -Wshadow -Wno-sign-compare -mptable: mptable.o - $(CC) -o mptable mptable.o +mptable: mptable.c + $(CC) $(CFLAGS) -o $@ $< + clean: - \rm *.o mptable + rm -f mptable Modified: trunk/util/mptable/mptable.c =================================================================== --- trunk/util/mptable/mptable.c 2010-01-26 11:22:43 UTC (rev 5055) +++ trunk/util/mptable/mptable.c 2010-01-26 14:09:30 UTC (rev 5056) @@ -27,11 +27,6 @@ * mptable.c */ -#ifndef lint -static const char rcsid[] = - "$Id$"; -#endif /* not lint */ - #define VMAJOR 2 #define VMINOR 0 #define VDELTA 15 @@ -53,6 +48,7 @@ #include <stdlib.h> #include <string.h> #include <unistd.h> +#include <stdint.h> #define SEP_LINE \ "\n-------------------------------------------------------------------------------\n" @@ -97,7 +93,7 @@ }; typedef struct BUSTYPENAME { - u_char type; + uint8_t type; char name[ 7 ]; } busTypeName; @@ -135,8 +131,8 @@ }; typedef struct TABLE_ENTRY { - u_char type; - u_char length; + uint8_t type; + uint8_t length; char name[ 32 ]; } tableEntry; @@ -158,69 +154,69 @@ /* MP Floating Pointer Structure */ typedef struct MPFPS { - char signature[ 4 ]; - void* pap; - u_char length; - u_char spec_rev; - u_char checksum; - u_char mpfb1; - u_char mpfb2; - u_char mpfb3; - u_char mpfb4; - u_char mpfb5; + uint8_t signature[ 4 ]; + uint32_t pap; + uint8_t length; + uint8_t spec_rev; + uint8_t checksum; + uint8_t mpfb1; + uint8_t mpfb2; + uint8_t mpfb3; + uint8_t mpfb4; + uint8_t mpfb5; } mpfps_t; /* MP Configuration Table Header */ typedef struct MPCTH { - char signature[ 4 ]; - u_short base_table_length; - u_char spec_rev; - u_char checksum; - u_char oem_id[ 8 ]; - u_char product_id[ 12 ]; - void* oem_table_pointer; - u_short oem_table_size; - u_short entry_count; - void* apic_address; - u_short extended_table_length; - u_char extended_table_checksum; - u_char reserved; + uint8_t signature[ 4 ]; + uint16_t base_table_length; + uint8_t spec_rev; + uint8_t checksum; + uint8_t oem_id[ 8 ]; + uint8_t product_id[ 12 ]; + uint32_t oem_table_pointer; + uint16_t oem_table_size; + uint16_t entry_count; + uint32_t apic_address; + uint16_t extended_table_length; + uint8_t extended_table_checksum; + uint8_t reserved; } mpcth_t; typedef struct PROCENTRY { - u_char type; - u_char apicID; - u_char apicVersion; - u_char cpuFlags; - u_long cpuSignature; - u_long featureFlags; - u_long reserved1; - u_long reserved2; + uint8_t type; + uint8_t apicID; + uint8_t apicVersion; + uint8_t cpuFlags; + uint32_t cpuSignature; + uint32_t featureFlags; + uint32_t reserved1; + uint32_t reserved2; } ProcEntry; typedef struct BUSENTRY { - u_char type; - u_char busID; - char busType[ 6 ]; + uint8_t type; + uint8_t busID; + uint8_t busType[ 6 ]; } BusEntry; typedef struct IOAPICENTRY { - u_char type; - u_char apicID; - u_char apicVersion; - u_char apicFlags; - void* apicAddress; + uint8_t type; + uint8_t apicID; + uint8_t apicVersion; + uint8_t apicFlags; + uint32_t apicAddress; } IOApicEntry; typedef struct INTENTRY { - u_char type; - u_char intType; - u_short intFlags; - u_char srcBusID; - u_char srcBusIRQ; - u_char dstApicID; - u_char dstApicINT; + uint8_t type; + uint8_t intType; + uint16_t intFlags; + uint8_t srcBusID; + uint8_t srcBusIRQ; + uint8_t dstApicID; + uint8_t dstApicINT; } IntEntry; @@ -229,42 +225,42 @@ */ typedef struct SASENTRY { - u_char type; - u_char length; - u_char busID; - u_char addressType; - u_int64_t addressBase; - u_int64_t addressLength; + uint8_t type; + uint8_t length; + uint8_t busID; + uint8_t addressType; + uint64_t addressBase; + uint64_t addressLength; } SasEntry; typedef struct BHDENTRY { - u_char type; - u_char length; - u_char busID; - u_char busInfo; - u_char busParent; - u_char reserved[ 3 ]; + uint8_t type; + uint8_t length; + uint8_t busID; + uint8_t busInfo; + uint8_t busParent; + uint8_t reserved[ 3 ]; } BhdEntry; typedef struct CBASMENTRY { - u_char type; - u_char length; - u_char busID; - u_char addressMod; - u_int predefinedRange; + uint8_t type; + uint8_t length; + uint8_t busID; + uint8_t addressMod; + uint32_t predefinedRange; } CbasmEntry; -typedef unsigned long vm_offset_t; +typedef uint32_t vm_offset_t; static void apic_probe( vm_offset_t* paddr, int* where ); static void MPConfigDefault( int featureByte ); static void MPFloatingPointer( vm_offset_t paddr, int where, mpfps_t* mpfps ); -static void MPConfigTableHeader( void* pap ); +static void MPConfigTableHeader( uint32_t pap ); static int readType( void ); static void seekEntry( vm_offset_t addr ); @@ -282,7 +278,7 @@ static void doOptionList( void ); static void doDmesg( void ); -static void pnstr( char* s, int c ); +static void pnstr( uint8_t* s, int c ); /* global data */ int pfd; /* physical /dev/mem fd */ @@ -418,9 +414,6 @@ mpfps_t mpfps; int defaultConfig; - extern int optreset; - int ch; - /* announce ourselves */ if (verbose) puts( SEP_LINE2 ); @@ -432,19 +425,18 @@ /* Ron hates getopt() */ for(argc--, argv++; argc; argc--, argv++){ - char *optarg = argv[0]; - if ( strcmp( optarg, "-dmesg") == 0 ) { + if ( strcmp( argv[0], "-dmesg") == 0 ) { dmesg = 1; } else - if ( strcmp( optarg, "-help") == 0 ) + if ( strcmp( argv[0], "-help") == 0 ) { usage(); } else - if ( strcmp( optarg, "-grope") == 0 ){ + if ( strcmp( argv[0], "-grope") == 0 ){ grope = 1; - } else if ( strcmp( optarg, "-verbose") == 0 ) + } else if ( strcmp( argv[0], "-verbose") == 0 ) verbose = 1; - else if ( strcmp( optarg, "-noisy") == 0 ) + else if ( strcmp( argv[0], "-noisy") == 0 ) noisy = 1; else usage(); } @@ -787,7 +779,7 @@ * */ static void -MPConfigTableHeader( void* pap ) +MPConfigTableHeader( uint32_t pap ) { vm_offset_t paddr; mpcth_t cth; @@ -1239,8 +1231,8 @@ break; } - printf( " address base: 0x%qx\n", entry.addressBase ); - printf( " address range: 0x%qx\n", entry.addressLength ); + printf( " address base: 0x%lx\n", entry.addressBase ); + printf( " address range: 0x%lx\n", entry.addressLength ); } @@ -1315,13 +1307,13 @@ * */ static void -pnstr( char* s, int c ) +pnstr( uint8_t* s, int c ) { - char string[ MAXPNSTR + 1 ]; + uint8_t string[ MAXPNSTR + 1 ]; if ( c > MAXPNSTR ) c = MAXPNSTR; - strncpy( string, s, c ); + strncpy( (char *)string, (char *)s, c ); string[ c ] = '\0'; printf( "%s", string ); }

1 0

KBuild Report [r5055]
by coresystems autobuild service 26 Jan '10

26 Jan '10

[1/117] a-trend/atc-6220 ok. Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [2/117] a-trend/atc-6240 ok. Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [3/117] abit/be6-ii_v2_0 ok. Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [4/117] advantech/pcm-5820 ok. Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [5/117] amd/db800 ok. Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [6/117] amd/dbm690t ok. Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/amd/dbm690t/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [7/117] amd/norwich ok. Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [8/117] amd/pistachio ok. Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/amd/pistachio/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [9/117] amd/rumba ok. Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [10/117] amd/serengeti_cheetah ok. Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/amd/serengeti_cheetah/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [11/117] amd/serengeti_cheetah_fam10 ok. Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [12/117] arima/hdama ok. Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/arima/hdama/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [13/117] artecgroup/dbe61 ok. Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [14/117] asi/mb_5blgp ok. Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [15/117] asi/mb_5blmp ok. Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [16/117] asus/a8n_e ok. Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/asus/a8n_e/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [17/117] asus/a8v-e_se ok. Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [18/117] asus/m2v-mx_se ok. Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/asus/m2v-mx_se/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x1f00000 +CONFIG_RAMBASE = 0x100000 -CONFIG_RAMTOP = 0x2000000 +CONFIG_RAMTOP = 0x200000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [19/117] asus/mew-am ok. Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [20/117] asus/mew-vm ok. Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [21/117] asus/p2b-d ok. Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [22/117] asus/p2b-ds ok. Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [23/117] asus/p2b-f ok. Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [24/117] asus/p2b ok. Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [25/117] asus/p3b-f ok. Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [26/117] axus/tc320 ok. Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [27/117] azza/pt-6ibd ok. Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [28/117] bcom/winnet100 ok. Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [29/117] bcom/winnetp680 ok. Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/bcom/winnetp680/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 [30/117] biostar/m6tba ok. Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [31/117] broadcom/blast ok. Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [32/117] compaq/deskpro_en_sff_p600 ok. Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [33/117] dell/s1850 ok. Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TTYS0_BAUD = 0x4b00 +CONFIG_TTYS0_BAUD = 0x1c200 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [34/117] digitallogic/adl855pc ok. Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [35/117] digitallogic/msm586seg ok. Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/digitallogic/msm586seg/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [36/117] digitallogic/msm800sev ok. Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [37/117] eaglelion/5bcm ok. Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [38/117] emulation/qemu-x86 ok. Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/emulation/qemu-x86/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_EMULATION_QEMU_X86 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0x8f000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [39/117] gigabyte/ga-6bxc ok. Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [40/117] gigabyte/ga_2761gxdk ok. Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [41/117] gigabyte/m57sli ok. Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/gigabyte/m57sli/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [42/117] hp/dl145_g3 ok. Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [43/117] hp/e_vectra_p2706t ok. Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [44/117] ibm/e325 ok. Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [45/117] ibm/e326 ok. Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/ibm/e326/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [46/117] iei/juki-511p ok. Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/iei/juki-511p/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [47/117] iei/nova4899r ok. Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [48/117] iei/pcisa-lx-800-r10 ok. Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [49/117] intel/d945gclf ok. Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/intel/d945gclf/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xffed8000 +CONFIG_DCACHE_RAM_BASE = 0xffdf8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [50/117] intel/eagleheights ok. Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE2 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [51/117] intel/jarrell ok. Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_REBOOT_CNT = 0x8 +CONFIG_MAX_REBOOT_CNT = 0x3 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [52/117] intel/mtarvon ok. Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [53/117] intel/truxton ok. Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_EP80579 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [54/117] intel/xe7501devkit ok. Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [55/117] iwill/dk8_htx ok. Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/iwill/dk8_htx/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc4000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_SIZE = 0xc000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [56/117] iwill/dk8s2 ok. Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [57/117] iwill/dk8x ok. Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [58/117] jetway/j7f24 ok. Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/jetway/j7f24/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [59/117] kontron/986lcd-m ok. Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/kontron/986lcd-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 [60/117] kontron/kt690 ok. Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/kontron/kt690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [61/117] lippert/frontrunner ok. Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [62/117] lippert/roadrunner-lx ok. Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [63/117] lippert/spacerunner-lx ok. Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [64/117] mitac/6513wu ok. Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [65/117] msi/ms6119 ok. Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [66/117] msi/ms6147 ok. Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [67/117] msi/ms6156 ok. Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [68/117] msi/ms6178 ok. Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [69/117] msi/ms7135 ok. Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/msi/ms7135/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [70/117] msi/ms7260 ok. Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/msi/ms7260/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [71/117] msi/ms9185 ok. Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/msi/ms9185/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [72/117] msi/ms9282 ok. Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/msi/ms9282/Config-abuild.lb ok Creating builddir...ok -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [73/117] nec/powermate2000 ok. Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [74/117] newisys/khepri ok. Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [75/117] nvidia/l1_2pvv ok. Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/nvidia/l1_2pvv/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [76/117] olpc/btest ok. Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [77/117] olpc/rev_a ok. Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [78/117] pcengines/alix1c ok. Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [79/117] rca/rm4100 ok. Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/rca/rm4100/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [80/117] roda/rk886ex ok. Processing mainboard/roda/rk886ex (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/roda/rk886ex/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES = 0x0 [81/117] soyo/sy-6ba-plus-iii ok. Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [82/117] sunw/ultra40 ok. Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [83/117] supermicro/h8dme ok. Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/supermicro/h8dme/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [84/117] supermicro/h8dmr ok. Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/supermicro/h8dmr/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [85/117] supermicro/h8dmr_fam10 ok. Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [86/117] supermicro/x6dai_g ok. Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [87/117] supermicro/x6dhe_g ok. Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [88/117] supermicro/x6dhe_g2 ok. Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [89/117] supermicro/x6dhr_ig ok. Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [90/117] supermicro/x6dhr_ig2 ok. Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [91/117] technexion/tim5690 ok. Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/technexion/tim5690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 [92/117] technexion/tim8690 ok. Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/technexion/tim8690/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [93/117] technologic/ts5300 ok. Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/technologic/ts5300/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 -CONFIG_TTYS0_BASE = 0x2f8 +CONFIG_TTYS0_BASE = 0x3f8 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [94/117] televideo/tc7020 ok. Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [95/117] thomson/ip1000 ok. Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/thomson/ip1000/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [96/117] tyan/s1846 ok. Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [97/117] tyan/s2735 ok. Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x1 +CONFIG_USE_PRINTK_IN_CAR = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [98/117] tyan/s2850 ok. Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [99/117] tyan/s2875 ok. Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [100/117] tyan/s2880 ok. Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [101/117] tyan/s2881 ok. Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [102/117] tyan/s2882 ok. Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [103/117] tyan/s2885 ok. Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [104/117] tyan/s2891 ok. Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/tyan/s2891/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [105/117] tyan/s2892 ok. Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/tyan/s2892/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [106/117] tyan/s2895 ok. Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/tyan/s2895/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 [107/117] tyan/s2912 ok. Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/tyan/s2912/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [108/117] tyan/s2912_fam10 ok. Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/tyan/s2912_fam10/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [109/117] tyan/s4880 ok. Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [110/117] tyan/s4882 ok. Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x2000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [111/117] via/epia-cn ok. Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/via/epia-cn/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [112/117] via/epia-m ok. Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/via/epia-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [113/117] via/epia-m700 ok. Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/via/epia-m700/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_SIZE = 0x2000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HEAP_SIZE = 0x5000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [114/117] via/epia-n ok. Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/via/epia-n/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN400_VIDEO_MB_128MB = 0x0 +CONFIG_CN400_VIDEO_MB_16MB = 0x0 +CONFIG_CN400_VIDEO_MB_32MB = 0x1 +CONFIG_CN400_VIDEO_MB_64MB = 0x0 +CONFIG_CN400_VIDEO_MB_8MB = 0x0 +CONFIG_CN400_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [115/117] via/epia ok. Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [116/117] via/pc2500e ok. Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/via/pc2500e/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_USE_OPTION_TABLE = 0x1 +CONFIG_USE_OPTION_TABLE = 0x0 [117/117] via/vt8454c ok. Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5055/targets/via/vt8454c/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0

1 0

Submit patch to make e/f segment available for SeaBios
by Edwin Beasant 26 Jan '10

26 Jan '10

This patch adds e- and f-segment as an available RAM area on the AMD lx-northbridge platforms. - Allows SeaBios to become resident correctly Signed-off-by: Edwin Beasant <edwin_beasant(a)virtensys.com>

1 0

Re: [coreboot] RESUBMIT: Geode patch for trunk to fix cache flush and stack jump at copying stage.
by Patrick Georgi 26 Jan '10

26 Jan '10

Am 26.01.2010 12:15, schrieb Edwin Beasant: > Patch to fix AMD Geode LX booting of Coreboot: > > This patch introduces the following: > > - Cleaned up and commented writing of MSR’s for cache control > (Backport from v3) > > - Invalidates Cache Tags (by means of in-place rewrite of cache > data) which allows CAR data to be flushed to Ram > > - Re-enabled cache after flush of CAR to Ram > > / / > > /Signed-off-by: Edwin Beasant edwin_beasant(a)virtensys.com > <mailto:edwin_beasant@virtensys.com>/ > > --- > > > > Hope I get it right this time J > Thank you, committed as revision 5055. Patrick

1 0

[commit] r5055 - in trunk/src: cpu/amd/model_lx mainboard/amd/db800
by svn＠coreboot.org 26 Jan '10

26 Jan '10

Author: oxygene Date: 2010-01-26 12:22:43 +0100 (Tue, 26 Jan 2010) New Revision: 5055 Modified: trunk/src/cpu/amd/model_lx/cache_as_ram.inc trunk/src/mainboard/amd/db800/cache_as_ram_auto.c Log: - Clean up and comment writing of MSRs for cache control (Backport from v3) - Invalidate Cache Tags (by means of in-place rewrite of cache data) which allows CAR data to be flushed to RAM - Re-enable cache after flush of CAR to RAM Signed-off-by: Edwin Beasant <edwin_beasant(a)virtensys.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/cpu/amd/model_lx/cache_as_ram.inc =================================================================== --- trunk/src/cpu/amd/model_lx/cache_as_ram.inc 2010-01-25 15:17:11 UTC (rev 5054) +++ trunk/src/cpu/amd/model_lx/cache_as_ram.inc 2010-01-26 11:22:43 UTC (rev 5055) @@ -178,31 +178,28 @@ call cache_as_ram_main done_cache_as_ram_main: - /* If you wanted to maintain the stack in memory you would need to set the tags as dirty - so the wbinvd would push out the old stack contents to memory */ - /* Clear the cache, the following code from crt0.S.lb will setup a new stack*/ - wbinvd + /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ -/* the following code is from crt0.S.lb */ -/* This takes the place of the post-CAR funtions that the K8 uses to setup the stack and copy LB low.*/ + push %edi + mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + push %esi + mov $(CONFIG_DCACHE_RAM_BASE),%edi + mov %edi,%esi + cld + rep movsl %ds:(%esi),%es:(%edi) + pop %esi + pop %edi -#ifndef CONSOLE_DEBUG_TX_STRING - /* uses: esp, ebx, ax, dx */ -# define __CRT_CONSOLE_TX_STRING(string) \ - mov string, %ebx ; \ - CALLSP(crt_console_tx_string) + /* Clear the cache out to ram */ + wbinvd + /* re-enable the cache */ + movl %cr0, %eax + xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ + movl %eax, %cr0 -# if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) -# define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string) -# else -# define CONSOLE_DEBUG_TX_STRING(string) -# endif -#endif - /* clear boot_complete flag */ xorl %ebp, %ebp __main: - CONSOLE_DEBUG_TX_STRING($str_copying_to_ram) /* * Copy data into RAM and clear the BSS. Since these segments @@ -218,9 +215,6 @@ * Normally this is copying from FLASH ROM to RAM. */ movl %ebp, %esi - /* FIXME: look for a proper place for the stack */ - movl $0x4000000, %esp - movl %esp, %ebp pushl %esi pushl $str_coreboot_ram_name call cbfs_and_run_core Modified: trunk/src/mainboard/amd/db800/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/amd/db800/cache_as_ram_auto.c 2010-01-25 15:17:11 UTC (rev 5054) +++ trunk/src/mainboard/amd/db800/cache_as_ram_auto.c 2010-01-26 11:22:43 UTC (rev 5055) @@ -35,6 +35,7 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) #define POST_CODE(x) outb(x, 0x80) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -60,37 +61,38 @@ #include "cpu/amd/model_lx/cpureginit.c" #include "cpu/amd/model_lx/syspreinit.c" -static void msr_init(void) +struct msrinit { + u32 msrnum; + msr_t msr; + }; + +static const struct msrinit msr_table[] = { - msr_t msr; + {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB. + * Rom Properties: Write Serialize, WriteProtect. + * RomBase: 0xFFFC0 + * SysTop to RomBase Properties: Write Serialize, Cache Disable. + * SysTop: 0x000A0 + * System Memory Properties: (Write Back) */ + {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */ + {CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */ + {CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */ + + /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */ + {MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF + {MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF + {MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF + {MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF + {MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF + {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF +}; - /* Setup access to the cache for under 1MB. */ - msr.hi = 0x24fffc02; - msr.lo = 0x1000A000; /* 0-A0000 write back */ - wrmsr(CPU_RCONF_DEFAULT, msr); - msr.hi = 0x0; /* Write back */ - msr.lo = 0x0; - wrmsr(CPU_RCONF_A0_BF, msr); - wrmsr(CPU_RCONF_C0_DF, msr); - wrmsr(CPU_RCONF_E0_FF, msr); - - /* Setup access to the cache for under 640K. Note MC not setup yet. */ - msr.hi = 0x20000000; - msr.lo = 0xfff80; - wrmsr(MSR_GLIU0 + 0x20, msr); - - msr.hi = 0x20000000; - msr.lo = 0x80fffe0; - wrmsr(MSR_GLIU0 + 0x21, msr); - - msr.hi = 0x20000000; - msr.lo = 0xfff80; - wrmsr(MSR_GLIU1 + 0x20, msr); - - msr.hi = 0x20000000; - msr.lo = 0x80fffe0; - wrmsr(MSR_GLIU1 + 0x21, msr); +static void msr_init(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(msr_table); i++) + wrmsr(msr_table[i].msrnum, msr_table[i].msr); } static void mb_gpio_init(void)

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Re: [coreboot] RESUBMIT: Geode patch for trunk to fix cache flush and stack jump at copying stage.
by Patrick Georgi 26 Jan '10

26 Jan '10

Am 26.01.2010 11:58, schrieb Edwin Beasant: > > Added the code/cache setup comments and stripped whitespace changes, > hope this is to the liking of everyone J > Looks good to me, thank you! We still need your signature before we can commit it, see http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure Once this is signed off, it's also Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> (that is, I agree that this change should get in :-) ) Patrick

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Re: [coreboot] Geode patch for trunk to fix cache flush and stack jump at copying stage.
by Patrick Georgi 26 Jan '10

26 Jan '10

Thank you for your patch, it's highly appreciated! As discussed on IRC, please add some comment to each address range in the array about what kind of configuration is used for it (eg. "write-back" for 0xa0000-0xbffff). Also, we need a Sign-off before we can commit it to the repository, with which you basically state that the work was yours (or taken from "safe" sources), as some basic legal protection for the project (so we know who to blame if Award/Phoenix code managed its way into our repository ;-) ) http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure has the details on that. Regards, Patrick

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coreboot January 2010