Hello,
I've finally got my board working with Coreboot now I started to stress
test the whole system to know if it is stable. Now, when I'm trying to
test my memory with Memtest86+ it doesn't starts! instead it shows correct
information about my cpus and caches but at "Memory" there is just a 0K
and in the middle of the screen a "0K LxBIOS" what is that mean? After
waiting a few minutes I'm getting the whole screen full of rubbish symbols
and than the monitors goes off.
I already tried several versions of memtest86+ without luck. I know there
is a payload with Memtest86+ I haven't tried yet but I just don't think it
will make any difference, won't it?
THX,
Knut Kujat
7
16
Re: [coreboot] Geode patch for trunk to fix cache flush and stack jump at copying stage.
by ron minnich 25 Jan '10
by ron minnich 25 Jan '10
25 Jan '10
This looks good, I assume tested on db800 :-)
Edwin, are you the only one out there with one of these?
I think it's right but have not touched geode for a year now!
I'm ready to ack if you add comments and sign it off.
ron
1
0
Geode patch for trunk to fix cache flush and stack jump at copying stage.
by Edwin Beasant 25 Jan '10
by Edwin Beasant 25 Jan '10
25 Jan '10
1
0
[1/117] a-trend/atc-6220 ok.
Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[2/117] a-trend/atc-6240 ok.
Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[3/117] abit/be6-ii_v2_0 ok.
Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[4/117] advantech/pcm-5820 ok.
Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[5/117] amd/db800 ok.
Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[6/117] amd/dbm690t ok.
Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/amd/dbm690t/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[7/117] amd/norwich ok.
Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[8/117] amd/pistachio ok.
Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/amd/pistachio/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[9/117] amd/rumba ok.
Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[10/117] amd/serengeti_cheetah ok.
Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/amd/serengeti_cheetah/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[11/117] amd/serengeti_cheetah_fam10 ok.
Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[12/117] arima/hdama ok.
Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/arima/hdama/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[13/117] artecgroup/dbe61 ok.
Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[14/117] asi/mb_5blgp ok.
Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[15/117] asi/mb_5blmp ok.
Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[16/117] asus/a8n_e ok.
Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/asus/a8n_e/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[17/117] asus/a8v-e_se ok.
Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[18/117] asus/m2v-mx_se ok.
Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/asus/m2v-mx_se/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x1f00000
+CONFIG_RAMBASE = 0x100000
-CONFIG_RAMTOP = 0x2000000
+CONFIG_RAMTOP = 0x200000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[19/117] asus/mew-am ok.
Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[20/117] asus/mew-vm ok.
Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[21/117] asus/p2b-d ok.
Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[22/117] asus/p2b-ds ok.
Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[23/117] asus/p2b-f ok.
Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[24/117] asus/p2b ok.
Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[25/117] asus/p3b-f ok.
Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[26/117] axus/tc320 ok.
Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[27/117] azza/pt-6ibd ok.
Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[28/117] bcom/winnet100 ok.
Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[29/117] bcom/winnetp680 ok.
Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/bcom/winnetp680/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
[30/117] biostar/m6tba ok.
Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[31/117] broadcom/blast ok.
Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[32/117] compaq/deskpro_en_sff_p600 ok.
Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[33/117] dell/s1850 ok.
Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TTYS0_BAUD = 0x4b00
+CONFIG_TTYS0_BAUD = 0x1c200
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[34/117] digitallogic/adl855pc ok.
Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SMP = 0x0
+CONFIG_SMP = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[35/117] digitallogic/msm586seg ok.
Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/digitallogic/msm586seg/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_SC520 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[36/117] digitallogic/msm800sev ok.
Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[37/117] eaglelion/5bcm ok.
Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[38/117] emulation/qemu-x86 ok.
Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/emulation/qemu-x86/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_EMULATION_QEMU_X86 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0x8f000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[39/117] gigabyte/ga-6bxc ok.
Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[40/117] gigabyte/ga_2761gxdk ok.
Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[41/117] gigabyte/m57sli ok.
Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/gigabyte/m57sli/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[42/117] hp/dl145_g3 ok.
Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[43/117] hp/e_vectra_p2706t ok.
Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[44/117] ibm/e325 ok.
Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[45/117] ibm/e326 ok.
Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/ibm/e326/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[46/117] iei/juki-511p ok.
Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/iei/juki-511p/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[47/117] iei/nova4899r ok.
Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[48/117] iei/pcisa-lx-800-r10 ok.
Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[49/117] intel/d945gclf ok.
Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/intel/d945gclf/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xffed8000
+CONFIG_DCACHE_RAM_BASE = 0xffdf8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[50/117] intel/eagleheights ok.
Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE2 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[51/117] intel/jarrell ok.
Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_REBOOT_CNT = 0x8
+CONFIG_MAX_REBOOT_CNT = 0x3
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[52/117] intel/mtarvon ok.
Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[53/117] intel/truxton ok.
Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_EP80579 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[54/117] intel/xe7501devkit ok.
Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[55/117] iwill/dk8_htx ok.
Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/iwill/dk8_htx/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc4000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_SIZE = 0xc000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x80000
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[56/117] iwill/dk8s2 ok.
Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[57/117] iwill/dk8x ok.
Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[58/117] jetway/j7f24 ok.
Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/jetway/j7f24/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[59/117] kontron/986lcd-m ok.
Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/kontron/986lcd-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
[60/117] kontron/kt690 ok.
Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/kontron/kt690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[61/117] lippert/frontrunner ok.
Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[62/117] lippert/roadrunner-lx ok.
Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[63/117] lippert/spacerunner-lx ok.
Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[64/117] mitac/6513wu ok.
Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[65/117] msi/ms6119 ok.
Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[66/117] msi/ms6147 ok.
Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[67/117] msi/ms6156 ok.
Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[68/117] msi/ms6178 ok.
Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[69/117] msi/ms7135 ok.
Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/msi/ms7135/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[70/117] msi/ms7260 ok.
Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/msi/ms7260/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[71/117] msi/ms9185 ok.
Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/msi/ms9185/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[72/117] msi/ms9282 ok.
Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/msi/ms9282/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[73/117] nec/powermate2000 ok.
Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[74/117] newisys/khepri ok.
Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[75/117] nvidia/l1_2pvv ok.
Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/nvidia/l1_2pvv/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[76/117] olpc/btest ok.
Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[77/117] olpc/rev_a ok.
Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[78/117] pcengines/alix1c ok.
Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[79/117] rca/rm4100 ok.
Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/rca/rm4100/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[80/117] roda/rk886ex ok.
Processing mainboard/roda/rk886ex (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/roda/rk886ex/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES = 0x0
[81/117] soyo/sy-6ba-plus-iii ok.
Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[82/117] sunw/ultra40 ok.
Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[83/117] supermicro/h8dme ok.
Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/supermicro/h8dme/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[84/117] supermicro/h8dmr ok.
Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/supermicro/h8dmr/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[85/117] supermicro/h8dmr_fam10 ok.
Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[86/117] supermicro/x6dai_g ok.
Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[87/117] supermicro/x6dhe_g ok.
Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[88/117] supermicro/x6dhe_g2 ok.
Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[89/117] supermicro/x6dhr_ig ok.
Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[90/117] supermicro/x6dhr_ig2 ok.
Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[91/117] technexion/tim5690 ok.
Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/technexion/tim5690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
[92/117] technexion/tim8690 ok.
Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/technexion/tim8690/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[93/117] technologic/ts5300 ok.
Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/technologic/ts5300/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_SC520 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
-CONFIG_TTYS0_BASE = 0x2f8
+CONFIG_TTYS0_BASE = 0x3f8
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[94/117] televideo/tc7020 ok.
Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[95/117] thomson/ip1000 ok.
Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/thomson/ip1000/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[96/117] tyan/s1846 ok.
Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[97/117] tyan/s2735 ok.
Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_USE_PRINTK_IN_CAR = 0x1
+CONFIG_USE_PRINTK_IN_CAR = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[98/117] tyan/s2850 ok.
Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[99/117] tyan/s2875 ok.
Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[100/117] tyan/s2880 ok.
Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[101/117] tyan/s2881 ok.
Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[102/117] tyan/s2882 ok.
Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[103/117] tyan/s2885 ok.
Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[104/117] tyan/s2891 ok.
Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/tyan/s2891/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[105/117] tyan/s2892 ok.
Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/tyan/s2892/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[106/117] tyan/s2895 ok.
Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/tyan/s2895/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
[107/117] tyan/s2912 ok.
Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/tyan/s2912/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[108/117] tyan/s2912_fam10 ok.
Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/tyan/s2912_fam10/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[109/117] tyan/s4880 ok.
Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[110/117] tyan/s4882 ok.
Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x2000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[111/117] via/epia-cn ok.
Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/via/epia-cn/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[112/117] via/epia-m ok.
Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/via/epia-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[113/117] via/epia-m700 ok.
Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/via/epia-m700/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_SIZE = 0x2000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HEAP_SIZE = 0x5000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[114/117] via/epia-n ok.
Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/via/epia-n/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN400_VIDEO_MB_128MB = 0x0
+CONFIG_CN400_VIDEO_MB_16MB = 0x0
+CONFIG_CN400_VIDEO_MB_32MB = 0x1
+CONFIG_CN400_VIDEO_MB_64MB = 0x0
+CONFIG_CN400_VIDEO_MB_8MB = 0x0
+CONFIG_CN400_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[115/117] via/epia ok.
Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[116/117] via/pc2500e ok.
Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/via/pc2500e/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_OPTION_TABLE = 0x1
+CONFIG_USE_OPTION_TABLE = 0x0
[117/117] via/vt8454c ok.
Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5054/targets/via/vt8454c/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
1
0
Hi,
attached patch takes care of the UDELAY configuration in kconfig. It
also fixes:
- acpi table build on a couple of boards (introduced by one of the
earlier patches)
- build error due to missing init_timer() on amd/sc520 systems
The only difference in UDELAY configuration to newconfig is via/epia
(TSC instead of IO), but given that C3 is shown to support TSC on other
boards, I preferred more regular configurations.
Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>
2
1
[1/117] a-trend/atc-6220 ok.
Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[2/117] a-trend/atc-6240 ok.
Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[3/117] abit/be6-ii_v2_0 ok.
Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[4/117] advantech/pcm-5820 ok.
Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[5/117] amd/db800 ok.
Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[6/117] amd/dbm690t ok.
Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/amd/dbm690t/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[7/117] amd/norwich ok.
Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[8/117] amd/pistachio ok.
Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/amd/pistachio/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[9/117] amd/rumba ok.
Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[10/117] amd/serengeti_cheetah fail.
[11/117] amd/serengeti_cheetah_fam10 ok.
Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[12/117] arima/hdama ok.
Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/arima/hdama/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[13/117] artecgroup/dbe61 ok.
Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[14/117] asi/mb_5blgp ok.
Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[15/117] asi/mb_5blmp ok.
Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[16/117] asus/a8n_e ok.
Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/asus/a8n_e/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[17/117] asus/a8v-e_se ok.
Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[18/117] asus/m2v-mx_se ok.
Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/asus/m2v-mx_se/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x1f00000
+CONFIG_RAMBASE = 0x100000
-CONFIG_RAMTOP = 0x2000000
+CONFIG_RAMTOP = 0x200000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[19/117] asus/mew-am ok.
Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[20/117] asus/mew-vm ok.
Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[21/117] asus/p2b-d ok.
Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[22/117] asus/p2b-ds ok.
Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[23/117] asus/p2b-f ok.
Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[24/117] asus/p2b ok.
Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[25/117] asus/p3b-f ok.
Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[26/117] axus/tc320 ok.
Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[27/117] azza/pt-6ibd ok.
Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[28/117] bcom/winnet100 ok.
Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[29/117] bcom/winnetp680 ok.
Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/bcom/winnetp680/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
[30/117] biostar/m6tba ok.
Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[31/117] broadcom/blast ok.
Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[32/117] compaq/deskpro_en_sff_p600 ok.
Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[33/117] dell/s1850 ok.
Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TTYS0_BAUD = 0x4b00
+CONFIG_TTYS0_BAUD = 0x1c200
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[34/117] digitallogic/adl855pc ok.
Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SMP = 0x0
+CONFIG_SMP = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[35/117] digitallogic/msm586seg fail.
[36/117] digitallogic/msm800sev ok.
Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[37/117] eaglelion/5bcm ok.
Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[38/117] emulation/qemu-x86 ok.
Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/emulation/qemu-x86/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_EMULATION_QEMU_X86 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0x8f000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[39/117] gigabyte/ga-6bxc ok.
Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[40/117] gigabyte/ga_2761gxdk ok.
Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[41/117] gigabyte/m57sli ok.
Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/gigabyte/m57sli/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[42/117] hp/dl145_g3 ok.
Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[43/117] hp/e_vectra_p2706t ok.
Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[44/117] ibm/e325 ok.
Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[45/117] ibm/e326 ok.
Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/ibm/e326/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[46/117] iei/juki-511p ok.
Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/iei/juki-511p/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[47/117] iei/nova4899r ok.
Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[48/117] iei/pcisa-lx-800-r10 ok.
Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[49/117] intel/d945gclf ok.
Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/intel/d945gclf/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xffed8000
+CONFIG_DCACHE_RAM_BASE = 0xffdf8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[50/117] intel/eagleheights ok.
Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE2 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[51/117] intel/jarrell ok.
Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_REBOOT_CNT = 0x8
+CONFIG_MAX_REBOOT_CNT = 0x3
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[52/117] intel/mtarvon ok.
Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[53/117] intel/truxton ok.
Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_EP80579 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[54/117] intel/xe7501devkit ok.
Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[55/117] iwill/dk8_htx fail.
[56/117] iwill/dk8s2 ok.
Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[57/117] iwill/dk8x ok.
Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[58/117] jetway/j7f24 ok.
Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/jetway/j7f24/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[59/117] kontron/986lcd-m ok.
Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/kontron/986lcd-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
[60/117] kontron/kt690 ok.
Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/kontron/kt690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[61/117] lippert/frontrunner ok.
Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[62/117] lippert/roadrunner-lx ok.
Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[63/117] lippert/spacerunner-lx ok.
Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[64/117] mitac/6513wu ok.
Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[65/117] msi/ms6119 ok.
Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[66/117] msi/ms6147 ok.
Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[67/117] msi/ms6156 ok.
Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[68/117] msi/ms6178 ok.
Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[69/117] msi/ms7135 ok.
Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/msi/ms7135/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[70/117] msi/ms7260 ok.
Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/msi/ms7260/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[71/117] msi/ms9185 ok.
Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/msi/ms9185/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[72/117] msi/ms9282 ok.
Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/msi/ms9282/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[73/117] nec/powermate2000 ok.
Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[74/117] newisys/khepri ok.
Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[75/117] nvidia/l1_2pvv ok.
Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/nvidia/l1_2pvv/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[76/117] olpc/btest ok.
Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[77/117] olpc/rev_a ok.
Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[78/117] pcengines/alix1c ok.
Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[79/117] rca/rm4100 ok.
Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/rca/rm4100/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[80/117] roda/rk886ex ok.
Processing mainboard/roda/rk886ex (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/roda/rk886ex/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES = 0x0
[81/117] soyo/sy-6ba-plus-iii ok.
Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[82/117] sunw/ultra40 ok.
Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[83/117] supermicro/h8dme ok.
Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/supermicro/h8dme/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[84/117] supermicro/h8dmr ok.
Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/supermicro/h8dmr/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[85/117] supermicro/h8dmr_fam10 ok.
Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[86/117] supermicro/x6dai_g ok.
Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[87/117] supermicro/x6dhe_g ok.
Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[88/117] supermicro/x6dhe_g2 ok.
Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[89/117] supermicro/x6dhr_ig ok.
Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[90/117] supermicro/x6dhr_ig2 ok.
Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[91/117] technexion/tim5690 ok.
Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/technexion/tim5690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
[92/117] technexion/tim8690 ok.
Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/technexion/tim8690/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[93/117] technologic/ts5300 fail.
[94/117] televideo/tc7020 ok.
Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[95/117] thomson/ip1000 ok.
Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/thomson/ip1000/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[96/117] tyan/s1846 ok.
Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[97/117] tyan/s2735 ok.
Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_USE_PRINTK_IN_CAR = 0x1
+CONFIG_USE_PRINTK_IN_CAR = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[98/117] tyan/s2850 ok.
Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[99/117] tyan/s2875 ok.
Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[100/117] tyan/s2880 ok.
Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[101/117] tyan/s2881 ok.
Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[102/117] tyan/s2882 ok.
Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[103/117] tyan/s2885 ok.
Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[104/117] tyan/s2891 ok.
Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/tyan/s2891/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[105/117] tyan/s2892 ok.
Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/tyan/s2892/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[106/117] tyan/s2895 ok.
Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/tyan/s2895/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
[107/117] tyan/s2912 ok.
Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/tyan/s2912/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[108/117] tyan/s2912_fam10 ok.
Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/tyan/s2912_fam10/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[109/117] tyan/s4880 ok.
Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[110/117] tyan/s4882 ok.
Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x2000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[111/117] via/epia-cn ok.
Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/via/epia-cn/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[112/117] via/epia-m ok.
Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/via/epia-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
[113/117] via/epia-m700 ok.
Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/via/epia-m700/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_SIZE = 0x2000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HEAP_SIZE = 0x5000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[114/117] via/epia-n ok.
Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/via/epia-n/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN400_VIDEO_MB_128MB = 0x0
+CONFIG_CN400_VIDEO_MB_16MB = 0x0
+CONFIG_CN400_VIDEO_MB_32MB = 0x1
+CONFIG_CN400_VIDEO_MB_64MB = 0x0
+CONFIG_CN400_VIDEO_MB_8MB = 0x0
+CONFIG_CN400_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[115/117] via/epia ok.
Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[116/117] via/pc2500e ok.
Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/via/pc2500e/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_OPTION_TABLE = 0x1
+CONFIG_USE_OPTION_TABLE = 0x0
[117/117] via/vt8454c ok.
Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5053/targets/via/vt8454c/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
1
0
25 Jan '10
Author: stepan
Date: 2010-01-25 14:15:17 +0100 (Mon, 25 Jan 2010)
New Revision: 5053
Removed:
trunk/src/northbridge/intel/e7520/raminit_test.c
trunk/src/northbridge/intel/e7525/raminit_test.c
Modified:
trunk/src/northbridge/intel/e7520/Config.lb
trunk/src/northbridge/intel/e7525/Config.lb
Log:
This code was copied from amdk8 and never really made usable.
It's supposed to be a userspace regression test for ram init, but
in fact, it doesn't even execute ram init. This was suggested by
Carl-Daniel on 2009-08-27
Thus, dropping it.
Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de>
Acked-by: Stefan Reinauer <stepan(a)coresystems.de>
Modified: trunk/src/northbridge/intel/e7520/Config.lb
===================================================================
--- trunk/src/northbridge/intel/e7520/Config.lb 2010-01-25 10:50:21 UTC (rev 5052)
+++ trunk/src/northbridge/intel/e7520/Config.lb 2010-01-25 13:15:17 UTC (rev 5053)
@@ -9,8 +9,3 @@
default CONFIG_WRITE_HIGH_TABLES=1
-makerule raminit_test
- depends "$(TOP)/src/northbridge/intel/e7520/raminit_test.c"
- depends "$(TOP)/src/northbridge/intel/e7520/raminit.c"
- action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@"
-end
Deleted: trunk/src/northbridge/intel/e7520/raminit_test.c
===================================================================
--- trunk/src/northbridge/intel/e7520/raminit_test.c 2010-01-25 10:50:21 UTC (rev 5052)
+++ trunk/src/northbridge/intel/e7520/raminit_test.c 2010-01-25 13:15:17 UTC (rev 5053)
@@ -1,443 +0,0 @@
-#include <unistd.h>
-#include <limits.h>
-#include <stdint.h>
-#include <string.h>
-#include <setjmp.h>
-#include <device/pci_def.h>
-#include <stdlib.h>
-#include "e7520.h"
-
-jmp_buf end_buf;
-
-static int is_cpu_pre_c0(void)
-{
- return 0;
-}
-
-#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \
- (((BUS) & 0xFF) << 16) | \
- (((DEV) & 0x1f) << 11) | \
- (((FN) & 0x07) << 8) | \
- ((WHERE) & 0xFF))
-
-#define PCI_DEV(BUS, DEV, FN) ( \
- (((BUS) & 0xFF) << 16) | \
- (((DEV) & 0x1f) << 11) | \
- (((FN) & 0x7) << 8))
-
-#define PCI_ID(VENDOR_ID, DEVICE_ID) \
- ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
-
-typedef unsigned device_t;
-
-unsigned char pci_register[256*5*3*256];
-
-static uint8_t pci_read_config8(device_t dev, unsigned where)
-{
- unsigned addr;
- addr = dev | where;
- return pci_register[addr];
-}
-
-static uint16_t pci_read_config16(device_t dev, unsigned where)
-{
- unsigned addr;
- addr = dev | where;
- return pci_register[addr] | (pci_register[addr + 1] << 8);
-}
-
-static uint32_t pci_read_config32(device_t dev, unsigned where)
-{
- unsigned addr;
- uint32_t value;
- addr = dev | where;
- value = pci_register[addr] |
- (pci_register[addr + 1] << 8) |
- (pci_register[addr + 2] << 16) |
- (pci_register[addr + 3] << 24);
-
-#if 0
- print_debug("pcir32(");
- print_debug_hex32(addr);
- print_debug("):");
- print_debug_hex32(value);
- print_debug("\n");
-#endif
- return value;
-
-}
-
-static void pci_write_config8(device_t dev, unsigned where, uint8_t value)
-{
- unsigned addr;
- addr = dev | where;
- pci_register[addr] = value;
-}
-
-static void pci_write_config16(device_t dev, unsigned where, uint16_t value)
-{
- unsigned addr;
- addr = dev | where;
- pci_register[addr] = value & 0xff;
- pci_register[addr + 1] = (value >> 8) & 0xff;
-}
-
-static void pci_write_config32(device_t dev, unsigned where, uint32_t value)
-{
- unsigned addr;
- addr = dev | where;
- pci_register[addr] = value & 0xff;
- pci_register[addr + 1] = (value >> 8) & 0xff;
- pci_register[addr + 2] = (value >> 16) & 0xff;
- pci_register[addr + 3] = (value >> 24) & 0xff;
-
-#if 0
- print_debug("pciw32(");
- print_debug_hex32(addr);
- print_debug(", ");
- print_debug_hex32(value);
- print_debug(")\n");
-#endif
-}
-
-#define PCI_DEV_INVALID (0xffffffffU)
-static device_t pci_locate_device(unsigned pci_id, device_t dev)
-{
- for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
- unsigned int id;
- id = pci_read_config32(dev, 0);
- if (id == pci_id) {
- return dev;
- }
- }
- return PCI_DEV_INVALID;
-}
-
-
-
-
-static void uart_tx_byte(unsigned char data)
-{
- write(STDOUT_FILENO, &data, 1);
-}
-static void hlt(void)
-{
- longjmp(end_buf, 2);
-}
-#include "../../../arch/i386/lib/console.c"
-
-unsigned long log2(unsigned long x)
-{
- // assume 8 bits per byte.
- unsigned long i = 1 << (sizeof(x)*8 - 1);
- unsigned long pow = sizeof(x) * 8 - 1;
-
- if (! x) {
- static const char errmsg[] = " called with invalid parameter of 0\n";
- write(STDERR_FILENO, __func__, sizeof(__func__) - 1);
- write(STDERR_FILENO, errmsg, sizeof(errmsg) - 1);
- hlt();
- }
- for(; i > x; i >>= 1, pow--)
- ;
-
- return pow;
-}
-
-typedef struct msr_struct
-{
- unsigned lo;
- unsigned hi;
-} msr_t;
-
-static inline msr_t rdmsr(unsigned index)
-{
- msr_t result;
- result.lo = 0;
- result.hi = 0;
- return result;
-}
-
-static inline void wrmsr(unsigned index, msr_t msr)
-{
-}
-
-#include "raminit.h"
-
-#define SIO_BASE 0x2e
-
-static void hard_reset(void)
-{
- /* FIXME implement the hard reset case... */
- longjmp(end_buf, 3);
-}
-
-static void memreset_setup(void)
-{
- /* Nothing to do */
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- /* Nothing to do */
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
-
-
-static uint8_t spd_mt4lsdt464a[256] =
-{
- 0x80, 0x08, 0x04, 0x0C, 0x08, 0x01, 0x40, 0x00, 0x01, 0x70,
- 0x54, 0x00, 0x80, 0x10, 0x00, 0x01, 0x8F, 0x04, 0x06, 0x01,
- 0x01, 0x00, 0x0E, 0x75, 0x54, 0x00, 0x00, 0x0F, 0x0E, 0x0F,
-
- 0x25, 0x08, 0x15, 0x08, 0x15, 0x08, 0x00, 0x12, 0x01, 0x4E,
- 0x9C, 0xE4, 0xB7, 0x46, 0x2C, 0xFF, 0x01, 0x02, 0x03, 0x04,
- 0x05, 0x06, 0x07, 0x08, 0x09, 0x01, 0x02, 0x03, 0x04, 0x05,
- 0x06, 0x07, 0x08, 0x09, 0x00,
-};
-
-static uint8_t spd_micron_512MB_DDR333[256] =
-{
- 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x02, 0x48, 0x00, 0x04, 0x60,
- 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
- 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
- 0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x01, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x10, 0x6f, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x01, 0x33, 0x36, 0x56, 0x44, 0x44, 0x46, 0x31,
- 0x32, 0x38, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43,
- 0x33, 0x03, 0x00, 0x03, 0x23, 0x17, 0x07, 0x5a, 0xb2, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-};
-
-static uint8_t spd_micron_256MB_DDR333[256] =
-{
- 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00, 0x04, 0x60,
- 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
- 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
- 0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x3c, 0x48, 0x30, 0x23, 0x50, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x58, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x01, 0x31, 0x38, 0x56, 0x44, 0x44, 0x46, 0x36,
- 0x34, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, 0x31,
- 0x20, 0x01, 0x00, 0x03, 0x19, 0x17, 0x05, 0xb2, 0xf4, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-};
-
-#define MAX_DIMMS 16
-static uint8_t spd_data[MAX_DIMMS*256];
-
-static unsigned spd_count, spd_fail_count;
-static int spd_read_byte(unsigned device, unsigned address)
-{
- int result;
- spd_count++;
- if ((device < 0x50) || (device >= (0x50 +MAX_DIMMS))) {
- result = -1;
- }
- else {
- device -= 0x50;
-
- if (address > 256) {
- result = -1;
- }
- else if (spd_data[(device << 8) | 2] != 7) {
- result = -1;
- }
- else {
- result = spd_data[(device << 8) | address];
- }
- }
-#if 0
- print_debug("spd_read_byte(");
- print_debug_hex32(device);
- print_debug(", ");
- print_debug_hex32(address);
- print_debug(") -> ");
- print_debug_hex32(result);
- print_debug("\n");
-#endif
- if (spd_count >= spd_fail_count) {
- result = -1;
- }
- return result;
-}
-
-/* no specific code here. this should go away completely */
-static void coherent_ht_mainboard(unsigned cpus)
-{
-}
-
-#include "raminit.c"
-#include "../../../lib/generic_sdram.c"
-
-#define FIRST_CPU 1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void raminit_main(void)
-{
- /*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
- static const struct mem_controller cpu[] = {
-#if FIRST_CPU
- {
- .node_id = 0,
- .f0 = PCI_DEV(0, 0x18, 0),
- .f1 = PCI_DEV(0, 0x18, 1),
- .f2 = PCI_DEV(0, 0x18, 2),
- .f3 = PCI_DEV(0, 0x18, 3),
- .channel0 = { 0x50+0, 0x50+2, 0x50+4, 0x50+6 },
- .channel1 = { 0x50+1, 0x50+3, 0x50+5, 0x50+7 },
- },
-#endif
-#if SECOND_CPU
- {
- .node_id = 1,
- .f0 = PCI_DEV(0, 0x19, 0),
- .f1 = PCI_DEV(0, 0x19, 1),
- .f2 = PCI_DEV(0, 0x19, 2),
- .f3 = PCI_DEV(0, 0x19, 3),
- .channel0 = { 0x50+8, 0x50+10, 0x50+12, 0x50+14 },
- .channel1 = { 0x50+9, 0x50+11, 0x50+13, 0x50+15 },
- },
-#endif
- };
- console_init();
- memreset_setup();
- sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}
-
-static void reset_tests(void)
-{
- /* Clear the results of any previous tests */
- memset(pci_register, 0, sizeof(pci_register));
- memset(spd_data, 0, sizeof(spd_data));
- spd_count = 0;
- spd_fail_count = UINT_MAX;
-
- pci_write_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP,
- NBCAP_128Bit |
- NBCAP_MP| NBCAP_BIG_MP |
- /* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */
- (NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) |
- NBCAP_MEMCTRL);
-
- pci_write_config32(PCI_DEV(0, 0x19, 3), NORTHBRIDGE_CAP,
- NBCAP_128Bit |
- NBCAP_MP| NBCAP_BIG_MP |
- /* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */
- (NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) |
- NBCAP_MEMCTRL);
-
-#if 0
- pci_read_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP);
-#endif
-}
-
-static void test1(void)
-{
- reset_tests();
-
- memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
- memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
-#if 0
- memcpy(&spd_data[2*256], spd_micron_512MB_DDR333, 256);
- memcpy(&spd_data[3*256], spd_micron_512MB_DDR333, 256);
-
- memcpy(&spd_data[8*256], spd_micron_512MB_DDR333, 256);
- memcpy(&spd_data[9*256], spd_micron_512MB_DDR333, 256);
- memcpy(&spd_data[10*256], spd_micron_512MB_DDR333, 256);
- memcpy(&spd_data[11*256], spd_micron_512MB_DDR333, 256);
-#endif
-
- raminit_main();
-
-#if 0
- print_debug("spd_count: ");
- print_debug_hex32(spd_count);
- print_debug("\r\n");
-#endif
-
-}
-
-
-static void do_test2(int i)
-{
- jmp_buf tmp_buf;
- memcpy(&tmp_buf, &end_buf, sizeof(end_buf));
- if (setjmp(end_buf) != 0) {
- goto done;
- }
- reset_tests();
- spd_fail_count = i;
-
- print_debug("\r\nSPD will fail after: ");
- print_debug_hex32(spd_fail_count);
- print_debug(" accesses.\r\n");
-
- memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
- memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
-
- raminit_main();
-
- done:
- memcpy(&end_buf, &tmp_buf, sizeof(end_buf));
-}
-
-static void test2(void)
-{
- int i;
- for(i = 0; i < 0x48; i++) {
- do_test2(i);
- }
-
-}
-
-int main(int argc, char **argv)
-{
- if (setjmp(end_buf) != 0) {
- return -1;
- }
- test1();
- test2();
- return 0;
-}
Modified: trunk/src/northbridge/intel/e7525/Config.lb
===================================================================
--- trunk/src/northbridge/intel/e7525/Config.lb 2010-01-25 10:50:21 UTC (rev 5052)
+++ trunk/src/northbridge/intel/e7525/Config.lb 2010-01-25 13:15:17 UTC (rev 5053)
@@ -9,8 +9,3 @@
default CONFIG_WRITE_HIGH_TABLES=1
-makerule raminit_test
- depends "$(TOP)/src/northbridge/intel/e7525/raminit_test.c"
- depends "$(TOP)/src/northbridge/intel/e7525/raminit.c"
- action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@"
-end
Deleted: trunk/src/northbridge/intel/e7525/raminit_test.c
===================================================================
--- trunk/src/northbridge/intel/e7525/raminit_test.c 2010-01-25 10:50:21 UTC (rev 5052)
+++ trunk/src/northbridge/intel/e7525/raminit_test.c 2010-01-25 13:15:17 UTC (rev 5053)
@@ -1,394 +0,0 @@
-#include <unistd.h>
-#include <limits.h>
-#include <stdint.h>
-#include <string.h>
-#include <setjmp.h>
-#include <device/pci_def.h>
-#include <stdlib.h>
-#include "e7525.h"
-
-jmp_buf end_buf;
-
-static int is_cpu_pre_c0(void)
-{
- return 0;
-}
-
-#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \
- (((BUS) & 0xFF) << 16) | \
- (((DEV) & 0x1f) << 11) | \
- (((FN) & 0x07) << 8) | \
- ((WHERE) & 0xFF))
-
-#define PCI_DEV(BUS, DEV, FN) ( \
- (((BUS) & 0xFF) << 16) | \
- (((DEV) & 0x1f) << 11) | \
- (((FN) & 0x7) << 8))
-
-#define PCI_ID(VENDOR_ID, DEVICE_ID) \
- ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
-
-typedef unsigned device_t;
-
-unsigned char pci_register[256*5*3*256];
-
-static uint8_t pci_read_config8(device_t dev, unsigned where)
-{
- unsigned addr;
- addr = dev | where;
- return pci_register[addr];
-}
-
-static uint16_t pci_read_config16(device_t dev, unsigned where)
-{
- unsigned addr;
- addr = dev | where;
- return pci_register[addr] | (pci_register[addr + 1] << 8);
-}
-
-static uint32_t pci_read_config32(device_t dev, unsigned where)
-{
- unsigned addr;
- uint32_t value;
- addr = dev | where;
- value = pci_register[addr] |
- (pci_register[addr + 1] << 8) |
- (pci_register[addr + 2] << 16) |
- (pci_register[addr + 3] << 24);
-
- return value;
-
-}
-
-static void pci_write_config8(device_t dev, unsigned where, uint8_t value)
-{
- unsigned addr;
- addr = dev | where;
- pci_register[addr] = value;
-}
-
-static void pci_write_config16(device_t dev, unsigned where, uint16_t value)
-{
- unsigned addr;
- addr = dev | where;
- pci_register[addr] = value & 0xff;
- pci_register[addr + 1] = (value >> 8) & 0xff;
-}
-
-static void pci_write_config32(device_t dev, unsigned where, uint32_t value)
-{
- unsigned addr;
- addr = dev | where;
- pci_register[addr] = value & 0xff;
- pci_register[addr + 1] = (value >> 8) & 0xff;
- pci_register[addr + 2] = (value >> 16) & 0xff;
- pci_register[addr + 3] = (value >> 24) & 0xff;
-}
-
-#define PCI_DEV_INVALID (0xffffffffU)
-static device_t pci_locate_device(unsigned pci_id, device_t dev)
-{
- for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
- unsigned int id;
- id = pci_read_config32(dev, 0);
- if (id == pci_id) {
- return dev;
- }
- }
- return PCI_DEV_INVALID;
-}
-
-
-
-
-static void uart_tx_byte(unsigned char data)
-{
- write(STDOUT_FILENO, &data, 1);
-}
-static void hlt(void)
-{
- longjmp(end_buf, 2);
-}
-#include "../../../arch/i386/lib/console.c"
-
-unsigned long log2(unsigned long x)
-{
- // assume 8 bits per byte.
- unsigned long i = 1 << (sizeof(x)*8 - 1);
- unsigned long pow = sizeof(x) * 8 - 1;
-
- if (! x) {
- static const char errmsg[] = " called with invalid parameter of 0\n";
- write(STDERR_FILENO, __func__, sizeof(__func__) - 1);
- write(STDERR_FILENO, errmsg, sizeof(errmsg) - 1);
- hlt();
- }
- for(; i > x; i >>= 1, pow--)
- ;
-
- return pow;
-}
-
-typedef struct msr_struct
-{
- unsigned lo;
- unsigned hi;
-} msr_t;
-
-static inline msr_t rdmsr(unsigned index)
-{
- msr_t result;
- result.lo = 0;
- result.hi = 0;
- return result;
-}
-
-static inline void wrmsr(unsigned index, msr_t msr)
-{
-}
-
-#include "raminit.h"
-
-#define SIO_BASE 0x2e
-
-static void hard_reset(void)
-{
- /* FIXME implement the hard reset case... */
- longjmp(end_buf, 3);
-}
-
-static void memreset_setup(void)
-{
- /* Nothing to do */
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- /* Nothing to do */
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
-
-
-static uint8_t spd_mt4lsdt464a[256] =
-{
- 0x80, 0x08, 0x04, 0x0C, 0x08, 0x01, 0x40, 0x00, 0x01, 0x70,
- 0x54, 0x00, 0x80, 0x10, 0x00, 0x01, 0x8F, 0x04, 0x06, 0x01,
- 0x01, 0x00, 0x0E, 0x75, 0x54, 0x00, 0x00, 0x0F, 0x0E, 0x0F,
-
- 0x25, 0x08, 0x15, 0x08, 0x15, 0x08, 0x00, 0x12, 0x01, 0x4E,
- 0x9C, 0xE4, 0xB7, 0x46, 0x2C, 0xFF, 0x01, 0x02, 0x03, 0x04,
- 0x05, 0x06, 0x07, 0x08, 0x09, 0x01, 0x02, 0x03, 0x04, 0x05,
- 0x06, 0x07, 0x08, 0x09, 0x00,
-};
-
-static uint8_t spd_micron_512MB_DDR333[256] =
-{
- 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x02, 0x48, 0x00, 0x04, 0x60,
- 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
- 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
- 0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x01, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x10, 0x6f, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x01, 0x33, 0x36, 0x56, 0x44, 0x44, 0x46, 0x31,
- 0x32, 0x38, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43,
- 0x33, 0x03, 0x00, 0x03, 0x23, 0x17, 0x07, 0x5a, 0xb2, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-};
-
-static uint8_t spd_micron_256MB_DDR333[256] =
-{
- 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00, 0x04, 0x60,
- 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
- 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
- 0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x3c, 0x48, 0x30, 0x23, 0x50, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x58, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x01, 0x31, 0x38, 0x56, 0x44, 0x44, 0x46, 0x36,
- 0x34, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, 0x31,
- 0x20, 0x01, 0x00, 0x03, 0x19, 0x17, 0x05, 0xb2, 0xf4, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-};
-
-#define MAX_DIMMS 16
-static uint8_t spd_data[MAX_DIMMS*256];
-
-static unsigned spd_count, spd_fail_count;
-static int spd_read_byte(unsigned device, unsigned address)
-{
- int result;
- spd_count++;
- if ((device < 0x50) || (device >= (0x50 +MAX_DIMMS))) {
- result = -1;
- }
- else {
- device -= 0x50;
-
- if (address > 256) {
- result = -1;
- }
- else if (spd_data[(device << 8) | 2] != 7) {
- result = -1;
- }
- else {
- result = spd_data[(device << 8) | address];
- }
- }
- if (spd_count >= spd_fail_count) {
- result = -1;
- }
- return result;
-}
-
-#include "raminit.c"
-#include "../../../lib/generic_sdram.c"
-
-#define FIRST_CPU 1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-#if 0
-static void raminit_main(void)
-{
- /*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
- static const struct mem_controller cpu[] = {
-#if FIRST_CPU
- {
- .node_id = 0,
- .f0 = PCI_DEV(0, 0x18, 0),
- .f1 = PCI_DEV(0, 0x18, 1),
- .f2 = PCI_DEV(0, 0x18, 2),
- .f3 = PCI_DEV(0, 0x18, 3),
- .channel0 = { 0x50+0, 0x50+2, 0x50+4, 0x50+6 },
- .channel1 = { 0x50+1, 0x50+3, 0x50+5, 0x50+7 },
- },
-#endif
-#if SECOND_CPU
- {
- .node_id = 1,
- .f0 = PCI_DEV(0, 0x19, 0),
- .f1 = PCI_DEV(0, 0x19, 1),
- .f2 = PCI_DEV(0, 0x19, 2),
- .f3 = PCI_DEV(0, 0x19, 3),
- .channel0 = { 0x50+8, 0x50+10, 0x50+12, 0x50+14 },
- .channel1 = { 0x50+9, 0x50+11, 0x50+13, 0x50+15 },
- },
-#endif
- };
- console_init();
- memreset_setup();
- sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}
-#endif
-static void reset_tests(void)
-{
- /* Clear the results of any previous tests */
- memset(pci_register, 0, sizeof(pci_register));
- memset(spd_data, 0, sizeof(spd_data));
- spd_count = 0;
- spd_fail_count = UINT_MAX;
-
- pci_write_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP,
- NBCAP_128Bit |
- NBCAP_MP| NBCAP_BIG_MP |
- /* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */
- (NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) |
- NBCAP_MEMCTRL);
-
- pci_write_config32(PCI_DEV(0, 0x19, 3), NORTHBRIDGE_CAP,
- NBCAP_128Bit |
- NBCAP_MP| NBCAP_BIG_MP |
- /* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */
- (NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) |
- NBCAP_MEMCTRL);
-}
-
-static void test1(void)
-{
- reset_tests();
-
- memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
- memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
-// raminit_main();
-}
-
-
-static void do_test2(int i)
-{
- jmp_buf tmp_buf;
- memcpy(&tmp_buf, &end_buf, sizeof(end_buf));
- if (setjmp(end_buf) != 0) {
- goto done;
- }
- reset_tests();
- spd_fail_count = i;
-
- print_debug("\r\nSPD will fail after: ");
- print_debug_hex32(spd_fail_count);
- print_debug(" accesses.\r\n");
-
- memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
- memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
-
-// raminit_main();
-
- done:
- memcpy(&end_buf, &tmp_buf, sizeof(end_buf));
-}
-
-static void test2(void)
-{
- int i;
- for(i = 0; i < 0x48; i++) {
- do_test2(i);
- }
-
-}
-
-int main(int argc, char **argv)
-{
- if (setjmp(end_buf) != 0) {
- return -1;
- }
- test1();
- test2();
- return 0;
-}
1
0
[1/117] a-trend/atc-6220 ok.
Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[2/117] a-trend/atc-6240 ok.
Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[3/117] abit/be6-ii_v2_0 ok.
Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[4/117] advantech/pcm-5820 ok.
Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[5/117] amd/db800 ok.
Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[6/117] amd/dbm690t ok.
Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/amd/dbm690t/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[7/117] amd/norwich ok.
Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[8/117] amd/pistachio ok.
Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/amd/pistachio/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[9/117] amd/rumba ok.
Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[10/117] amd/serengeti_cheetah fail.
[11/117] amd/serengeti_cheetah_fam10 ok.
Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[12/117] arima/hdama ok.
Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/arima/hdama/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[13/117] artecgroup/dbe61 ok.
Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[14/117] asi/mb_5blgp ok.
Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[15/117] asi/mb_5blmp ok.
Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[16/117] asus/a8n_e ok.
Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/asus/a8n_e/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[17/117] asus/a8v-e_se ok.
Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[18/117] asus/m2v-mx_se ok.
Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/asus/m2v-mx_se/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x1f00000
+CONFIG_RAMBASE = 0x100000
-CONFIG_RAMTOP = 0x2000000
+CONFIG_RAMTOP = 0x200000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[19/117] asus/mew-am ok.
Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[20/117] asus/mew-vm ok.
Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[21/117] asus/p2b-d ok.
Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[22/117] asus/p2b-ds ok.
Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[23/117] asus/p2b-f ok.
Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[24/117] asus/p2b ok.
Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[25/117] asus/p3b-f ok.
Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[26/117] axus/tc320 ok.
Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[27/117] azza/pt-6ibd ok.
Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[28/117] bcom/winnet100 ok.
Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[29/117] bcom/winnetp680 ok.
Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/bcom/winnetp680/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
[30/117] biostar/m6tba ok.
Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[31/117] broadcom/blast ok.
Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[32/117] compaq/deskpro_en_sff_p600 ok.
Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[33/117] dell/s1850 ok.
Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TTYS0_BAUD = 0x4b00
+CONFIG_TTYS0_BAUD = 0x1c200
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[34/117] digitallogic/adl855pc ok.
Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SMP = 0x0
+CONFIG_SMP = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[35/117] digitallogic/msm586seg fail.
[36/117] digitallogic/msm800sev ok.
Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[37/117] eaglelion/5bcm ok.
Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[38/117] emulation/qemu-x86 ok.
Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/emulation/qemu-x86/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_EMULATION_QEMU_X86 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0x8f000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[39/117] gigabyte/ga-6bxc ok.
Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[40/117] gigabyte/ga_2761gxdk ok.
Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[41/117] gigabyte/m57sli ok.
Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/gigabyte/m57sli/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[42/117] hp/dl145_g3 ok.
Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[43/117] hp/e_vectra_p2706t ok.
Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[44/117] ibm/e325 ok.
Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[45/117] ibm/e326 ok.
Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/ibm/e326/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[46/117] iei/juki-511p ok.
Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/iei/juki-511p/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[47/117] iei/nova4899r ok.
Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[48/117] iei/pcisa-lx-800-r10 ok.
Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[49/117] intel/d945gclf ok.
Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/intel/d945gclf/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xffed8000
+CONFIG_DCACHE_RAM_BASE = 0xffdf8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[50/117] intel/eagleheights ok.
Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE2 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[51/117] intel/jarrell ok.
Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_REBOOT_CNT = 0x8
+CONFIG_MAX_REBOOT_CNT = 0x3
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[52/117] intel/mtarvon ok.
Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[53/117] intel/truxton ok.
Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_EP80579 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[54/117] intel/xe7501devkit ok.
Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[55/117] iwill/dk8_htx fail.
[56/117] iwill/dk8s2 ok.
Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[57/117] iwill/dk8x ok.
Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[58/117] jetway/j7f24 ok.
Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/jetway/j7f24/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[59/117] kontron/986lcd-m ok.
Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/kontron/986lcd-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
[60/117] kontron/kt690 ok.
Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/kontron/kt690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[61/117] lippert/frontrunner ok.
Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[62/117] lippert/roadrunner-lx ok.
Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[63/117] lippert/spacerunner-lx ok.
Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[64/117] mitac/6513wu ok.
Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[65/117] msi/ms6119 ok.
Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[66/117] msi/ms6147 ok.
Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[67/117] msi/ms6156 ok.
Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[68/117] msi/ms6178 ok.
Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[69/117] msi/ms7135 ok.
Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/msi/ms7135/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[70/117] msi/ms7260 ok.
Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/msi/ms7260/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[71/117] msi/ms9185 ok.
Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/msi/ms9185/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[72/117] msi/ms9282 ok.
Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/msi/ms9282/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[73/117] nec/powermate2000 ok.
Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[74/117] newisys/khepri ok.
Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[75/117] nvidia/l1_2pvv ok.
Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/nvidia/l1_2pvv/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[76/117] olpc/btest ok.
Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[77/117] olpc/rev_a ok.
Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[78/117] pcengines/alix1c ok.
Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[79/117] rca/rm4100 ok.
Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/rca/rm4100/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[80/117] roda/rk886ex ok.
Processing mainboard/roda/rk886ex (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/roda/rk886ex/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES = 0x0
[81/117] soyo/sy-6ba-plus-iii ok.
Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[82/117] sunw/ultra40 ok.
Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[83/117] supermicro/h8dme ok.
Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/supermicro/h8dme/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[84/117] supermicro/h8dmr ok.
Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/supermicro/h8dmr/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[85/117] supermicro/h8dmr_fam10 ok.
Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[86/117] supermicro/x6dai_g ok.
Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[87/117] supermicro/x6dhe_g ok.
Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[88/117] supermicro/x6dhe_g2 ok.
Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[89/117] supermicro/x6dhr_ig ok.
Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[90/117] supermicro/x6dhr_ig2 ok.
Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[91/117] technexion/tim5690 ok.
Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/technexion/tim5690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
[92/117] technexion/tim8690 ok.
Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/technexion/tim8690/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[93/117] technologic/ts5300 fail.
[94/117] televideo/tc7020 ok.
Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[95/117] thomson/ip1000 ok.
Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/thomson/ip1000/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[96/117] tyan/s1846 ok.
Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[97/117] tyan/s2735 ok.
Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_USE_PRINTK_IN_CAR = 0x1
+CONFIG_USE_PRINTK_IN_CAR = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[98/117] tyan/s2850 ok.
Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[99/117] tyan/s2875 ok.
Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[100/117] tyan/s2880 ok.
Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[101/117] tyan/s2881 ok.
Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[102/117] tyan/s2882 ok.
Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[103/117] tyan/s2885 ok.
Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[104/117] tyan/s2891 ok.
Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/tyan/s2891/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[105/117] tyan/s2892 ok.
Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/tyan/s2892/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[106/117] tyan/s2895 ok.
Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/tyan/s2895/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
[107/117] tyan/s2912 ok.
Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/tyan/s2912/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[108/117] tyan/s2912_fam10 ok.
Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/tyan/s2912_fam10/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[109/117] tyan/s4880 ok.
Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[110/117] tyan/s4882 ok.
Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x2000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[111/117] via/epia-cn ok.
Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/via/epia-cn/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[112/117] via/epia-m ok.
Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/via/epia-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
[113/117] via/epia-m700 ok.
Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/via/epia-m700/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_SIZE = 0x2000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HEAP_SIZE = 0x5000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[114/117] via/epia-n ok.
Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/via/epia-n/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN400_VIDEO_MB_128MB = 0x0
+CONFIG_CN400_VIDEO_MB_16MB = 0x0
+CONFIG_CN400_VIDEO_MB_32MB = 0x1
+CONFIG_CN400_VIDEO_MB_64MB = 0x0
+CONFIG_CN400_VIDEO_MB_8MB = 0x0
+CONFIG_CN400_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[115/117] via/epia ok.
Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[116/117] via/pc2500e ok.
Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/via/pc2500e/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_OPTION_TABLE = 0x1
+CONFIG_USE_OPTION_TABLE = 0x0
[117/117] via/vt8454c ok.
Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5052/targets/via/vt8454c/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
1
0
Author: oxygene
Date: 2010-01-25 11:50:21 +0100 (Mon, 25 Jan 2010)
New Revision: 5052
Modified:
trunk/src/cpu/amd/socket_754/Kconfig
trunk/src/cpu/amd/socket_939/Kconfig
trunk/src/cpu/amd/socket_940/Kconfig
trunk/src/mainboard/Kconfig
trunk/src/mainboard/amd/db800/Kconfig
trunk/src/mainboard/amd/pistachio/Kconfig
trunk/src/mainboard/amd/serengeti_cheetah/Kconfig
trunk/src/mainboard/asus/a8n_e/Kconfig
trunk/src/mainboard/asus/a8v-e_se/Kconfig
trunk/src/mainboard/asus/m2v-mx_se/Kconfig
trunk/src/mainboard/broadcom/blast/Kconfig
trunk/src/mainboard/digitallogic/adl855pc/Kconfig
trunk/src/mainboard/digitallogic/msm586seg/Kconfig
trunk/src/mainboard/digitallogic/msm800sev/Kconfig
trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig
trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
trunk/src/mainboard/gigabyte/m57sli/Kconfig
trunk/src/mainboard/hp/dl145_g3/Kconfig
trunk/src/mainboard/ibm/e325/Kconfig
trunk/src/mainboard/ibm/e326/Kconfig
trunk/src/mainboard/intel/d945gclf/Kconfig
trunk/src/mainboard/intel/eagleheights/Kconfig
trunk/src/mainboard/intel/jarrell/Kconfig
trunk/src/mainboard/iwill/dk8_htx/Kconfig
trunk/src/mainboard/iwill/dk8s2/Kconfig
trunk/src/mainboard/iwill/dk8x/Kconfig
trunk/src/mainboard/msi/ms7135/Kconfig
trunk/src/mainboard/msi/ms7260/Kconfig
trunk/src/mainboard/msi/ms9185/Kconfig
trunk/src/mainboard/msi/ms9282/Kconfig
trunk/src/mainboard/newisys/khepri/Kconfig
trunk/src/mainboard/nvidia/l1_2pvv/Kconfig
trunk/src/mainboard/roda/rk886ex/Kconfig
trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig
trunk/src/mainboard/technexion/tim8690/Kconfig
trunk/src/mainboard/technologic/ts5300/Kconfig
trunk/src/mainboard/tyan/s2880/Kconfig
trunk/src/mainboard/tyan/s2881/Kconfig
trunk/src/mainboard/tyan/s2882/Kconfig
trunk/src/mainboard/tyan/s2885/Kconfig
trunk/src/mainboard/tyan/s2892/Kconfig
trunk/src/mainboard/tyan/s2912/Kconfig
trunk/src/mainboard/tyan/s4880/Kconfig
trunk/src/mainboard/tyan/s4882/Kconfig
trunk/src/mainboard/via/pc2500e/Kconfig
trunk/src/mainboard/via/vt8454c/Kconfig
trunk/util/compareboard/compareboard
Log:
More Kconfig changes to improve match with newconfig:
DIMM_SUPPORT
APIC_ID_OFFSET
ACPI_SSDTX_NUM
IRQ_SLOT_COUNT
MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
(except msi/ms9185)
MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
MEM_TRAIN_SEQ
HAVE_ACPI_RESUME
Also remove MMX (kconfig specific) and HAVE_MOVNTI and IOAPIC
(which we deliberately differ in kconfig) from compareboard
report.
Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>
Acked-by: Stefan Reinauer <stepan(a)coresystems.de>
Modified: trunk/src/cpu/amd/socket_754/Kconfig
===================================================================
--- trunk/src/cpu/amd/socket_754/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/cpu/amd/socket_754/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -6,3 +6,8 @@
hex
default 0x10
depends on CPU_AMD_SOCKET_754
+
+config DIMM_SUPPORT
+ hex
+ default 0x108
+ depends on CPU_AMD_SOCKET_754
Modified: trunk/src/cpu/amd/socket_939/Kconfig
===================================================================
--- trunk/src/cpu/amd/socket_939/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/cpu/amd/socket_939/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -6,3 +6,8 @@
hex
default 0x0
depends on CPU_AMD_SOCKET_939
+
+config DIMM_SUPPORT
+ hex
+ default 0x108
+ depends on CPU_AMD_SOCKET_939
Modified: trunk/src/cpu/amd/socket_940/Kconfig
===================================================================
--- trunk/src/cpu/amd/socket_940/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/cpu/amd/socket_940/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -7,3 +7,8 @@
hex
default 0x0
depends on CPU_AMD_SOCKET_940
+
+config DIMM_SUPPORT
+ hex
+ default 0x108
+ depends on CPU_AMD_SOCKET_940
Modified: trunk/src/mainboard/Kconfig
===================================================================
--- trunk/src/mainboard/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -287,6 +287,11 @@
default "Roda"
depends on VENDOR_RODA
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x4352
+ depends on VENDOR_RODA
+
config MAINBOARD_VENDOR
string
default "Soyo"
@@ -302,6 +307,11 @@
default "Supermicro"
depends on VENDOR_SUPERMICRO
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x15d9
+ depends on VENDOR_SUPERMICRO
+
config MAINBOARD_VENDOR
string
default "Technexion"
Modified: trunk/src/mainboard/amd/db800/Kconfig
===================================================================
--- trunk/src/mainboard/amd/db800/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/amd/db800/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -29,7 +29,7 @@
config IRQ_SLOT_COUNT
int
- default 6
+ default 4
depends on BOARD_AMD_DB800
config DCACHE_RAM_BASE
Modified: trunk/src/mainboard/amd/pistachio/Kconfig
===================================================================
--- trunk/src/mainboard/amd/pistachio/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/amd/pistachio/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -38,7 +38,7 @@
config APIC_ID_OFFSET
hex
- default 0x8
+ default 0x0
depends on BOARD_AMD_PISTACHIO
config LB_CKS_RANGE_END
Modified: trunk/src/mainboard/amd/serengeti_cheetah/Kconfig
===================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/amd/serengeti_cheetah/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -124,3 +124,7 @@
default 0x2b80
depends on BOARD_AMD_SERENGETI_CHEETAH
+config ACPI_SSDTX_NUM
+ int
+ default 1
+ depends on BOARD_AMD_SERENGETI_CHEETAH
Modified: trunk/src/mainboard/asus/a8n_e/Kconfig
===================================================================
--- trunk/src/mainboard/asus/a8n_e/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/asus/a8n_e/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -30,7 +30,7 @@
config APIC_ID_OFFSET
hex
- default 0x10
+ default 0x0
depends on BOARD_ASUS_A8N_E
config MEM_TRAIN_SEQ
Modified: trunk/src/mainboard/asus/a8v-e_se/Kconfig
===================================================================
--- trunk/src/mainboard/asus/a8v-e_se/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/asus/a8v-e_se/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -104,11 +104,6 @@
default n
depends on BOARD_ASUS_A8V_E_SE
-config IRQ_SLOT_COUNT
- int
- default 13
- depends on BOARD_ASUS_A8V_E_SE
-
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
default 0x1043
Modified: trunk/src/mainboard/asus/m2v-mx_se/Kconfig
===================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/asus/m2v-mx_se/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -32,6 +32,7 @@
select HAVE_HARD_RESET
select HAVE_OPTION_TABLE
select HAVE_ACPI_TABLES
+ select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_512
select VGA
select TINY_BOOTBLOCK
Modified: trunk/src/mainboard/broadcom/blast/Kconfig
===================================================================
--- trunk/src/mainboard/broadcom/blast/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/broadcom/blast/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -37,7 +37,7 @@
config APIC_ID_OFFSET
hex
- default 0x10
+ default 0x0
depends on BOARD_BROADCOM_BLAST
config SB_HT_CHAIN_ON_BUS0
Modified: trunk/src/mainboard/digitallogic/adl855pc/Kconfig
===================================================================
--- trunk/src/mainboard/digitallogic/adl855pc/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/digitallogic/adl855pc/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -23,8 +23,3 @@
int
default 5
depends on BOARD_DIGITALLOGIC_ADL855PC
-
-config HAVE_INIT_TIMER
- bool
- default n
- depends on BOARD_DIGITALLOGIC_ADL855PC
Modified: trunk/src/mainboard/digitallogic/msm586seg/Kconfig
===================================================================
--- trunk/src/mainboard/digitallogic/msm586seg/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/digitallogic/msm586seg/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -19,8 +19,3 @@
int
default 2
depends on BOARD_DIGITALLOGIC_MSM586SEG
-
-config HAVE_INIT_TIMER
- bool
- default n
- depends on BOARD_DIGITALLOGIC_MSM586SEG
Modified: trunk/src/mainboard/digitallogic/msm800sev/Kconfig
===================================================================
--- trunk/src/mainboard/digitallogic/msm800sev/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/digitallogic/msm800sev/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -29,7 +29,7 @@
config IRQ_SLOT_COUNT
int
- default 7
+ default 9
depends on BOARD_DIGITALLOGIC_MSM800SEV
config DCACHE_RAM_BASE
Modified: trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig
===================================================================
--- trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -46,6 +46,6 @@
config IRQ_SLOT_COUNT
int
- default 5
+ default 6
depends on BOARD_GIGABYTE_GA_6BXC
Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
===================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -36,12 +36,12 @@
config APIC_ID_OFFSET
hex
- default 16
+ default 0x10
depends on BOARD_GIGABYTE_GA_2761GXDK
config MEM_TRAIN_SEQ
int
- default 1
+ default 2
depends on BOARD_GIGABYTE_GA_2761GXDK
config SB_HT_CHAIN_ON_BUS0
Modified: trunk/src/mainboard/gigabyte/m57sli/Kconfig
===================================================================
--- trunk/src/mainboard/gigabyte/m57sli/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/gigabyte/m57sli/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -39,12 +39,12 @@
config APIC_ID_OFFSET
hex
- default 16
+ default 0x10
depends on BOARD_GIGABYTE_M57SLI
config MEM_TRAIN_SEQ
int
- default 1
+ default 2
depends on BOARD_GIGABYTE_M57SLI
config SB_HT_CHAIN_ON_BUS0
Modified: trunk/src/mainboard/hp/dl145_g3/Kconfig
===================================================================
--- trunk/src/mainboard/hp/dl145_g3/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/hp/dl145_g3/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -38,7 +38,7 @@
config APIC_ID_OFFSET
hex
- default 0x10
+ default 0x8
depends on BOARD_HP_DL145_G3
config SB_HT_CHAIN_ON_BUS0
Modified: trunk/src/mainboard/ibm/e325/Kconfig
===================================================================
--- trunk/src/mainboard/ibm/e325/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/ibm/e325/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -38,7 +38,7 @@
config APIC_ID_OFFSET
hex
- default 0x8
+ default 0x0
depends on BOARD_IBM_E325
config LB_CKS_RANGE_END
Modified: trunk/src/mainboard/ibm/e326/Kconfig
===================================================================
--- trunk/src/mainboard/ibm/e326/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/ibm/e326/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -38,7 +38,7 @@
config APIC_ID_OFFSET
hex
- default 0x8
+ default 0x0
depends on BOARD_IBM_E326
config LB_CKS_RANGE_END
Modified: trunk/src/mainboard/intel/d945gclf/Kconfig
===================================================================
--- trunk/src/mainboard/intel/d945gclf/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/intel/d945gclf/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -28,6 +28,7 @@
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
+ select HAVE_ACPI_RESUME
select MMCONF_SUPPORT
select USE_PRINTK_IN_CAR
select AP_IN_SIPI_WAIT
@@ -90,8 +91,3 @@
int
default 2
depends on BOARD_INTEL_D945GCLF
-
-config HAVE_INIT_TIMER
- bool
- default n
- depends on BOARD_INTEL_D945GCLF
Modified: trunk/src/mainboard/intel/eagleheights/Kconfig
===================================================================
--- trunk/src/mainboard/intel/eagleheights/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/intel/eagleheights/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -57,7 +57,7 @@
config IRQ_SLOT_COUNT
int
- default 18
+ default 9
depends on BOARD_INTEL_EAGLEHEIGHTS
config MAX_CPUS
Modified: trunk/src/mainboard/intel/jarrell/Kconfig
===================================================================
--- trunk/src/mainboard/intel/jarrell/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/intel/jarrell/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -40,7 +40,7 @@
config IRQ_SLOT_COUNT
int
- default 9
+ default 18
depends on BOARD_INTEL_JARRELL
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
Modified: trunk/src/mainboard/iwill/dk8_htx/Kconfig
===================================================================
--- trunk/src/mainboard/iwill/dk8_htx/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/iwill/dk8_htx/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -40,7 +40,7 @@
config APIC_ID_OFFSET
hex
- default 0x8
+ default 0x10
depends on BOARD_IWILL_DK8_HTX
config LB_CKS_RANGE_END
@@ -118,3 +118,7 @@
default 0x2b80
depends on BOARD_IWILL_DK8_HTX
+config ACPI_SSDTX_NUM
+ int
+ default 3
+ depends on BOARD_IWILL_DK8_HTX
Modified: trunk/src/mainboard/iwill/dk8s2/Kconfig
===================================================================
--- trunk/src/mainboard/iwill/dk8s2/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/iwill/dk8s2/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -39,7 +39,7 @@
config APIC_ID_OFFSET
hex
- default 0x8
+ default 0x0
depends on BOARD_IWILL_DK8S2
config LB_CKS_RANGE_END
@@ -104,7 +104,7 @@
config IRQ_SLOT_COUNT
int
- default 11
+ default 12
depends on BOARD_IWILL_DK8S2
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
Modified: trunk/src/mainboard/iwill/dk8x/Kconfig
===================================================================
--- trunk/src/mainboard/iwill/dk8x/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/iwill/dk8x/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -38,7 +38,7 @@
config APIC_ID_OFFSET
hex
- default 0x8
+ default 0x0
depends on BOARD_IWILL_DK8X
config LB_CKS_RANGE_END
@@ -103,5 +103,5 @@
config IRQ_SLOT_COUNT
int
- default 11
+ default 9
depends on BOARD_IWILL_DK8X
Modified: trunk/src/mainboard/msi/ms7135/Kconfig
===================================================================
--- trunk/src/mainboard/msi/ms7135/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/msi/ms7135/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -19,12 +19,12 @@
config APIC_ID_OFFSET
hex
- default 0x10
+ default 0x0
depends on BOARD_MSI_MS7135
config MEM_TRAIN_SEQ
int
- default 0
+ default 2
depends on BOARD_MSI_MS7135
config SB_HT_CHAIN_ON_BUS0
Modified: trunk/src/mainboard/msi/ms7260/Kconfig
===================================================================
--- trunk/src/mainboard/msi/ms7260/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/msi/ms7260/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -37,12 +37,12 @@
config APIC_ID_OFFSET
hex
- default 16
+ default 0x10
depends on BOARD_MSI_MS7260
config MEM_TRAIN_SEQ
int
- default 1
+ default 2
depends on BOARD_MSI_MS7260
config SB_HT_CHAIN_ON_BUS0
Modified: trunk/src/mainboard/msi/ms9185/Kconfig
===================================================================
--- trunk/src/mainboard/msi/ms9185/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/msi/ms9185/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -38,7 +38,7 @@
config APIC_ID_OFFSET
hex
- default 0x10
+ default 0x8
depends on BOARD_MSI_MS9185
config SB_HT_CHAIN_ON_BUS0
Modified: trunk/src/mainboard/msi/ms9282/Kconfig
===================================================================
--- trunk/src/mainboard/msi/ms9282/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/msi/ms9282/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -36,7 +36,7 @@
config APIC_ID_OFFSET
hex
- default 16
+ default 0x10
depends on BOARD_MSI_MS9282
config SB_HT_CHAIN_ON_BUS0
Modified: trunk/src/mainboard/newisys/khepri/Kconfig
===================================================================
--- trunk/src/mainboard/newisys/khepri/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/newisys/khepri/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -32,7 +32,7 @@
config APIC_ID_OFFSET
hex
- default 0x10
+ default 0x0
depends on BOARD_NEWISYS_KHEPRI
config K8_REV_F_SUPPORT
@@ -97,7 +97,7 @@
config IRQ_SLOT_COUNT
int
- default 11
+ default 9
depends on BOARD_NEWISYS_KHEPRI
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
Modified: trunk/src/mainboard/nvidia/l1_2pvv/Kconfig
===================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/nvidia/l1_2pvv/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -37,7 +37,7 @@
config APIC_ID_OFFSET
hex
- default 16
+ default 0x10
depends on BOARD_NVIDIA_L1_2PVV
config MEM_TRAIN_SEQ
Modified: trunk/src/mainboard/roda/rk886ex/Kconfig
===================================================================
--- trunk/src/mainboard/roda/rk886ex/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/roda/rk886ex/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -14,8 +14,9 @@
select USE_PRINTK_IN_CAR
select AP_IN_SIPI_WAIT
select UDELAY_LAPIC
+ select HAVE_SMI_HANDLER
select HAVE_ACPI_TABLES
- select HAVE_SMI_HANDLER
+ select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_1024
config MAINBOARD_DIR
@@ -67,3 +68,8 @@
int
default 2
depends on BOARD_RODA_RK886EX
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x6886
+ depends on BOARD_RODA_RK886EX
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -136,3 +136,8 @@
bool
default n
depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x1511
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
Modified: trunk/src/mainboard/technexion/tim8690/Kconfig
===================================================================
--- trunk/src/mainboard/technexion/tim8690/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/technexion/tim8690/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -39,7 +39,7 @@
config APIC_ID_OFFSET
hex
- default 0x8
+ default 0x0
depends on BOARD_TECHNEXION_TIM8690
config LB_CKS_RANGE_END
Modified: trunk/src/mainboard/technologic/ts5300/Kconfig
===================================================================
--- trunk/src/mainboard/technologic/ts5300/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/technologic/ts5300/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -19,8 +19,3 @@
int
default 2
depends on BOARD_TECHNOLOGIC_TS5300
-
-config HAVE_INIT_TIMER
- bool
- default n
- depends on BOARD_TECHNOLOGIC_TS5300
Modified: trunk/src/mainboard/tyan/s2880/Kconfig
===================================================================
--- trunk/src/mainboard/tyan/s2880/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/tyan/s2880/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -19,7 +19,7 @@
config APIC_ID_OFFSET
hex
- default 0x10
+ default 0x0
depends on BOARD_TYAN_S2880
config SB_HT_CHAIN_ON_BUS0
@@ -89,5 +89,5 @@
config IRQ_SLOT_COUNT
int
- default 9
+ default 13
depends on BOARD_TYAN_S2880
Modified: trunk/src/mainboard/tyan/s2881/Kconfig
===================================================================
--- trunk/src/mainboard/tyan/s2881/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/tyan/s2881/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -19,7 +19,7 @@
config APIC_ID_OFFSET
hex
- default 0x10
+ default 0x0
depends on BOARD_TYAN_S2881
config SB_HT_CHAIN_ON_BUS0
Modified: trunk/src/mainboard/tyan/s2882/Kconfig
===================================================================
--- trunk/src/mainboard/tyan/s2882/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/tyan/s2882/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -19,7 +19,7 @@
config APIC_ID_OFFSET
hex
- default 0x10
+ default 0x0
depends on BOARD_TYAN_S2882
config SB_HT_CHAIN_ON_BUS0
@@ -89,5 +89,5 @@
config IRQ_SLOT_COUNT
int
- default 9
+ default 15
depends on BOARD_TYAN_S2882
Modified: trunk/src/mainboard/tyan/s2885/Kconfig
===================================================================
--- trunk/src/mainboard/tyan/s2885/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/tyan/s2885/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -89,5 +89,5 @@
config IRQ_SLOT_COUNT
int
- default 9
+ default 11
depends on BOARD_TYAN_S2885
Modified: trunk/src/mainboard/tyan/s2892/Kconfig
===================================================================
--- trunk/src/mainboard/tyan/s2892/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/tyan/s2892/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -20,7 +20,7 @@
config APIC_ID_OFFSET
hex
- default 0x10
+ default 0x0
depends on BOARD_TYAN_S2892
config SB_HT_CHAIN_ON_BUS0
Modified: trunk/src/mainboard/tyan/s2912/Kconfig
===================================================================
--- trunk/src/mainboard/tyan/s2912/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/tyan/s2912/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -37,7 +37,7 @@
config APIC_ID_OFFSET
hex
- default 16
+ default 0x10
depends on BOARD_TYAN_S2912
config MEM_TRAIN_SEQ
@@ -139,3 +139,8 @@
int
default 11
depends on BOARD_TYAN_S2912
+
+config ACPI_SSDTX_NUM
+ int
+ default 3
+ depends on BOARD_TYAN_S2912
Modified: trunk/src/mainboard/tyan/s4880/Kconfig
===================================================================
--- trunk/src/mainboard/tyan/s4880/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/tyan/s4880/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -92,7 +92,7 @@
config IRQ_SLOT_COUNT
int
- default 11
+ default 22
depends on BOARD_TYAN_S4880
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
Modified: trunk/src/mainboard/tyan/s4882/Kconfig
===================================================================
--- trunk/src/mainboard/tyan/s4882/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/tyan/s4882/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -92,7 +92,7 @@
config IRQ_SLOT_COUNT
int
- default 11
+ default 22
depends on BOARD_TYAN_S4882
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
Modified: trunk/src/mainboard/via/pc2500e/Kconfig
===================================================================
--- trunk/src/mainboard/via/pc2500e/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/via/pc2500e/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -21,6 +21,16 @@
default "pc2500e"
depends on BOARD_VIA_PC2500E
+config DCACHE_RAM_BASE
+ hex
+ default 0xc0000
+ depends on BOARD_VIA_PC2500E
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x1000
+ depends on BOARD_VIA_PC2500E
+
config RAMBASE
hex
default 0x4000
Modified: trunk/src/mainboard/via/vt8454c/Kconfig
===================================================================
--- trunk/src/mainboard/via/vt8454c/Kconfig 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/src/mainboard/via/vt8454c/Kconfig 2010-01-25 10:50:21 UTC (rev 5052)
@@ -11,6 +11,7 @@
select USE_PRINTK_IN_CAR
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_512
+ select USE_DCACHE_RAM
config MAINBOARD_DIR
string
Modified: trunk/util/compareboard/compareboard
===================================================================
--- trunk/util/compareboard/compareboard 2010-01-25 07:56:01 UTC (rev 5051)
+++ trunk/util/compareboard/compareboard 2010-01-25 10:50:21 UTC (rev 5052)
@@ -77,6 +77,8 @@
-e "/^CONFIG_STACK_SIZE / d" \
-e "/^CONFIG_GDB_STUB / d" \
-e "/^CONFIG_VIDEO_MB / d" \
+ -e "/^CONFIG_IOAPIC / d" \
+ -e "/^CONFIG_HAVE_MOVNTI / d" \
-e "/^CONFIG_PCIE_CONFIGSPACE_HOLE / d" \
$A/old > $A/old.filtered
sed \
@@ -85,6 +87,8 @@
-e "/^CONFIG_[MAXIMUMDEFAULT]*_CONSOLE_LOGLEVEL_/ d" \
-e "/^CONFIG_COREBOOT_ROMSIZE_/ d" \
-e "/^CONFIG_BOARD_/ d" \
+ -e "/^CONFIG_IOAPIC / d" \
+ -e "/^CONFIG_HAVE_MOVNTI / d" \
-e "/^CONFIG_[NORTHSOUTH]*BRIDGE_/ d" \
-e "/^CONFIG_SUPERIO_/ d" \
-e "/^CONFIG_GX1_VIDEOMODE_/ d" \
@@ -103,6 +107,7 @@
-e "/^CONFIG_VIDEO_MB / d" \
-e "/^CONFIG_EXPERT / d" \
-e "/^CONFIG_SSE / d" \
+ -e "/^CONFIG_MMX / d" \
-e "/^CONFIG_VGA_BIOS / d" \
-e "/^CONFIG_WARNINGS_ARE_ERRORS / d" \
-e "/^CONFIG_TINY_BOOTBLOCK / d" \
1
0
Hi,
more changes to make kconfig's configs more similar to newconfig's:
DIMM_SUPPORT
APIC_ID_OFFSET
ACPI_SSDTX_NUM
IRQ_SLOT_COUNT
MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
(msi/ms9185 has a device id of 0x1022, which would be AMD, but we
have a global vendor ID set for msi. which one is right? MSI's or AMD's?)
MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
MEM_TRAIN_SEQ
HAVE_ACPI_RESUME
It also removes HAVE_MOVNTI and IOAPIC from the compareboards report
(which also ends up on the list) as we deliberately diverged from
newconfig there (they're per-CPU or per-chipset now, so we can assume
that newconfig is incorrect there), and also MMX (a kconfig-only symbol)
Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>
2
2