Author: stepan
Date: Sun Jan 31 21:51:00 2010
New Revision: 5071
URL: http://tracker.coreboot.org/trac/coreboot/changeset/5071
Log:
compareboard:
- drop all occurences of LOGLEVEL settings.
- drop CONFIG_CPU_[VIA|INTEL|AMD] because they're Kconfig only.
- re-enable CONFIG_IOAPIC for now, it might need some fixing.
Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de>
Acked-by: Stefan Reinauer <stepan(a)coresystems.de>
Modified:
trunk/util/compareboard/compareboard
Modified: trunk/util/compareboard/compareboard
==============================================================================
--- trunk/util/compareboard/compareboard Sun Jan 31 19:48:34 2010 (r5070)
+++ trunk/util/compareboard/compareboard Sun Jan 31 21:51:00 2010 (r5071)
@@ -84,10 +84,10 @@
sed \
-e "/^CONFIG_VENDOR_/ d" \
-e "/^CONFIG_ARCH_POWERPC / d" \
- -e "/^CONFIG_[MAXIMUMDEFAULT]*_CONSOLE_LOGLEVEL_/ d" \
+ -e "/^CONFIG_MAXIMUM_CONSOLE_LOGLEVEL/ d" \
+ -e "/^CONFIG_DEFAULT_CONSOLE_LOGLEVEL/ d" \
-e "/^CONFIG_COREBOOT_ROMSIZE_/ d" \
-e "/^CONFIG_BOARD_/ d" \
- -e "/^CONFIG_IOAPIC / d" \
-e "/^CONFIG_HAVE_MOVNTI / d" \
-e "/^CONFIG_[NORTHSOUTH]*BRIDGE_/ d" \
-e "/^CONFIG_SUPERIO_/ d" \
@@ -100,6 +100,9 @@
-e "/^CONFIG_COMPRESSED_PAYLOAD_LZMA / d" \
-e "/^CONFIG_CPU_[A-Z]*_MODEL_/ d" \
-e "/^CONFIG_CPU_[A-Z]*_SOCKET_/ d" \
+ -e "/^CONFIG_CPU_AMD_/ d" \
+ -e "/^CONFIG_CPU_INTEL_/ d" \
+ -e "/^CONFIG_CPU_VIA_/ d" \
-e "/^CONFIG_ROMBASE / d" \
-e "/^CONFIG_ROM_IMAGE_SIZE / d" \
-e "/^CONFIG_STACK_SIZE / d" \
1
0
[1/117] a-trend/atc-6220 ok.
Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[2/117] a-trend/atc-6240 ok.
Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[3/117] abit/be6-ii_v2_0 ok.
Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[4/117] advantech/pcm-5820 ok.
Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[5/117] amd/db800 ok.
Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[6/117] amd/dbm690t ok.
Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/amd/dbm690t/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[7/117] amd/norwich ok.
Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[8/117] amd/pistachio ok.
Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/amd/pistachio/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[9/117] amd/rumba ok.
Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[10/117] amd/serengeti_cheetah ok.
Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/amd/serengeti_cheetah/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[11/117] amd/serengeti_cheetah_fam10 ok.
Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[12/117] arima/hdama ok.
Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/arima/hdama/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[13/117] artecgroup/dbe61 ok.
Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[14/117] asi/mb_5blgp ok.
Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[15/117] asi/mb_5blmp ok.
Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[16/117] asus/a8n_e ok.
Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/asus/a8n_e/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[17/117] asus/a8v-e_se ok.
Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[18/117] asus/m2v-mx_se ok.
Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/asus/m2v-mx_se/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x1f00000
+CONFIG_RAMBASE = 0x100000
-CONFIG_RAMTOP = 0x2000000
+CONFIG_RAMTOP = 0x200000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[19/117] asus/mew-am ok.
Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[20/117] asus/mew-vm ok.
Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[21/117] asus/p2b-d ok.
Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[22/117] asus/p2b-ds ok.
Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[23/117] asus/p2b-f ok.
Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[24/117] asus/p2b ok.
Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[25/117] asus/p3b-f ok.
Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[26/117] axus/tc320 ok.
Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[27/117] azza/pt-6ibd ok.
Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[28/117] bcom/winnet100 ok.
Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[29/117] bcom/winnetp680 ok.
Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/bcom/winnetp680/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
[30/117] biostar/m6tba ok.
Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[31/117] broadcom/blast ok.
Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[32/117] compaq/deskpro_en_sff_p600 ok.
Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[33/117] dell/s1850 ok.
Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TTYS0_BAUD = 0x4b00
+CONFIG_TTYS0_BAUD = 0x1c200
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[34/117] digitallogic/adl855pc ok.
Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SMP = 0x0
+CONFIG_SMP = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[35/117] digitallogic/msm586seg ok.
Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/digitallogic/msm586seg/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_SC520 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[36/117] digitallogic/msm800sev ok.
Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[37/117] eaglelion/5bcm ok.
Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[38/117] emulation/qemu-x86 ok.
Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/emulation/qemu-x86/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_EMULATION_QEMU_X86 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0x8f000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[39/117] gigabyte/ga-6bxc ok.
Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[40/117] gigabyte/ga_2761gxdk ok.
Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[41/117] gigabyte/m57sli ok.
Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/gigabyte/m57sli/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[42/117] hp/dl145_g3 ok.
Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[43/117] hp/e_vectra_p2706t ok.
Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[44/117] ibm/e325 ok.
Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[45/117] ibm/e326 ok.
Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/ibm/e326/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[46/117] iei/juki-511p ok.
Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/iei/juki-511p/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[47/117] iei/nova4899r ok.
Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[48/117] iei/pcisa-lx-800-r10 ok.
Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[49/117] intel/d945gclf ok.
Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/intel/d945gclf/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xffed8000
+CONFIG_DCACHE_RAM_BASE = 0xffdf8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[50/117] intel/eagleheights ok.
Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE2 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[51/117] intel/jarrell ok.
Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_REBOOT_CNT = 0x8
+CONFIG_MAX_REBOOT_CNT = 0x3
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[52/117] intel/mtarvon ok.
Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[53/117] intel/truxton ok.
Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_EP80579 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[54/117] intel/xe7501devkit ok.
Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[55/117] iwill/dk8_htx ok.
Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/iwill/dk8_htx/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc4000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_SIZE = 0xc000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x80000
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[56/117] iwill/dk8s2 ok.
Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[57/117] iwill/dk8x ok.
Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[58/117] jetway/j7f24 ok.
Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/jetway/j7f24/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[59/117] kontron/986lcd-m ok.
Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/kontron/986lcd-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
[60/117] kontron/kt690 ok.
Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/kontron/kt690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[61/117] lippert/frontrunner ok.
Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[62/117] lippert/roadrunner-lx ok.
Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[63/117] lippert/spacerunner-lx ok.
Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[64/117] mitac/6513wu ok.
Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[65/117] msi/ms6119 ok.
Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[66/117] msi/ms6147 ok.
Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[67/117] msi/ms6156 ok.
Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[68/117] msi/ms6178 ok.
Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[69/117] msi/ms7135 ok.
Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/msi/ms7135/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[70/117] msi/ms7260 ok.
Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/msi/ms7260/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[71/117] msi/ms9185 ok.
Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/msi/ms9185/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[72/117] msi/ms9282 ok.
Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/msi/ms9282/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[73/117] nec/powermate2000 ok.
Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[74/117] newisys/khepri ok.
Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[75/117] nvidia/l1_2pvv ok.
Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/nvidia/l1_2pvv/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[76/117] olpc/btest ok.
Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[77/117] olpc/rev_a ok.
Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[78/117] pcengines/alix1c ok.
Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[79/117] rca/rm4100 ok.
Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/rca/rm4100/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[80/117] roda/rk886ex ok.
Processing mainboard/roda/rk886ex (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/roda/rk886ex/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES = 0x0
[81/117] soyo/sy-6ba-plus-iii ok.
Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[82/117] sunw/ultra40 ok.
Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[83/117] supermicro/h8dme ok.
Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/supermicro/h8dme/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[84/117] supermicro/h8dmr ok.
Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/supermicro/h8dmr/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[85/117] supermicro/h8dmr_fam10 ok.
Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[86/117] supermicro/x6dai_g ok.
Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[87/117] supermicro/x6dhe_g ok.
Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[88/117] supermicro/x6dhe_g2 ok.
Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[89/117] supermicro/x6dhr_ig ok.
Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[90/117] supermicro/x6dhr_ig2 ok.
Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[91/117] technexion/tim5690 ok.
Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/technexion/tim5690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
[92/117] technexion/tim8690 ok.
Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/technexion/tim8690/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[93/117] technologic/ts5300 ok.
Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/technologic/ts5300/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_SC520 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
-CONFIG_TTYS0_BASE = 0x2f8
+CONFIG_TTYS0_BASE = 0x3f8
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[94/117] televideo/tc7020 ok.
Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[95/117] thomson/ip1000 ok.
Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/thomson/ip1000/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[96/117] tyan/s1846 ok.
Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[97/117] tyan/s2735 ok.
Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_USE_PRINTK_IN_CAR = 0x1
+CONFIG_USE_PRINTK_IN_CAR = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[98/117] tyan/s2850 ok.
Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[99/117] tyan/s2875 ok.
Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[100/117] tyan/s2880 ok.
Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[101/117] tyan/s2881 ok.
Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[102/117] tyan/s2882 ok.
Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[103/117] tyan/s2885 ok.
Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[104/117] tyan/s2891 ok.
Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/tyan/s2891/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[105/117] tyan/s2892 ok.
Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/tyan/s2892/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[106/117] tyan/s2895 ok.
Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/tyan/s2895/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
[107/117] tyan/s2912 ok.
Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/tyan/s2912/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[108/117] tyan/s2912_fam10 ok.
Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/tyan/s2912_fam10/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[109/117] tyan/s4880 ok.
Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[110/117] tyan/s4882 ok.
Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x2000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[111/117] via/epia-cn ok.
Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/via/epia-cn/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[112/117] via/epia-m ok.
Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/via/epia-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[113/117] via/epia-m700 ok.
Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/via/epia-m700/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_SIZE = 0x2000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HEAP_SIZE = 0x5000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[114/117] via/epia-n ok.
Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/via/epia-n/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN400_VIDEO_MB_128MB = 0x0
+CONFIG_CN400_VIDEO_MB_16MB = 0x0
+CONFIG_CN400_VIDEO_MB_32MB = 0x1
+CONFIG_CN400_VIDEO_MB_64MB = 0x0
+CONFIG_CN400_VIDEO_MB_8MB = 0x0
+CONFIG_CN400_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[115/117] via/epia ok.
Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[116/117] via/pc2500e ok.
Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/via/pc2500e/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_OPTION_TABLE = 0x1
+CONFIG_USE_OPTION_TABLE = 0x0
[117/117] via/vt8454c ok.
Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5070/targets/via/vt8454c/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
1
0
Author: uwe
Date: Sun Jan 31 19:48:34 2010
New Revision: 5070
URL: http://tracker.coreboot.org/trac/coreboot/changeset/5070
Log:
Add detection support for the Winbond W83877AF (trivial).
Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de>
Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de>
Modified:
trunk/util/superiotool/winbond.c
Modified: trunk/util/superiotool/winbond.c
==============================================================================
--- trunk/util/superiotool/winbond.c Sat Jan 30 15:56:15 2010 (r5069)
+++ trunk/util/superiotool/winbond.c Sun Jan 31 19:48:34 2010 (r5070)
@@ -464,9 +464,11 @@
/* ID[3..0] */
{0xa, "W83877F", {
{EOT}}},
+ {0xb, "W83877AF", {
+ {EOT}}},
{0xc, "W83877TF", {
{EOT}}},
- {0xd, "W83877ATF", {
+ {0xd, "W83877ATF/ATG", {
{EOT}}},
{EOT}
};
@@ -556,7 +558,7 @@
else
id = (devid << 4) | ((rev & 0xf0) >> 4); /* ID and rev[7..4] */
- if (olddevid == 0x0a || olddevid == 0x0c || olddevid == 0x0d)
+ if (olddevid >= 0x0a && olddevid <= 0x0d)
id = olddevid & 0x0f; /* ID[3..0] */
if (superio_unknown(reg_table, id)) {
@@ -566,7 +568,7 @@
return;
}
- if (olddevid == 0x0a || olddevid == 0x0c || olddevid == 0x0d)
+ if (olddevid >= 0x0a && olddevid <= 0x0d)
printf("Found Winbond %s (id=0x%02x) at 0x%x\n",
get_superio_name(reg_table, id), olddevid, port);
else
1
0
Re: [coreboot] #15: fix abuild for all boards that use the "three images solution
by coreboot 31 Jan '10
by coreboot 31 Jan '10
31 Jan '10
#15: fix abuild for all boards that use the "three images solution
---------------------------------+------------------------------------------
Reporter: anonymous | Owner: yhlu
Type: defect | Status: closed
Priority: major | Milestone:
Component: coreboot | Resolution: wontfix
Keywords: abuild | Dependencies:
Patchstatus: there is no patch |
---------------------------------+------------------------------------------
Comment(by CobraMacos):
Just to share an expirience:
I found a way to download youTube videos. Some of are webs where you put
the link from YouTube and it gives you file with strange extension and
small size. Some are really complicated.
My way was to use moviesherlock (moviesherlock.com or sm like this -
please ask me - will rememeber). Really simple utility, that just works,
and only 1 button in software.
<a
href=http://download.cnet.com/3001-2140_4-75065920.html?spi=68a87b0bad1ea20…>I
downloaded it from here:
http://download.cnet.com/3001-2140_4-75065920.html?spi=68a87b0bad1ea20e1228…</a>.
I downloaded even HD movies!
But it looks too easy, has no player, but just works. It downloaded ~12
concurrent movies for me and actually slows down my system. Its possible
to do search in <a href=http://moviesherlock.com>moviesherlock</a> and
search results differs from what you see in YouTube. Thats strange.
Who knows - youTube results are same for same keyword? I likes cat (Simons
cat / dog).
Why doesn't youtube allows to download its movies without external
tools?!! It actually sucks!
Thanks in advance!
--
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/15#comment:6>
coreboot <http://www.coreboot.org/>
1
0
[1/117] a-trend/atc-6220 ok.
Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[2/117] a-trend/atc-6240 ok.
Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[3/117] abit/be6-ii_v2_0 ok.
Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[4/117] advantech/pcm-5820 ok.
Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[5/117] amd/db800 ok.
Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[6/117] amd/dbm690t ok.
Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/amd/dbm690t/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[7/117] amd/norwich ok.
Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[8/117] amd/pistachio ok.
Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/amd/pistachio/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[9/117] amd/rumba ok.
Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[10/117] amd/serengeti_cheetah ok.
Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/amd/serengeti_cheetah/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[11/117] amd/serengeti_cheetah_fam10 ok.
Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[12/117] arima/hdama ok.
Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/arima/hdama/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[13/117] artecgroup/dbe61 ok.
Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[14/117] asi/mb_5blgp ok.
Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[15/117] asi/mb_5blmp ok.
Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[16/117] asus/a8n_e ok.
Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/asus/a8n_e/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[17/117] asus/a8v-e_se ok.
Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[18/117] asus/m2v-mx_se ok.
Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/asus/m2v-mx_se/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x1f00000
+CONFIG_RAMBASE = 0x100000
-CONFIG_RAMTOP = 0x2000000
+CONFIG_RAMTOP = 0x200000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[19/117] asus/mew-am ok.
Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[20/117] asus/mew-vm ok.
Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[21/117] asus/p2b-d ok.
Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[22/117] asus/p2b-ds ok.
Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[23/117] asus/p2b-f ok.
Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[24/117] asus/p2b ok.
Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[25/117] asus/p3b-f ok.
Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[26/117] axus/tc320 ok.
Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[27/117] azza/pt-6ibd ok.
Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[28/117] bcom/winnet100 ok.
Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[29/117] bcom/winnetp680 ok.
Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/bcom/winnetp680/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
[30/117] biostar/m6tba ok.
Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[31/117] broadcom/blast ok.
Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[32/117] compaq/deskpro_en_sff_p600 ok.
Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[33/117] dell/s1850 ok.
Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TTYS0_BAUD = 0x4b00
+CONFIG_TTYS0_BAUD = 0x1c200
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[34/117] digitallogic/adl855pc ok.
Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SMP = 0x0
+CONFIG_SMP = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[35/117] digitallogic/msm586seg ok.
Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/digitallogic/msm586seg/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_SC520 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[36/117] digitallogic/msm800sev ok.
Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[37/117] eaglelion/5bcm ok.
Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[38/117] emulation/qemu-x86 ok.
Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/emulation/qemu-x86/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_EMULATION_QEMU_X86 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0x8f000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[39/117] gigabyte/ga-6bxc ok.
Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[40/117] gigabyte/ga_2761gxdk ok.
Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[41/117] gigabyte/m57sli ok.
Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/gigabyte/m57sli/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[42/117] hp/dl145_g3 ok.
Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[43/117] hp/e_vectra_p2706t ok.
Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[44/117] ibm/e325 ok.
Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[45/117] ibm/e326 ok.
Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/ibm/e326/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[46/117] iei/juki-511p ok.
Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/iei/juki-511p/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[47/117] iei/nova4899r ok.
Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[48/117] iei/pcisa-lx-800-r10 ok.
Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[49/117] intel/d945gclf ok.
Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/intel/d945gclf/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xffed8000
+CONFIG_DCACHE_RAM_BASE = 0xffdf8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[50/117] intel/eagleheights ok.
Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE2 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[51/117] intel/jarrell ok.
Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_REBOOT_CNT = 0x8
+CONFIG_MAX_REBOOT_CNT = 0x3
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[52/117] intel/mtarvon ok.
Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[53/117] intel/truxton ok.
Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_EP80579 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[54/117] intel/xe7501devkit ok.
Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[55/117] iwill/dk8_htx ok.
Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/iwill/dk8_htx/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc4000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_SIZE = 0xc000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x80000
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[56/117] iwill/dk8s2 ok.
Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[57/117] iwill/dk8x ok.
Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[58/117] jetway/j7f24 ok.
Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/jetway/j7f24/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[59/117] kontron/986lcd-m ok.
Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/kontron/986lcd-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
[60/117] kontron/kt690 ok.
Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/kontron/kt690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[61/117] lippert/frontrunner ok.
Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[62/117] lippert/roadrunner-lx ok.
Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[63/117] lippert/spacerunner-lx ok.
Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[64/117] mitac/6513wu ok.
Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[65/117] msi/ms6119 ok.
Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[66/117] msi/ms6147 ok.
Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[67/117] msi/ms6156 ok.
Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[68/117] msi/ms6178 ok.
Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[69/117] msi/ms7135 ok.
Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/msi/ms7135/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[70/117] msi/ms7260 ok.
Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/msi/ms7260/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[71/117] msi/ms9185 ok.
Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/msi/ms9185/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[72/117] msi/ms9282 ok.
Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/msi/ms9282/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[73/117] nec/powermate2000 ok.
Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[74/117] newisys/khepri ok.
Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[75/117] nvidia/l1_2pvv ok.
Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/nvidia/l1_2pvv/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[76/117] olpc/btest ok.
Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[77/117] olpc/rev_a ok.
Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[78/117] pcengines/alix1c ok.
Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[79/117] rca/rm4100 ok.
Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/rca/rm4100/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[80/117] roda/rk886ex ok.
Processing mainboard/roda/rk886ex (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/roda/rk886ex/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES = 0x0
[81/117] soyo/sy-6ba-plus-iii ok.
Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[82/117] sunw/ultra40 ok.
Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[83/117] supermicro/h8dme ok.
Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/supermicro/h8dme/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[84/117] supermicro/h8dmr ok.
Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/supermicro/h8dmr/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[85/117] supermicro/h8dmr_fam10 ok.
Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[86/117] supermicro/x6dai_g ok.
Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[87/117] supermicro/x6dhe_g ok.
Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[88/117] supermicro/x6dhe_g2 ok.
Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[89/117] supermicro/x6dhr_ig ok.
Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[90/117] supermicro/x6dhr_ig2 ok.
Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[91/117] technexion/tim5690 ok.
Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/technexion/tim5690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
[92/117] technexion/tim8690 ok.
Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/technexion/tim8690/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[93/117] technologic/ts5300 ok.
Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/technologic/ts5300/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_SC520 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
-CONFIG_TTYS0_BASE = 0x2f8
+CONFIG_TTYS0_BASE = 0x3f8
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[94/117] televideo/tc7020 ok.
Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[95/117] thomson/ip1000 ok.
Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/thomson/ip1000/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[96/117] tyan/s1846 ok.
Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[97/117] tyan/s2735 ok.
Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_USE_PRINTK_IN_CAR = 0x1
+CONFIG_USE_PRINTK_IN_CAR = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[98/117] tyan/s2850 ok.
Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[99/117] tyan/s2875 ok.
Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[100/117] tyan/s2880 ok.
Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[101/117] tyan/s2881 ok.
Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[102/117] tyan/s2882 ok.
Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[103/117] tyan/s2885 ok.
Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[104/117] tyan/s2891 ok.
Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/tyan/s2891/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[105/117] tyan/s2892 ok.
Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/tyan/s2892/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[106/117] tyan/s2895 ok.
Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/tyan/s2895/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
[107/117] tyan/s2912 ok.
Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/tyan/s2912/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[108/117] tyan/s2912_fam10 ok.
Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/tyan/s2912_fam10/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[109/117] tyan/s4880 ok.
Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[110/117] tyan/s4882 ok.
Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x2000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[111/117] via/epia-cn ok.
Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/via/epia-cn/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[112/117] via/epia-m ok.
Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/via/epia-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[113/117] via/epia-m700 ok.
Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/via/epia-m700/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_SIZE = 0x2000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HEAP_SIZE = 0x5000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[114/117] via/epia-n ok.
Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/via/epia-n/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN400_VIDEO_MB_128MB = 0x0
+CONFIG_CN400_VIDEO_MB_16MB = 0x0
+CONFIG_CN400_VIDEO_MB_32MB = 0x1
+CONFIG_CN400_VIDEO_MB_64MB = 0x0
+CONFIG_CN400_VIDEO_MB_8MB = 0x0
+CONFIG_CN400_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[115/117] via/epia ok.
Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[116/117] via/pc2500e ok.
Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/via/pc2500e/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_OPTION_TABLE = 0x1
+CONFIG_USE_OPTION_TABLE = 0x0
[117/117] via/vt8454c ok.
Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5069/targets/via/vt8454c/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
1
0
Hello,
This is a rework patch for the RCA RM4100 and Thomson IP1000. A few of
the changes include:
1. Setting up the PCI Host Bridge registers (not doing this was causing
random unexpected exception errors)
2. Setting up some LPC registers
3. dropping the early lpc code to disable the TCO timer. This probably
can also be dropped from the i82801xx code too. To my suprise the is an
LPC register that disables this completely (0xd4).
4. move gpio code to run earlier.
5. all this needs to be done pre-raminit
Build and Run tested. See patch.
Signed-off-by: Joseph Smith <joe(a)settoplinux.org>
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
3
6
30 Jan '10
Author: linux_junkie
Date: Sat Jan 30 15:56:15 2010
New Revision: 5069
URL: http://tracker.coreboot.org/trac/coreboot/changeset/5069
Log:
Trivial fixup on IP1000 and RM4100 copyright entries.
Signed-off-by: Joseph Smith <joe(a)settoplinux.org>
Acked-by: Joseph Smith <joe(a)settoplinux.org>
Modified:
trunk/src/mainboard/rca/rm4100/auto.c
trunk/src/mainboard/thomson/ip1000/auto.c
Modified: trunk/src/mainboard/rca/rm4100/auto.c
==============================================================================
--- trunk/src/mainboard/rca/rm4100/auto.c Sat Jan 30 11:58:30 2010 (r5068)
+++ trunk/src/mainboard/rca/rm4100/auto.c Sat Jan 30 15:56:15 2010 (r5069)
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2010 Joseph Smith <joe(a)settoplinux.org>
+ * Copyright (C) 2008-2010 Joseph Smith <joe(a)settoplinux.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
Modified: trunk/src/mainboard/thomson/ip1000/auto.c
==============================================================================
--- trunk/src/mainboard/thomson/ip1000/auto.c Sat Jan 30 11:58:30 2010 (r5068)
+++ trunk/src/mainboard/thomson/ip1000/auto.c Sat Jan 30 15:56:15 2010 (r5069)
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2010 Joseph Smith <joe(a)settoplinux.org>
+ * Copyright (C) 2008-2010 Joseph Smith <joe(a)settoplinux.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
1
0
[1/117] a-trend/atc-6220 ok.
Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[2/117] a-trend/atc-6240 ok.
Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[3/117] abit/be6-ii_v2_0 ok.
Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[4/117] advantech/pcm-5820 ok.
Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[5/117] amd/db800 ok.
Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[6/117] amd/dbm690t ok.
Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/amd/dbm690t/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[7/117] amd/norwich ok.
Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[8/117] amd/pistachio ok.
Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/amd/pistachio/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[9/117] amd/rumba ok.
Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[10/117] amd/serengeti_cheetah ok.
Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/amd/serengeti_cheetah/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[11/117] amd/serengeti_cheetah_fam10 ok.
Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[12/117] arima/hdama ok.
Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/arima/hdama/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[13/117] artecgroup/dbe61 ok.
Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[14/117] asi/mb_5blgp ok.
Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[15/117] asi/mb_5blmp ok.
Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[16/117] asus/a8n_e ok.
Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/asus/a8n_e/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[17/117] asus/a8v-e_se ok.
Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[18/117] asus/m2v-mx_se ok.
Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/asus/m2v-mx_se/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x1f00000
+CONFIG_RAMBASE = 0x100000
-CONFIG_RAMTOP = 0x2000000
+CONFIG_RAMTOP = 0x200000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[19/117] asus/mew-am ok.
Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[20/117] asus/mew-vm ok.
Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[21/117] asus/p2b-d ok.
Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[22/117] asus/p2b-ds ok.
Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[23/117] asus/p2b-f ok.
Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[24/117] asus/p2b ok.
Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[25/117] asus/p3b-f ok.
Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[26/117] axus/tc320 ok.
Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[27/117] azza/pt-6ibd ok.
Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[28/117] bcom/winnet100 ok.
Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[29/117] bcom/winnetp680 ok.
Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/bcom/winnetp680/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
[30/117] biostar/m6tba ok.
Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[31/117] broadcom/blast ok.
Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[32/117] compaq/deskpro_en_sff_p600 ok.
Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[33/117] dell/s1850 ok.
Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TTYS0_BAUD = 0x4b00
+CONFIG_TTYS0_BAUD = 0x1c200
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[34/117] digitallogic/adl855pc ok.
Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SMP = 0x0
+CONFIG_SMP = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[35/117] digitallogic/msm586seg ok.
Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/digitallogic/msm586seg/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_SC520 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[36/117] digitallogic/msm800sev ok.
Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[37/117] eaglelion/5bcm ok.
Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[38/117] emulation/qemu-x86 ok.
Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/emulation/qemu-x86/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_EMULATION_QEMU_X86 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0x8f000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[39/117] gigabyte/ga-6bxc ok.
Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[40/117] gigabyte/ga_2761gxdk ok.
Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[41/117] gigabyte/m57sli ok.
Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/gigabyte/m57sli/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[42/117] hp/dl145_g3 ok.
Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[43/117] hp/e_vectra_p2706t ok.
Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[44/117] ibm/e325 ok.
Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[45/117] ibm/e326 ok.
Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/ibm/e326/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[46/117] iei/juki-511p ok.
Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/iei/juki-511p/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[47/117] iei/nova4899r ok.
Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[48/117] iei/pcisa-lx-800-r10 ok.
Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[49/117] intel/d945gclf ok.
Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/intel/d945gclf/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xffed8000
+CONFIG_DCACHE_RAM_BASE = 0xffdf8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[50/117] intel/eagleheights ok.
Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE2 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[51/117] intel/jarrell ok.
Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_REBOOT_CNT = 0x8
+CONFIG_MAX_REBOOT_CNT = 0x3
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[52/117] intel/mtarvon ok.
Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[53/117] intel/truxton ok.
Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_EP80579 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[54/117] intel/xe7501devkit ok.
Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[55/117] iwill/dk8_htx ok.
Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/iwill/dk8_htx/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc4000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_SIZE = 0xc000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x80000
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[56/117] iwill/dk8s2 ok.
Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[57/117] iwill/dk8x ok.
Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[58/117] jetway/j7f24 ok.
Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/jetway/j7f24/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[59/117] kontron/986lcd-m ok.
Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/kontron/986lcd-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
[60/117] kontron/kt690 ok.
Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/kontron/kt690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[61/117] lippert/frontrunner ok.
Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[62/117] lippert/roadrunner-lx ok.
Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[63/117] lippert/spacerunner-lx ok.
Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[64/117] mitac/6513wu ok.
Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[65/117] msi/ms6119 ok.
Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[66/117] msi/ms6147 ok.
Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[67/117] msi/ms6156 ok.
Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[68/117] msi/ms6178 ok.
Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[69/117] msi/ms7135 ok.
Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/msi/ms7135/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[70/117] msi/ms7260 ok.
Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/msi/ms7260/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[71/117] msi/ms9185 ok.
Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/msi/ms9185/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[72/117] msi/ms9282 ok.
Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/msi/ms9282/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[73/117] nec/powermate2000 ok.
Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[74/117] newisys/khepri ok.
Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[75/117] nvidia/l1_2pvv ok.
Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/nvidia/l1_2pvv/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[76/117] olpc/btest ok.
Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[77/117] olpc/rev_a ok.
Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[78/117] pcengines/alix1c ok.
Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[79/117] rca/rm4100 ok.
Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/rca/rm4100/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[80/117] roda/rk886ex ok.
Processing mainboard/roda/rk886ex (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/roda/rk886ex/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES = 0x0
[81/117] soyo/sy-6ba-plus-iii ok.
Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[82/117] sunw/ultra40 ok.
Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[83/117] supermicro/h8dme ok.
Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/supermicro/h8dme/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[84/117] supermicro/h8dmr ok.
Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/supermicro/h8dmr/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[85/117] supermicro/h8dmr_fam10 ok.
Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[86/117] supermicro/x6dai_g ok.
Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[87/117] supermicro/x6dhe_g ok.
Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[88/117] supermicro/x6dhe_g2 ok.
Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[89/117] supermicro/x6dhr_ig ok.
Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[90/117] supermicro/x6dhr_ig2 ok.
Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[91/117] technexion/tim5690 ok.
Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/technexion/tim5690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
[92/117] technexion/tim8690 ok.
Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/technexion/tim8690/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[93/117] technologic/ts5300 ok.
Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/technologic/ts5300/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_SC520 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
-CONFIG_TTYS0_BASE = 0x2f8
+CONFIG_TTYS0_BASE = 0x3f8
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[94/117] televideo/tc7020 ok.
Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[95/117] thomson/ip1000 ok.
Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/thomson/ip1000/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[96/117] tyan/s1846 ok.
Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[97/117] tyan/s2735 ok.
Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_USE_PRINTK_IN_CAR = 0x1
+CONFIG_USE_PRINTK_IN_CAR = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[98/117] tyan/s2850 ok.
Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[99/117] tyan/s2875 ok.
Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[100/117] tyan/s2880 ok.
Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[101/117] tyan/s2881 ok.
Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[102/117] tyan/s2882 ok.
Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[103/117] tyan/s2885 ok.
Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[104/117] tyan/s2891 ok.
Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/tyan/s2891/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[105/117] tyan/s2892 ok.
Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/tyan/s2892/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[106/117] tyan/s2895 ok.
Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/tyan/s2895/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
[107/117] tyan/s2912 ok.
Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/tyan/s2912/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[108/117] tyan/s2912_fam10 ok.
Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/tyan/s2912_fam10/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[109/117] tyan/s4880 ok.
Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[110/117] tyan/s4882 ok.
Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x2000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[111/117] via/epia-cn ok.
Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/via/epia-cn/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[112/117] via/epia-m ok.
Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/via/epia-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[113/117] via/epia-m700 ok.
Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/via/epia-m700/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_SIZE = 0x2000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HEAP_SIZE = 0x5000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[114/117] via/epia-n ok.
Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/via/epia-n/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN400_VIDEO_MB_128MB = 0x0
+CONFIG_CN400_VIDEO_MB_16MB = 0x0
+CONFIG_CN400_VIDEO_MB_32MB = 0x1
+CONFIG_CN400_VIDEO_MB_64MB = 0x0
+CONFIG_CN400_VIDEO_MB_8MB = 0x0
+CONFIG_CN400_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[115/117] via/epia ok.
Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[116/117] via/pc2500e ok.
Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/via/pc2500e/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_OPTION_TABLE = 0x1
+CONFIG_USE_OPTION_TABLE = 0x0
[117/117] via/vt8454c ok.
Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5068/targets/via/vt8454c/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
1
0
[1/117] a-trend/atc-6220 fail.
[2/117] a-trend/atc-6240 fail.
[3/117] abit/be6-ii_v2_0 fail.
[4/117] advantech/pcm-5820 fail.
[5/117] amd/db800 ok.
Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[6/117] amd/dbm690t ok.
Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/amd/dbm690t/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[7/117] amd/norwich ok.
Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[8/117] amd/pistachio ok.
Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/amd/pistachio/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[9/117] amd/rumba fail.
[10/117] amd/serengeti_cheetah ok.
Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/amd/serengeti_cheetah/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[11/117] amd/serengeti_cheetah_fam10 ok.
Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[12/117] arima/hdama ok.
Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/arima/hdama/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[13/117] artecgroup/dbe61 ok.
Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[14/117] asi/mb_5blgp fail.
[15/117] asi/mb_5blmp fail.
[16/117] asus/a8n_e ok.
Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/asus/a8n_e/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[17/117] asus/a8v-e_se ok.
Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[18/117] asus/m2v-mx_se ok.
Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/asus/m2v-mx_se/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x1f00000
+CONFIG_RAMBASE = 0x100000
-CONFIG_RAMTOP = 0x2000000
+CONFIG_RAMTOP = 0x200000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[19/117] asus/mew-am fail.
[20/117] asus/mew-vm fail.
[21/117] asus/p2b-d fail.
[22/117] asus/p2b-ds fail.
[23/117] asus/p2b-f fail.
[24/117] asus/p2b fail.
[25/117] asus/p3b-f fail.
[26/117] axus/tc320 fail.
[27/117] azza/pt-6ibd fail.
[28/117] bcom/winnet100 fail.
[29/117] bcom/winnetp680 ok.
Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/bcom/winnetp680/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
[30/117] biostar/m6tba fail.
[31/117] broadcom/blast ok.
Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[32/117] compaq/deskpro_en_sff_p600 fail.
[33/117] dell/s1850 fail.
[34/117] digitallogic/adl855pc fail.
[35/117] digitallogic/msm586seg fail.
[36/117] digitallogic/msm800sev ok.
Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[37/117] eaglelion/5bcm fail.
[38/117] emulation/qemu-x86 fail.
[39/117] gigabyte/ga-6bxc fail.
[40/117] gigabyte/ga_2761gxdk ok.
Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[41/117] gigabyte/m57sli ok.
Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/gigabyte/m57sli/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[42/117] hp/dl145_g3 ok.
Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[43/117] hp/e_vectra_p2706t fail.
[44/117] ibm/e325 ok.
Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[45/117] ibm/e326 ok.
Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/ibm/e326/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[46/117] iei/juki-511p fail.
[47/117] iei/nova4899r fail.
[48/117] iei/pcisa-lx-800-r10 ok.
Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[49/117] intel/d945gclf ok.
Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/intel/d945gclf/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xffed8000
+CONFIG_DCACHE_RAM_BASE = 0xffdf8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[50/117] intel/eagleheights ok.
Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE2 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[51/117] intel/jarrell fail.
[52/117] intel/mtarvon fail.
[53/117] intel/truxton fail.
[54/117] intel/xe7501devkit fail.
[55/117] iwill/dk8_htx ok.
Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/iwill/dk8_htx/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc4000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_SIZE = 0xc000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x80000
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[56/117] iwill/dk8s2 ok.
Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[57/117] iwill/dk8x ok.
Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[58/117] jetway/j7f24 ok.
Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/jetway/j7f24/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[59/117] kontron/986lcd-m ok.
Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/kontron/986lcd-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
[60/117] kontron/kt690 ok.
Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/kontron/kt690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[61/117] lippert/frontrunner fail.
[62/117] lippert/roadrunner-lx ok.
Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[63/117] lippert/spacerunner-lx ok.
Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[64/117] mitac/6513wu fail.
[65/117] msi/ms6119 fail.
[66/117] msi/ms6147 fail.
[67/117] msi/ms6156 fail.
[68/117] msi/ms6178 fail.
[69/117] msi/ms7135 ok.
Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/msi/ms7135/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[70/117] msi/ms7260 ok.
Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/msi/ms7260/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[71/117] msi/ms9185 ok.
Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/msi/ms9185/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[72/117] msi/ms9282 ok.
Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/msi/ms9282/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[73/117] nec/powermate2000 fail.
[74/117] newisys/khepri ok.
Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[75/117] nvidia/l1_2pvv ok.
Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/nvidia/l1_2pvv/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[76/117] olpc/btest fail.
[77/117] olpc/rev_a fail.
[78/117] pcengines/alix1c ok.
Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[79/117] rca/rm4100 fail.
[80/117] roda/rk886ex ok.
Processing mainboard/roda/rk886ex (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/roda/rk886ex/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES = 0x0
[81/117] soyo/sy-6ba-plus-iii fail.
[82/117] sunw/ultra40 ok.
Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[83/117] supermicro/h8dme ok.
Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/supermicro/h8dme/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[84/117] supermicro/h8dmr ok.
Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/supermicro/h8dmr/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[85/117] supermicro/h8dmr_fam10 ok.
Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[86/117] supermicro/x6dai_g fail.
[87/117] supermicro/x6dhe_g fail.
[88/117] supermicro/x6dhe_g2 fail.
[89/117] supermicro/x6dhr_ig fail.
[90/117] supermicro/x6dhr_ig2 fail.
[91/117] technexion/tim5690 ok.
Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/technexion/tim5690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
[92/117] technexion/tim8690 ok.
Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/technexion/tim8690/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[93/117] technologic/ts5300 fail.
[94/117] televideo/tc7020 fail.
[95/117] thomson/ip1000 fail.
[96/117] tyan/s1846 fail.
[97/117] tyan/s2735 ok.
Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_USE_PRINTK_IN_CAR = 0x1
+CONFIG_USE_PRINTK_IN_CAR = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[98/117] tyan/s2850 ok.
Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[99/117] tyan/s2875 ok.
Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[100/117] tyan/s2880 ok.
Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[101/117] tyan/s2881 ok.
Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[102/117] tyan/s2882 ok.
Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[103/117] tyan/s2885 ok.
Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[104/117] tyan/s2891 ok.
Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/tyan/s2891/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[105/117] tyan/s2892 ok.
Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/tyan/s2892/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[106/117] tyan/s2895 ok.
Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/tyan/s2895/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
[107/117] tyan/s2912 ok.
Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/tyan/s2912/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[108/117] tyan/s2912_fam10 ok.
Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/tyan/s2912_fam10/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[109/117] tyan/s4880 ok.
Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[110/117] tyan/s4882 ok.
Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x2000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[111/117] via/epia-cn fail.
[112/117] via/epia-m ok.
Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/via/epia-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[113/117] via/epia-m700 ok.
Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/via/epia-m700/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_SIZE = 0x2000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HEAP_SIZE = 0x5000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[114/117] via/epia-n ok.
Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/via/epia-n/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN400_VIDEO_MB_128MB = 0x0
+CONFIG_CN400_VIDEO_MB_16MB = 0x0
+CONFIG_CN400_VIDEO_MB_32MB = 0x1
+CONFIG_CN400_VIDEO_MB_64MB = 0x0
+CONFIG_CN400_VIDEO_MB_8MB = 0x0
+CONFIG_CN400_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[115/117] via/epia ok.
Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[116/117] via/pc2500e fail.
[117/117] via/vt8454c ok.
Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5067/targets/via/vt8454c/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
1
0
[1/117] a-trend/atc-6220 fail.
[2/117] a-trend/atc-6240 fail.
[3/117] abit/be6-ii_v2_0 fail.
[4/117] advantech/pcm-5820 fail.
[5/117] amd/db800 ok.
Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[6/117] amd/dbm690t ok.
Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/amd/dbm690t/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[7/117] amd/norwich ok.
Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[8/117] amd/pistachio ok.
Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/amd/pistachio/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[9/117] amd/rumba fail.
[10/117] amd/serengeti_cheetah ok.
Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/amd/serengeti_cheetah/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[11/117] amd/serengeti_cheetah_fam10 ok.
Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[12/117] arima/hdama ok.
Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/arima/hdama/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[13/117] artecgroup/dbe61 ok.
Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[14/117] asi/mb_5blgp fail.
[15/117] asi/mb_5blmp fail.
[16/117] asus/a8n_e ok.
Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/asus/a8n_e/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[17/117] asus/a8v-e_se ok.
Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[18/117] asus/m2v-mx_se ok.
Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/asus/m2v-mx_se/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x1f00000
+CONFIG_RAMBASE = 0x100000
-CONFIG_RAMTOP = 0x2000000
+CONFIG_RAMTOP = 0x200000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[19/117] asus/mew-am fail.
[20/117] asus/mew-vm fail.
[21/117] asus/p2b-d fail.
[22/117] asus/p2b-ds fail.
[23/117] asus/p2b-f fail.
[24/117] asus/p2b fail.
[25/117] asus/p3b-f fail.
[26/117] axus/tc320 fail.
[27/117] azza/pt-6ibd fail.
[28/117] bcom/winnet100 fail.
[29/117] bcom/winnetp680 ok.
Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/bcom/winnetp680/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
[30/117] biostar/m6tba fail.
[31/117] broadcom/blast ok.
Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[32/117] compaq/deskpro_en_sff_p600 fail.
[33/117] dell/s1850 fail.
[34/117] digitallogic/adl855pc fail.
[35/117] digitallogic/msm586seg fail.
[36/117] digitallogic/msm800sev ok.
Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[37/117] eaglelion/5bcm fail.
[38/117] emulation/qemu-x86 fail.
[39/117] gigabyte/ga-6bxc fail.
[40/117] gigabyte/ga_2761gxdk fail.
[41/117] gigabyte/m57sli fail.
[42/117] hp/dl145_g3 ok.
Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[43/117] hp/e_vectra_p2706t fail.
[44/117] ibm/e325 ok.
Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[45/117] ibm/e326 ok.
Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/ibm/e326/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[46/117] iei/juki-511p fail.
[47/117] iei/nova4899r fail.
[48/117] iei/pcisa-lx-800-r10 ok.
Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[49/117] intel/d945gclf ok.
Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/intel/d945gclf/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xffed8000
+CONFIG_DCACHE_RAM_BASE = 0xffdf8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[50/117] intel/eagleheights ok.
Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE2 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[51/117] intel/jarrell fail.
[52/117] intel/mtarvon fail.
[53/117] intel/truxton fail.
[54/117] intel/xe7501devkit fail.
[55/117] iwill/dk8_htx ok.
Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/iwill/dk8_htx/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc4000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_SIZE = 0xc000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x80000
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[56/117] iwill/dk8s2 ok.
Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[57/117] iwill/dk8x ok.
Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[58/117] jetway/j7f24 ok.
Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/jetway/j7f24/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[59/117] kontron/986lcd-m ok.
Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/kontron/986lcd-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
[60/117] kontron/kt690 ok.
Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/kontron/kt690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[61/117] lippert/frontrunner fail.
[62/117] lippert/roadrunner-lx ok.
Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[63/117] lippert/spacerunner-lx ok.
Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[64/117] mitac/6513wu fail.
[65/117] msi/ms6119 fail.
[66/117] msi/ms6147 fail.
[67/117] msi/ms6156 fail.
[68/117] msi/ms6178 fail.
[69/117] msi/ms7135 ok.
Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/msi/ms7135/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[70/117] msi/ms7260 fail.
[71/117] msi/ms9185 ok.
Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/msi/ms9185/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[72/117] msi/ms9282 fail.
[73/117] nec/powermate2000 fail.
[74/117] newisys/khepri ok.
Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[75/117] nvidia/l1_2pvv ok.
Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/nvidia/l1_2pvv/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[76/117] olpc/btest fail.
[77/117] olpc/rev_a fail.
[78/117] pcengines/alix1c ok.
Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[79/117] rca/rm4100 fail.
[80/117] roda/rk886ex ok.
Processing mainboard/roda/rk886ex (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/roda/rk886ex/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES = 0x0
[81/117] soyo/sy-6ba-plus-iii fail.
[82/117] sunw/ultra40 ok.
Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[83/117] supermicro/h8dme ok.
Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/supermicro/h8dme/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[84/117] supermicro/h8dmr ok.
Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/supermicro/h8dmr/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[85/117] supermicro/h8dmr_fam10 ok.
Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[86/117] supermicro/x6dai_g fail.
[87/117] supermicro/x6dhe_g fail.
[88/117] supermicro/x6dhe_g2 fail.
[89/117] supermicro/x6dhr_ig fail.
[90/117] supermicro/x6dhr_ig2 fail.
[91/117] technexion/tim5690 ok.
Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/technexion/tim5690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
[92/117] technexion/tim8690 ok.
Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/technexion/tim8690/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[93/117] technologic/ts5300 fail.
[94/117] televideo/tc7020 fail.
[95/117] thomson/ip1000 fail.
[96/117] tyan/s1846 fail.
[97/117] tyan/s2735 ok.
Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_USE_PRINTK_IN_CAR = 0x1
+CONFIG_USE_PRINTK_IN_CAR = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[98/117] tyan/s2850 ok.
Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[99/117] tyan/s2875 ok.
Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[100/117] tyan/s2880 ok.
Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[101/117] tyan/s2881 ok.
Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[102/117] tyan/s2882 ok.
Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[103/117] tyan/s2885 ok.
Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[104/117] tyan/s2891 ok.
Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/tyan/s2891/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[105/117] tyan/s2892 ok.
Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/tyan/s2892/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[106/117] tyan/s2895 ok.
Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/tyan/s2895/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
[107/117] tyan/s2912 fail.
[108/117] tyan/s2912_fam10 ok.
Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/tyan/s2912_fam10/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[109/117] tyan/s4880 ok.
Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[110/117] tyan/s4882 ok.
Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x2000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[111/117] via/epia-cn fail.
[112/117] via/epia-m ok.
Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/via/epia-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[113/117] via/epia-m700 ok.
Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/via/epia-m700/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_SIZE = 0x2000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HEAP_SIZE = 0x5000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[114/117] via/epia-n ok.
Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/via/epia-n/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN400_VIDEO_MB_128MB = 0x0
+CONFIG_CN400_VIDEO_MB_16MB = 0x0
+CONFIG_CN400_VIDEO_MB_32MB = 0x1
+CONFIG_CN400_VIDEO_MB_64MB = 0x0
+CONFIG_CN400_VIDEO_MB_8MB = 0x0
+CONFIG_CN400_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[115/117] via/epia ok.
Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[116/117] via/pc2500e fail.
[117/117] via/vt8454c ok.
Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-5066/targets/via/vt8454c/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
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