coreboot September 2009

coreboot@coreboot.org

62 participants
305 discussions

SeaBIOS+libpayload?
by Kevin O'Connor 30 Sep '09

30 Sep '09

Hi, There has been suggestions recently on using parts of libpayload in seabios. The following is my thoughts on some challenges of such an integration: Constrained memory - unlike a normal libpayload app, SeaBIOS must reserve all memory that it uses during runtime in the e820 map. This reserved memory then can't be used by the OS. Naturally, this means reserved memory needs to be kept to a minimum - it would be a shame to keep any sizable amount of memory unusable by the OS just so that it can be used for the 5 seconds or so before the OS starts. I'd say all code and ram used by SeaBIOS runtime shouldn't exceed 256KB. Right now, SeaBIOS is using around 80K. Also, code needed from 16bit mode must be located in the first 1Meg of ram. The constraints on memory here are even stricter - I'd say all code and ram here shouldn't exceed 100K. As a result of these restrictions, SeaBIOS code uses different memory "zones" (6 of them) and purposely allocates ram from the different zones to optimize the memory footprint. (For example, an allocation needed only during init wouldn't be reserved in the e820, an allocation needed during runtime but not from 16bit code would be in e820 high-mem, and only those allocations needed during 16bit run-time would go into the e820 low-mem.) Support for 16bit mode - SeaBIOS is fundamentally a 16bit bios implementation and that means supporting 16bit callers. Because SeaBIOS uses gcc, this isn't as difficult as it may seem, but it does require implementation restrictions. All code needs to be compiled by the seabios build (to manipulate the assembler and set compiler flags); it's not possible to just link in a library. Also, special macro wrappers must be placed in the code around all non-stack memory accesses. Because of these memory restrictions, seabios tends to pass parameters by value (so as to avoid lots of macro accesses). Seabios also tends to avoid function pointers (is the pointer to the 16bit version of the function or to the 32bit version of the function?). Finally, available stack space in 16bit mode is severely constrained. A hw irq handler probably shouldn't use more than 100 bytes of stack. A regular 16bit handler probably shouldn't use more than 250 bytes of stack. Seabios must work without coreboot - seabios can be used natively with qemu, bochs, and kvm. This isn't necessarily a problem for pulling in a libpayload driver, but it does constrain other parts of libpayload. (For example, it's not possible to assume a coreboot table will be found). Parts of libpayload tend to assume other parts of libpayload are available - this can be difficult for "cherry picking" drivers. For example, usb requires malloc, in/out, printf, mdelay, pci_config_write, etc. These can be redirected, but that's troublesome for maintenance because the different implementations may have subtly different behavior. Alternatively, one could try to introduce more parts of libpayload into seabios, but that further expands the scope of conflicts. For example, should the libpayload version of malloc know how to do e820 map allocations? On the flip side, the clear advantage of using libpayload in seabios is a reduction of the overall code that needs to be maintained. It could also lead to better test coverage of the code and a higher quality. In general, I think this raises a high-level question. Is there a desire to introduce the memory and operating constraints into the libpayload code that SeaBIOS will need? This is a bit of a difficult question, as the other users (eg, filo) have no need to worry about these restrictions and it will definitely make maintenance and testing harder. My general feel has been that this isn't worth the cost. The amount of code being duplicated I would estimate is around 3000 lines. This is unarguably very tricky code (eg, hw init, timing, malloc), but there is not an overwhelming amount of it. Thoughts? -Kevin

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Inteltool patch v4
by Maciej Pijanka 30 Sep '09

30 Sep '09

Hello This is last version, includes detecting southbridge using device_class not device location on bus as Stefan suggested, also will tell if find more than one device with device_class 0x601 and notify which one it used (it will be first but may depend on order of devices inside structures returned by libpci). Regards Maciej -- Maciej Pijanka, PLD-Linux Developer, Reg Linux user #133161 POE/Perl user

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build service results for r4695
by coreboot information 30 Sep '09

30 Sep '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4695 to the coreboot repository. This caused the following changes: Change Log: Hm, quickfix to prevent the following crash, no idea yet what happens: *** glibc detected *** ././inteltool: double free or corruption (top): 0x08db0260 *** Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4695&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4695&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4695&device=briq&vendor=to… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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Asus M2N4-SLI details
by Andrew Morgan 30 Sep '09

30 Sep '09

Attached is the output of various tools run on an Asus M2N4-SLI board. Looks like mptable didn't work correctly? -- Andrew. /* * This file is part of the coreboot project. * * Copyright (C) 200x TODO <TODO@TODO> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifdef GETPIR /* TODO: Drop this when copying to coreboot. */ #include "pirq_routing.h" /* TODO: Drop this when copying to coreboot. */ #else /* TODO: Drop this when copying to coreboot. */ #include <arch/pirq_routing.h> #endif /* TODO: Drop this when copying to coreboot. */ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32 + 16 * 13, /* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x00 << 3) | 0x0, /* Interrupt router dev */ 0x828, /* IRQs devoted exclusively to PCI usage */ 0, /* Vendor */ 0, /* Device */ 0, /* Miniport */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x1f, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). */ { /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x01, (0x06 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}}, 0x1, 0x0}, {0x01, (0x07 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}}, 0x2, 0x0}, {0x01, (0x01 << 3) | 0x0, {{0x02, 0xdeb8}, {0x02, 0xdeb8}, {0x02, 0xdeb8}, {0x02, 0xdeb8}}, 0x3, 0x0}, {0x05, (0x00 << 3) | 0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}}, 0x4, 0x0}, {0x04, (0x00 << 3) | 0x0, {{0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}}, 0x5, 0x0}, {0x03, (0x00 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}}, 0x6, 0x0}, {0x02, (0x00 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}}, 0x7, 0x0}, {0x00, (0x01 << 3) | 0x0, {{0x06, 0xdeb8}, {0x06, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}}, 0x0, 0x0}, {0x00, (0x02 << 3) | 0x0, {{0x07, 0xdeb8}, {0x09, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}}, 0x0, 0x0}, {0x00, (0x04 << 3) | 0x0, {{0x0a, 0xdeb8}, {0x0b, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}}, 0x0, 0x0}, {0x00, (0x0a << 3) | 0x0, {{0x0c, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}}, 0x0, 0x0}, {0x00, (0x07 << 3) | 0x0, {{0x0d, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}}, 0x0, 0x0}, {0x00, (0x08 << 3) | 0x0, {{0x0e, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}}, 0x0, 0x0}, } }; unsigned long write_pirq_routing_table(unsigned long addr) { return copy_pirq_routing_table(addr); } superiotool r4668 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Found ITE IT8716F (id=0x8716, rev=0x0) at 0x2e Register dump: idx 20 21 22 23 24 2b val 87 16 00 01 00 00 def 87 16 01 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 00 00 00 00 04 00 80 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 f2 f3 val 01 03 f8 04 00 50 00 7f def 00 03 f8 04 00 50 00 7f LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 00 00 00 00 00 50 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0 val 01 03 78 07 78 07 03 0a def 00 03 78 07 78 07 03 03 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 02 90 00 00 00 00 00 0a 00 8a 00 ff def 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 68 def 01 00 60 00 64 01 02 00 LDN 0x06 (Mouse) idx 30 70 71 f0 val 01 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd val 04 00 7f 00 01 04 1f 00 00 08 00 00 00 00 01 00 38 00 00 00 3f 00 00 00 00 00 00 00 00 00 00 00 7f 00 01 00 00 7f 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 31 00 def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x08 (MIDI port) idx 30 60 61 70 f0 val 00 03 00 0a 00 def 00 03 00 0a 00 LDN 0x09 (Game port) idx 30 60 61 val 00 02 01 def 00 02 01 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff /* generated by MPTable, version 2.0.15*/ /* as modified by RGM for coreboot */ #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> #include <string.h> #include <stdint.h> void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "LNXI "; static const char productid[12] = "P4DPE "; struct mp_config_table *mc; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); mptable: readEntry: Operation not permitted -[0000:00]-+-00.0 nVidia Corporation CK804 Memory Controller [10de:005e] +-01.0 nVidia Corporation CK804 ISA Bridge [10de:0050] +-01.1 nVidia Corporation CK804 SMBus [10de:0052] +-02.0 nVidia Corporation CK804 USB Controller [10de:005a] +-02.1 nVidia Corporation CK804 USB Controller [10de:005b] +-04.0 nVidia Corporation CK804 AC'97 Audio Controller [10de:0059] +-06.0 nVidia Corporation CK804 IDE [10de:0053] +-07.0 nVidia Corporation CK804 Serial ATA Controller [10de:0054] +-08.0 nVidia Corporation CK804 Serial ATA Controller [10de:0055] +-09.0-[0000:01]--+-06.0 XXX | \-07.0 XXX +-0a.0 nVidia Corporation CK804 Ethernet Controller [10de:0057] +-0b.0-[0000:02]-- +-0c.0-[0000:03]-- +-0d.0-[0000:04]-- +-0e.0-[0000:05]----00.0 XXX +-18.0 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] +-18.1 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] +-18.2 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] \-18.3 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103]

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build service results for r4694
by coreboot information 30 Sep '09

30 Sep '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4694 to the coreboot repository. This caused the following changes: Change Log: Add initial inteltool support for Intel 440BX/440LX and 82371AB/EB/MB. Signed-off-by: Maciej Pijanka <maciej.pijanka(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4694&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4694&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4694&device=briq&vendor=to… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4695 - trunk/util/inteltool
by svn＠coreboot.org 30 Sep '09

30 Sep '09

Author: uwe Date: 2009-09-30 19:14:24 +0200 (Wed, 30 Sep 2009) New Revision: 4695 Modified: trunk/util/inteltool/inteltool.c Log: Hm, quickfix to prevent the following crash, no idea yet what happens: *** glibc detected *** ././inteltool: double free or corruption (top): 0x08db0260 *** Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/inteltool/inteltool.c =================================================================== --- trunk/util/inteltool/inteltool.c 2009-09-30 17:05:46 UTC (rev 4694) +++ trunk/util/inteltool/inteltool.c 2009-09-30 17:14:24 UTC (rev 4695) @@ -309,7 +309,7 @@ /* Clean up */ pci_free_dev(nb); - pci_free_dev(sb); + // pci_free_dev(sb); // TODO: glibc detected "double free or corruption" pci_cleanup(pacc); return 0;

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[v2] r4694 - trunk/util/inteltool
by svn＠coreboot.org 30 Sep '09

30 Sep '09

Author: uwe Date: 2009-09-30 19:05:46 +0200 (Wed, 30 Sep 2009) New Revision: 4694 Modified: trunk/util/inteltool/gpio.c trunk/util/inteltool/inteltool.c trunk/util/inteltool/inteltool.h trunk/util/inteltool/memory.c trunk/util/inteltool/powermgt.c Log: Add initial inteltool support for Intel 440BX/440LX and 82371AB/EB/MB. Signed-off-by: Maciej Pijanka <maciej.pijanka(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/inteltool/gpio.c =================================================================== --- trunk/util/inteltool/gpio.c 2009-09-30 14:46:43 UTC (rev 4693) +++ trunk/util/inteltool/gpio.c 2009-09-30 17:05:46 UTC (rev 4694) @@ -131,6 +131,9 @@ gpio_registers = ich0_gpio_registers; size = ARRAY_SIZE(ich0_gpio_registers); break; + case PCI_DEVICE_ID_INTEL_82371XX: + printf("This southbridge has GPIOs in the PM unit.\n"); + return 1; case 0x1234: // Dummy for non-existent functionality printf("This southbridge does not have GPIOBASE.\n"); return 1; Modified: trunk/util/inteltool/inteltool.c =================================================================== --- trunk/util/inteltool/inteltool.c 2009-09-30 14:46:43 UTC (rev 4693) +++ trunk/util/inteltool/inteltool.c 2009-09-30 17:05:46 UTC (rev 4694) @@ -29,6 +29,9 @@ uint16_t vendor_id, device_id; char *name; } supported_chips_list[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, @@ -47,7 +50,8 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" } + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" }, }; #ifndef __DARWIN__ @@ -112,7 +116,7 @@ int main(int argc, char *argv[]) { struct pci_access *pacc; - struct pci_dev *sb, *nb; + struct pci_dev *sb = NULL, *nb, *dev; int i, opt, option_index = 0; unsigned int id; @@ -204,8 +208,20 @@ pci_scan_bus(pacc); /* Find the required devices */ + for (dev = pacc->devices; dev; dev = dev->next) { + pci_fill_info(dev, PCI_FILL_CLASS); + /* The ISA/LPC bridge can be 0x1f, 0x07, or 0x04 so we probe. */ + if (dev->device_class == 0x0601) { /* ISA/LPC bridge */ + if (sb == NULL) + sb = dev; + else + fprintf(stderr, "Multiple devices with class ID" + " 0x0601, using %02x%02x:%02x.%02x\n", + dev->domain, dev->bus, dev->dev, + dev->func); + } + } - sb = pci_get_dev(pacc, 0, 0, 0x1f, 0); if (!sb) { printf("No southbridge found.\n"); exit(1); Modified: trunk/util/inteltool/inteltool.h =================================================================== --- trunk/util/inteltool/inteltool.h 2009-09-30 14:46:43 UTC (rev 4693) +++ trunk/util/inteltool/inteltool.h 2009-09-30 17:05:46 UTC (rev 4694) @@ -32,28 +32,37 @@ #define INTELTOOL_VERSION "1.0" /* Tested chipsets: */ -#define PCI_VENDOR_ID_INTEL 0x8086 -#define PCI_DEVICE_ID_INTEL_ICH 0x2410 -#define PCI_DEVICE_ID_INTEL_ICH0 0x2420 -#define PCI_DEVICE_ID_INTEL_ICH2 0x2440 -#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 -#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc -#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0 -#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 -#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 -#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd -#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 -#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_DEVICE_ID_INTEL_ICH 0x2410 +#define PCI_DEVICE_ID_INTEL_ICH0 0x2420 +#define PCI_DEVICE_ID_INTEL_ICH2 0x2440 +#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 +#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc +#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0 +#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 +#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 +#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd +#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 +#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 -#define PCI_DEVICE_ID_INTEL_82810 0x7120 -#define PCI_DEVICE_ID_INTEL_82810DC 0x7122 -#define PCI_DEVICE_ID_INTEL_82845 0x1a30 -#define PCI_DEVICE_ID_INTEL_82945P 0x2770 -#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 -#define PCI_DEVICE_ID_INTEL_PM965 0x2a00 -#define PCI_DEVICE_ID_INTEL_82975X 0x277c -#define PCI_DEVICE_ID_INTEL_X58 0x3405 +#define PCI_DEVICE_ID_INTEL_82810 0x7120 +#define PCI_DEVICE_ID_INTEL_82810DC 0x7122 +#define PCI_DEVICE_ID_INTEL_82845 0x1a30 +#define PCI_DEVICE_ID_INTEL_82945P 0x2770 +#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 +#define PCI_DEVICE_ID_INTEL_PM965 0x2a00 +#define PCI_DEVICE_ID_INTEL_82975X 0x277c +#define PCI_DEVICE_ID_INTEL_X58 0x3405 +#define PCI_DEVICE_ID_INTEL_82443LX 0x7180 + +/* 82443BX has a different device ID if AGP is disabled (hardware-wise). */ +#define PCI_DEVICE_ID_INTEL_82443BX 0x7190 +#define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192 + +/* 82371AB/EB/MB use the same device ID value. */ +#define PCI_DEVICE_ID_INTEL_82371XX 0x7110 + #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) #ifndef __DARWIN__ Modified: trunk/util/inteltool/memory.c =================================================================== --- trunk/util/inteltool/memory.c 2009-09-30 14:46:43 UTC (rev 4693) +++ trunk/util/inteltool/memory.c 2009-09-30 17:05:46 UTC (rev 4694) @@ -43,6 +43,8 @@ mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; break; + case PCI_DEVICE_ID_INTEL_82443LX: + case PCI_DEVICE_ID_INTEL_82443BX: case PCI_DEVICE_ID_INTEL_82810: case PCI_DEVICE_ID_INTEL_82810DC: printf("This northbrigde does not have MCHBAR.\n"); Modified: trunk/util/inteltool/powermgt.c =================================================================== --- trunk/util/inteltool/powermgt.c 2009-09-30 14:46:43 UTC (rev 4693) +++ trunk/util/inteltool/powermgt.c 2009-09-30 17:05:46 UTC (rev 4694) @@ -203,6 +203,50 @@ { 0x7c, 4, "RESERVED" }, }; +static const io_register_t i82371xx_pm_registers[] = { + { 0x00, 2, "PMSTS" }, + { 0x02, 2, "PMEN" }, + { 0x04, 2, "PMCNTRL" }, + { 0x06, 2, "RESERVED" }, + { 0x08, 1, "PMTMR" }, + { 0x09, 1, "RESERVED" }, + { 0x0A, 1, "RESERVED" }, + { 0x0B, 1, "RESERVED" }, + { 0x0C, 2, "GPSTS" }, + { 0x0E, 2, "GPEN" }, + { 0x10, 4, "PCNTRL" }, +#if DANGEROUS_REGISTERS + /* + * This register returns 0 on read, but reading it may cause + * the system to enter C2 state, which might hang the system. + */ + { 0x14, 1, "PLVL2" }, + { 0x15, 1, "PLVL3" }, + { 0x16, 2, "RESERVED" }, +#endif + { 0x18, 2, "GLBSTS" }, + { 0x1A, 2, "RESERVED" }, + { 0x1c, 4, "DEVSTS" }, + { 0x20, 2, "GLBEN" }, + { 0x22, 1, "RESERVED" }, + { 0x23, 1, "RESERVED" }, + { 0x24, 1, "RESERVED" }, + { 0x25, 1, "RESERVED" }, + { 0x26, 1, "RESERVED" }, + { 0x27, 1, "RESERVED" }, + { 0x28, 4, "GLBCTL" }, + { 0x2C, 4, "DEVCTL" }, + /* The registers 0x30-0x33 and 0x34-0x37 allow byte-wise reads only. */ + { 0x30, 1, "GPIREG 0" }, + { 0x31, 1, "GPIREG 1" }, + { 0x32, 1, "GPIREG 2" }, + { 0x33, 1, "GPIREG 3" }, + { 0x34, 1, "GPOREG 0" }, + { 0x35, 1, "GPOREG 1" }, + { 0x36, 1, "GPOREG 2" }, + { 0x37, 1, "GPOREG 3" }, +}; + int print_pmbase(struct pci_dev *sb) { int i, size; @@ -230,6 +274,11 @@ pm_registers = ich0_pm_registers; size = ARRAY_SIZE(ich0_pm_registers); break; + case PCI_DEVICE_ID_INTEL_82371XX: + pmbase = pci_read_word(sb, 0x40) & 0xfffc; + pm_registers = i82371xx_pm_registers; + size = ARRAY_SIZE(i82371xx_pm_registers); + break; case 0x1234: // Dummy for non-existent functionality printf("This southbridge does not have PMBASE.\n"); return 1;

1 0

build service results for r4693
by coreboot information 30 Sep '09

30 Sep '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "ward" checked in revision 4693 to the coreboot repository. This caused the following changes: Change Log: Add supermicro h8dmr fam10 target. This is largely a mashup of the tyan s2912 fam10 and h8dmr k8 targets. Many, many thanks to Marc, Myles, Patrick and Stepan for all their help with this, and to Arne for doing the s2912 fam10 port. Build and boot tested. Abuild tested. There are a number of outstanding issues and caveats - see src/mainboard/supermicro/h8dmr_fam10/README. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4693&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4693&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4693&device=briq&vendor=to… If something broke during this checkin please be a pain in ward's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[v2] r4693 - in trunk/coreboot-v2: src/mainboard/supermicro src/mainboard/supermicro/h8dmr_fam10 targets/supermicro targets/supermicro/h8dmr_fam10
by svn＠coreboot.org 30 Sep '09

30 Sep '09

Author: ward Date: 2009-09-30 16:46:43 +0200 (Wed, 30 Sep 2009) New Revision: 4693 Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/README trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/chip.h trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/mainboard.c trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/mptable.c trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/spd_addr.h trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/ trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/Config-abuild.lb trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/Config-lab.lb trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/Config.lb trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/Config.lb.kernel trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/VERSION Log: Add supermicro h8dmr fam10 target. This is largely a mashup of the tyan s2912 fam10 and h8dmr k8 targets. Many, many thanks to Marc, Myles, Patrick and Stepan for all their help with this, and to Arne for doing the s2912 fam10 port. Build and boot tested. Abuild tested. There are a number of outstanding issues and caveats - see src/mainboard/supermicro/h8dmr_fam10/README. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Peter Stuge <peter(a)stuge.se> Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Config.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Config.lb 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,338 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 AMD +## Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## CONFIG_XIP_ROM_SIZE must be a power of 2. +# for testing with -O != s. FIXME +#default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 +include /config/failovercalculation.lb + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o +#needed by irq_tables and mptable and acpi_tables +object get_bus_conf.o + +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end +#object reset.o + + if CONFIG_USE_INIT + makerule ./auto.o + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" + end + else + makerule ./auto.inc + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" + action "perl -e 's/\.rodata/.rom.data/g' -pi $@" + action "perl -e 's/\.text/.section .rom.text/g' -pi $@" + end + end + +if CONFIG_USE_FAILOVER_IMAGE +else + if CONFIG_AP_CODE_IN_CAR + makerule ./apc_auto.o + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" + end + end +end + + +## +## Build our 16 bit and 32 bit coreboot entry code +## +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds + end +else + if CONFIG_USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds + end +end + +mainboardinit cpu/x86/32bit/entry32.inc + + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end + +## +## Build our reset vector (This is where coreboot is entered) +## +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds + else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds + end +else + if CONFIG_USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds + else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds + end +end + +## +## Include an id string (For safe flashing) +## +mainboardinit southbridge/nvidia/mcp55/id.inc +ldscript /southbridge/nvidia/mcp55/id.lds + +## +## ROMSTRAP table for MCP55 +## +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE + mainboardinit southbridge/nvidia/mcp55/romstrap.inc + ldscript /southbridge/nvidia/mcp55/romstrap.lds + end +else + if CONFIG_USE_FALLBACK_IMAGE + mainboardinit southbridge/nvidia/mcp55/romstrap.inc + ldscript /southbridge/nvidia/mcp55/romstrap.lds + end +end + + ## + ## Setup Cache-As-Ram + ## + mainboardinit cpu/amd/car/cache_as_ram.inc + +### +### This is the early phase of coreboot startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE + ldscript /arch/i386/lib/failover_failover.lds + end +else + if CONFIG_USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + end +end + +## +## Setup RAM +## + if CONFIG_USE_INIT + initobject auto.o + else + mainboardinit ./auto.inc + end + +## +## Include the secondary Configuration files +## +config chip.h + +dir /southbridge/nvidia/mcp55 + +chip northbridge/amd/amdfam10/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F_1207 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdfam10 #mc0 + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on + # SB on link 2.0 + chip southbridge/nvidia/mcp55 + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + end # SM + device pci 1.1 on # SM 1 +#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? +# chip drivers/generic/generic #PCIXA Slot1 +# device i2c 50 on end +# end +# chip drivers/generic/generic #PCIXB Slot1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #PCIXB Slot2 +# device i2c 52 on end +# end +# chip drivers/generic/generic #PCI Slot1 +# device i2c 53 on end +# end +# chip drivers/generic/generic #Master MCP55 PCI-E +# device i2c 54 on end +# end +# chip drivers/generic/generic #Slave MCP55 PCI-E +# device i2c 55 on end +# end + chip drivers/generic/generic #MAC EEPROM + device i2c 51 on end + end + + end # SM + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + chip drivers/pci/onboard + device pci 6.0 on end + register "rom_address" = "0xfff00000" #for 1M +# register "rom_address" = "0xfff80000" #for 512K + end + end + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on # PCI E 5 + device pci 0.0 on #nec pci-x + end + device pci 0.1 on #nec pci-x + device pci 4.0 on end #scsi + device pci 4.1 on end #scsi + end + end + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_addr" = "0x51" + end + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end + end # mc0 + + end # PCI domain + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 on end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 off end # io +# device pnp 0.9 on end # io +# end +end #root_complex Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,371 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 AMD +## Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CBFS +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_MAX_CPUS +uses CONFIG_MAX_PHYSICAL_CPUS +uses CONFIG_LOGICAL_CPUS +uses CONFIG_IOAPIC +uses CONFIG_SMP +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_NRV2B +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses COREBOOT_EXTRA_VERSION +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_SERIAL8250 +uses CONFIG_HAVE_INIT_TIMER +uses CONFIG_GDB_STUB +uses CONFIG_CROSS_COMPILE +uses CC +uses HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_USE_INIT + +uses CONFIG_SERIAL_CPU_INIT + +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID + +uses CONFIG_PCI_64BIT_PREF_MEM + +uses CONFIG_LB_MEM_TOPK + +uses CONFIG_UNCOMPRESSED + +uses CONFIG_PCI_BUS_SEGN_BITS + +uses CONFIG_AP_CODE_IN_CAR + +uses CONFIG_MEM_TRAIN_SEQ + +uses CONFIG_WAIT_BEFORE_CPUS_INIT + +uses CONFIG_AMDMCT + +uses CONFIG_USE_PRINTK_IN_CAR +uses CONFIG_CAR_FAM10 +uses CONFIG_AMD_UCODE_PATCH_FILE + +### +### Build options +### + +## +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +## +default CONFIG_ROM_SIZE=1024*1024 + +## +## CONFIG_FALLBACK_SIZE is the amount of the ROM the ROM part of the fallback image will use +default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE +default CONFIG_FAILOVER_SIZE=0x02000 + +#more 1M for pgtbl +default CONFIG_LB_MEM_TOPK=16384 + +## +## Build code for the fallback boot +## +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 + +## +## Build code to reset the motherboard from coreboot +## +default CONFIG_HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default CONFIG_HAVE_MP_TABLE=1 + +## ACPI tables will be included +default CONFIG_HAVE_ACPI_TABLES=0 + +## +## Build code to export a CMOS option table +## +default CONFIG_HAVE_OPTION_TABLE=1 + +## +## Move the default coreboot cmos range off of AMD RTC registers +## +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_PHYSICAL_CPUS=2 +default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS +default CONFIG_LOGICAL_CPUS=1 + +default CONFIG_SERIAL_CPU_INIT=0 + +default CONFIG_ENABLE_APIC_EXT_ID=1 +default CONFIG_APIC_ID_OFFSET=0x00 +default CONFIG_LIFT_BSP_APIC_ID=1 + +#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. +#2G +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 +#1G +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 +#512M +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 + +#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 + +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 + +#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device +default CONFIG_HT_CHAIN_UNITID_BASE=1 + +#real SB Unit ID, default is 0x20, mean dont touch it at last +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 + +#make the SB HT chain on bus 0, default is not (0) +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 + +#only offset for SB chain?, default is yes(1) +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 + +#allow capable device use that above 4G +#default CONFIG_PCI_64BIT_PREF_MEM=1 + +## +## enable CACHE_AS_RAM specifics +## +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc4000 +default CONFIG_DCACHE_RAM_SIZE=0x0c000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000 +default CONFIG_USE_INIT=0 + +default CONFIG_MEM_TRAIN_SEQ=2 +default CONFIG_WAIT_BEFORE_CPUS_INIT=0 +default CONFIG_AMDMCT = 1 + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default CONFIG_MAINBOARD_PART_NUMBER="h8dmr (Fam10)" +default CONFIG_MAINBOARD_VENDOR="Supermicro" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511 + +## +## Set microcode patch file name +## +## Barcelona rev Ax: "mc_patch_01000020.h" +## Barcelona rev B0, B1, BA: "mc_patch_01000084.h" +## Barcelona rev B2, B3: "mc_patch_01000083.h" +## Shanghai rev RB-C2: "mc_patch_01000086.h" +## Shanghai rev DA-C2: "mc_patch_0100009f.h" +## +#default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000086.h" +default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_0100009f.h" + +### +### coreboot layout values +### + +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 0x1e000 + +## +## Use a 32K stack +## +default CONFIG_STACK_SIZE=0x8000 + +## +## Use a 48K heap +## +default CONFIG_HEAP_SIZE=0xc0000 + +## +## Only use the option table in a normal image +## +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) + +## +## Coreboot C code runs at this location in RAM +## +default CONFIG_RAMBASE=0x00200000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_PAYLOAD = 1 + +#default CONFIG_COMPRESSED_PAYLOAD = 1 + +# CBFS will take care of payload compression +default CONFIG_UNCOMPRESSED = 1 + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +## +## The Serial Console +## +default CONFIG_USE_PRINTK_IN_CAR=1 + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 + +# Select the serial console base port +default CONFIG_TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default CONFIG_TTYS0_LCS=0x3 + +## +### Select the coreboot loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 + +## +## Select power on after power fail setting +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +default CONFIG_USE_FAILOVER_IMAGE=0 +default CONFIG_USE_FALLBACK_IMAGE=0 +default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE + +# +# CBFS +# +# +default CONFIG_CBFS=1 + +### End Options.lb +end Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/README =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/README (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/README 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,32 @@ + + +There are a number of outstanding issues: + +* we don't have the mc_patch_01000086.h CPU ucode file yet which is +referenced in a comment in src/mainboard/supermicro/h8dmr_fam10/Options.lb. +AMD has not released it yet. This is not a problem specific to this port. + +* I'm seeing toolchain issues. I can't get this tree to compile correctly with +gcc 4.3 (32 bit) - there is an optimization issue where certain parts of the +CBFS code execute very slowly. With gcc 3.4 (32 bit) that slowness +disappears. This is probably not a problem related to this port specifically. + +* setting CONFIG_DEFAULT_CONSOLE_LOGLEVEL lower than 8 simply hangs the boot +shortly after the warm reset triggered by the MCP55 code. I think this too +might be a toolchain problem (but I see it on gcc 3.4 as well as 4.3). + +* during startup, the CPU cores talk through each other on serial for a +while. Again, not an issue specific to this port. + +* to avoid very slow LZMA decompression I use this port with LZMA compression +disabled in CBFS. I'm not sure what's causing this particular slowness. + +See also this thread: http://www.coreboot.org/pipermail/coreboot/2009-September/052107.html + +Ward, 2009-09-22 + +mansoor(a)iwavesystems.com said, about the last issue: + + Try enabling CONFIG_XIP_ROM_BASE. It solved the same problem for me in my board. + +So, that's a todo. Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,137 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 +#define __ROMCC__ + +#define RAMINIT_SYSINFO 1 +#define CACHE_AS_RAM_ADDRESS_DEBUG 0 + +#define SET_NB_CFG_54 1 + +//used by raminit +#define QRANK_DIMM_SUPPORT 1 + +#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 + +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" + +#if CONFIG_USE_INIT == 0 + #include "lib/memcpy.c" +#endif + +#include "arch/i386/lib/console.c" +#include "lib/uart8250.c" +#include "console/vtxprintf.c" +#include "./arch/i386/lib/printk_init.c" + +#if 0 +static void post_code(uint8_t value) { +#if 1 + int i; + for(i=0;i<0x80000;i++) { + outb(value, 0x80); + } +#endif +} +#endif + +#include <cpu/amd/model_fxx_rev.h> +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" + +#include "lib/delay.c" + +//#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" + +#include "northbridge/amd/amdk8/debug.c" + +#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" + +#include "northbridge/amd/amdk8/amdk8_f.h" + +#include "cpu/x86/mtrr.h" +#include "cpu/amd/mtrr.h" +#include "cpu/x86/tsc.h" + +#include "northbridge/amd/amdk8/amdk8_f_pci.c" +#include "northbridge/amd/amdk8/raminit_f_dqs.c" + +static inline unsigned get_nodes(void) +{ + return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1; +} + +#include "cpu/amd/dualcore/dualcore.c" + +void hardwaremain(int ret_addr) +{ + struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + + struct node_core_id id; + + id = get_node_core_id_x(); + + print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); + + train_ram(id.nodeid, sysinfo, sysinfox); + + /* + go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp + */ + + __asm__ volatile ( + "movl %0, %%edi\n\t" + "jmp *%%edi\n\t" + :: "a"(ret_addr) + ); + + + +} +struct eregs { + uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi; + uint32_t vector; + uint32_t error_code; + uint32_t eip; + uint32_t cs; + uint32_t eflags; +}; + +void x86_exception(struct eregs *info) +{ + do { + hlt(); + } while(1); +} + + Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,380 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 +#define __ROMCC__ + +#define RAMINIT_SYSINFO 1 + +#define FAM10_SCAN_PCI_BUS 0 +#define FAM10_ALLOCATE_IO_RANGE 1 + +#define QRANK_DIMM_SUPPORT 1 + +#if CONFIG_LOGICAL_CPUS==1 +#define SET_NB_CFG_54 1 +#endif + +#define FAM10_SET_FIDVID 1 +#define FAM10_SET_FIDVID_CORE_RANGE 0 + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" + +// for enable the FAN +#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" + +static void post_code(u8 value) { + outb(value, 0x80); +} + +#if CONFIG_USE_FAILOVER_IMAGE==0 +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "lib/ramtest.c" + +#include <cpu/amd/model_10xxx_rev.h> + +//#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +#include "northbridge/amd/amdfam10/raminit.h" +#include "northbridge/amd/amdfam10/amdfam10.h" + +#endif + +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdfam10/reset_test.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" +#include "superio/winbond/w83627hf/w83627hf_early_init.c" + +#if CONFIG_USE_FAILOVER_IMAGE==0 + +#include "cpu/x86/bist.h" + +#include "northbridge/amd/amdfam10/debug.c" + +#include "cpu/amd/mtrr/amd_earlymtrr.c" + + +#include "northbridge/amd/amdfam10/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" + +static void memreset_setup(void) +{ +} + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/amdfam10/amdfam10.h" +#include "northbridge/amd/amdht/ht_wrapper.c" + +#include "include/cpu/x86/mem.h" +#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" +#include "northbridge/amd/amdfam10/raminit_amdmct.c" +#include "northbridge/amd/amdfam10/amdfam10_pci.c" + +#include "resourcemap.c" + +#include "cpu/amd/quadcore/quadcore.c" + +#define MCP55_NUM 1 +#define MCP55_USE_NIC 1 +#define MCP55_USE_AZA 1 + +#define MCP55_PCI_E_X_0 4 + +#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" +#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" + +#include "cpu/amd/car/copy_and_run.c" + +#include "cpu/amd/car/post_cache_as_ram.c" + +#include "cpu/amd/model_10xxx/init_cpus.c" + +#include "cpu/amd/model_10xxx/fidvid.c" + +#endif + +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) + +#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" +#include "northbridge/amd/amdfam10/early_ht.c" + + +static void sio_setup(void) +{ + + unsigned value; + uint32_t dword; + uint8_t byte; + enable_smbus(); +// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ + smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ + + byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword |= (1<<0); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); + + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); + dword |= (1<<16); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); + +} + +void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) +{ + unsigned last_boot_normal_x = last_boot_normal(); + + /* Is this a cpu only reset? or Is this a secondary cpu? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal_x) { + goto normal_image; + } else { + goto fallback_image; + } + } + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the mcp55 */ + mcp55_enable_rom(); + + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal_x) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ + ); + + fallback_image: +#if CONFIG_HAVE_FAILOVER_BOOT==1 + __asm__ volatile ("jmp __fallback_image" + : /* outputs */ + : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ + ) +#endif + ; +} +#endif +void real_main(unsigned long bist, unsigned long cpu_init_detectedx); + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 + failover_process(bist, cpu_init_detectedx); + #else + real_main(bist, cpu_init_detectedx); + #endif +#else + #if CONFIG_USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); + #endif + real_main(bist, cpu_init_detectedx); +#endif +} + +#if CONFIG_USE_FAILOVER_IMAGE==0 +#include "spd_addr.h" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + u32 bsp_apicid = 0; + u32 val; + u32 wants_reset; + msr_t msr; + + post_code(0x30); + + if (bist == 0) { + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + } + + post_code(0x32); + + pnp_enter_ext_func_mode(SERIAL_DEV); + pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); + w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); + pnp_exit_ext_func_mode(SERIAL_DEV); + + uart_init(); + console_init(); + printk_debug("\n"); + + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + val = cpuid_eax(1); + printk_debug("BSP Family_Model: %08x \n", val); + printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n"); + printk_debug("bsp_apicid = %02x \n", bsp_apicid); + printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx); + + /* Setup sysinfo defaults */ + set_sysinfo_in_ram(0); + + update_microcode(val); + post_code(0x33); + + cpuSetAMDMSR(); + post_code(0x34); + + amd_ht_init(sysinfo); + post_code(0x35); + + /* Setup nodes PCI space and start core 0 AP init. */ + finalize_node_setup(sysinfo); + + /* Setup any mainboard PCI settings etc. */ + setup_mb_resource_map(); + post_code(0x36); + + /* wait for all the APs core0 started by finalize_node_setup. */ + /* FIXME: A bunch of cores are going to start output to serial at once. + * It would be nice to fixup prink spinlocks for ROM XIP mode. + * I think it could be done by putting the spinlock flag in the cache + * of the BSP located right after sysinfo. + */ + + wait_all_core0_started(); +#if CONFIG_LOGICAL_CPUS==1 + /* Core0 on each node is configured. Now setup any additional cores. */ + printk_debug("start_other_cores()\n"); + start_other_cores(); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); +#endif + + post_code(0x38); + +#if FAM10_SET_FIDVID == 1 + msr = rdmsr(0xc0010071); + printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + + /* FIXME: The sb fid change may survive the warm reset and only + * need to be done once.*/ + + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + post_code(0x39); + + if (!warm_reset_detect(0)) { // BSP is node 0 + init_fidvid_bsp(bsp_apicid, sysinfo->nodes); + } else { + init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + } + + post_code(0x3A); + + /* show final fid and vid */ + msr=rdmsr(0xc0010071); + printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); +#endif + + wants_reset = mcp55_early_setup_x(); + + /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + if (!warm_reset_detect(0)) { + print_info("...WARM RESET...\n\n\n"); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } + + if (wants_reset) + printk_debug("mcp55_early_setup_x wanted additional reset!\n"); + + post_code(0x3B); + +/* It's the time to set ctrl in sysinfo now; */ +printk_debug("fill_mem_ctrl()\n"); +fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + +post_code(0x3D); + +//printk_debug("enable_smbus()\n"); +// enable_smbus(); /* enable in sio_setup */ + +post_code(0x3E); + + memreset_setup(); + +post_code(0x40); + + + printk_debug("raminit_amdmct()\n"); + raminit_amdmct(sysinfo); + post_code(0x41); + +// printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); + post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. + post_code(0x42); // Should never see this post code. + +} + + +#endif Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/chip.h =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/chip.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/chip.h 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config { +}; Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/cmos.layout (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/cmos.layout 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,119 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 AMD +## Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 quad_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory1 + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,171 @@ +dir /southbridge/nvidia/mcp55 + +chip northbridge/amd/amdfam10/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F_1207 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdfam10 #mc0 + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on + # SB on link 2.0 + chip southbridge/nvidia/mcp55 + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + end # SM + device pci 1.1 on # SM 1 +#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? +# chip drivers/generic/generic #PCIXA Slot1 +# device i2c 50 on end +# end +# chip drivers/generic/generic #PCIXB Slot1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #PCIXB Slot2 +# device i2c 52 on end +# end +# chip drivers/generic/generic #PCI Slot1 +# device i2c 53 on end +# end +# chip drivers/generic/generic #Master MCP55 PCI-E +# device i2c 54 on end +# end +# chip drivers/generic/generic #Slave MCP55 PCI-E +# device i2c 55 on end +# end + chip drivers/generic/generic #MAC EEPROM + device i2c 51 on end + end + + end # SM + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + chip drivers/pci/onboard + device pci 6.0 on end + register "rom_address" = "0xfff00000" #for 1M +# register "rom_address" = "0xfff80000" #for 512K + end + end + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on # PCI E 5 + device pci 0.0 on #nec pci-x + end + device pci 0.1 on #nec pci-x + device pci 4.0 on end #scsi + device pci 4.1 on end #scsi + end + end + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_addr" = "0x51" + end + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end + end # mc0 + + end # PCI domain + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 on end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 off end # io +# device pnp 0.9 on end # io +# end +end #root_complex Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#if CONFIG_LOGICAL_CPUS==1 +#include <cpu/amd/dualcore.h> +#endif + +#include <cpu/amd/amdfam10_sysconf.h> + +#include <stdlib.h> +#include "mb_sysconf.h" + +// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +struct mb_sysconf_t mb_sysconf; + +/* Here you only need to set value in pci1234 for HT-IO that could be +installed or not You may need to preset pci1234 for HTIO board, please +refer to src/northbridge/amd/amdfam10/get_pci1234.c for detail */ +static u32 pci1234x[] = { + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, + }; + + +/* HT Chain device num, actually it is unit id base of every ht device +in chain, assume every chain only have 4 ht device at most */ + +static unsigned hcdnx[] = { + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, +}; + +extern void get_pci1234(void); + +static unsigned get_bus_conf_done = 0; + +void get_bus_conf(void) +{ + + unsigned apicid_base; + struct mb_sysconf_t *m; + + device_t dev; + int i, j; + + if(get_bus_conf_done==1) return; //do it only once + + get_bus_conf_done = 1; + + sysconf.mb = &mb_sysconf; + + m = sysconf.mb; + memset(m, 0, sizeof(struct mb_sysconf_t)); + + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for(i=0;i<sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_pci1234(); + + m->bus_type[0] = 1; //pci + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff; + + /* MCP55 */ + dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0)); + if (dev) { + m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); + } + + for(i=2; i<8;i++) { + dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); + if (dev) { + m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 ); + } + } + + for(i=0; i< sysconf.hc_possible_num; i++) { + if(!(sysconf.pci1234[i] & 0x1) ) continue; + + unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; + unsigned busn_max = (sysconf.pci1234[i] >> 20) & 0xff; + for (j = busn; j <= busn_max; j++) + m->bus_type[j] = 1; + if(m->bus_isa <= busn_max) + m->bus_isa = busn_max + 1; + printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa); + } + +/*I/O APICs: APIC ID Version State Address*/ +#if CONFIG_LOGICAL_CPUS==1 + apicid_base = get_apicid_base(1); +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#endif + m->apicid_mcp55 = apicid_base+0; + +} Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file was generated by getpir.c, do not modify! + * (but if you do, please run checkpir on it to verify) + * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +#include <cpu/amd/amdfam10_sysconf.h> +#include "mb_sysconf.h" + +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, + uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, + uint8_t slot, uint8_t rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +extern void get_bus_conf(void); + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + unsigned slot_num; + uint8_t *v; + struct mb_sysconf_t *m; + unsigned sbdn; + + uint8_t sum=0; + int i; + + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + sbdn = sysconf.sbdn; + m = sysconf.mb; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk_info("Writing IRQ routing tables to 0x%x...", addr); + + pirq = (void *)(addr); + v = (uint8_t *)(addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = m->bus_mcp55[0]; + pirq->rtr_devfn = ((sbdn+6)<<3)|0; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x10de; + pirq->rtr_device = 0x0370; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *) ( &pirq->checksum + 1); + slot_num = 0; +//pci bridge + write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + + for(i=1; i< sysconf.hc_possible_num; i++) { + if(!(sysconf.pci1234[i] & 0x1) ) continue; + unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; + unsigned devn = sysconf.hcdn[i] & 0xff; + + write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + } + +#if CONFIG_CBB + write_pirq_info(pirq_info, CONFIG_CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + if(sysconf.nodes>32) { + write_pirq_info(pirq_info, CONFIG_CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + } +#endif + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk_info("done.\n"); + + return (unsigned long) pirq_info; + +} Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/mainboard.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/mainboard.c 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("Supermicro H8DMR Mainboard (Family 10)") +}; Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MB_SYSCONF_H +#define MB_SYSCONF_H + +struct mb_sysconf_t { + unsigned char bus_isa; + unsigned char bus_mcp55[8]; //1 + unsigned apicid_mcp55; + unsigned bus_type[256]; + +}; + +#endif + Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/mptable.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/mptable.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/mptable.c 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,162 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> + +#include <cpu/amd/amdfam10_sysconf.h> + +#include "mb_sysconf.h" + +extern void get_bus_conf(void); + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "SUPERMIC"; + static const char productid[12] = "H8DMR "; + struct mp_config_table *mc; + struct mb_sysconf_t *m; + unsigned sbdn; + + int i,j; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + get_bus_conf(); + sbdn = sysconf.sbdn; + m = sysconf.mb; + +/*Bus: Bus ID Type*/ + /* define bus and isa numbers */ + for(j= 0; j < 256 ; j++) { + if(m->bus_type[j]) + smp_write_bus(mc, j, "PCI "); + } + smp_write_bus(mc, m->bus_isa, "ISA "); + +/*I/O APICs: APIC ID Version State Address*/ + { + device_t dev; + struct resource *res; + uint32_t dword; + + dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_1); + if (res) { + smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base); + } + + dword = 0x43c6c643; + pci_write_config32(dev, 0x7c, dword); + + dword = 0x81001a00; + pci_write_config32(dev, 0x80, dword); + + dword = 0xd00012d2; + pci_write_config32(dev, 0x84, dword); + + } + + + } + + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_mcp55, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_mcp55, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_mcp55, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_mcp55, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_mcp55, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_mcp55, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_mcp55, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 + + for(j=7; j>=2; j--) { + if(!m->bus_mcp55[j]) continue; + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + } + } + + for(j=0; j<1; j++) + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); + } + +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,286 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static void setup_mb_resource_map(void) +{ + static const unsigned int register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR_FAM10 + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR_FAM10 + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ +// WARD CHANGED + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff020, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ + // WARD CHANGED + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000033, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration region i + */ + // WARD CHANGED + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + + }; + + int max; + max = ARRAY_SIZE(register_values); + setup_resource_map(register_values, max); +} + Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/spd_addr.h =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/spd_addr.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/spd_addr.h 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * This file defines the SPD addresses for the mainboard. Must be included in + * cache_as_ram_auto.c + */ + +#define RC00 0 +#define RC01 1 +#define RC02 2 +#define RC03 3 +#define RC04 4 +#define RC05 5 +#define RC06 6 +#define RC07 7 +#define RC08 8 +#define RC09 9 +#define RC10 10 +#define RC11 11 +#define RC12 12 +#define RC13 13 +#define RC14 14 +#define RC15 15 +#define RC16 16 +#define RC17 17 +#define RC18 18 +#define RC19 19 +#define RC20 20 +#define RC21 21 +#define RC22 22 +#define RC23 23 +#define RC24 24 +#define RC25 25 +#define RC26 26 +#define RC27 27 +#define RC28 28 +#define RC29 29 +#define RC30 30 +#define RC31 31 + +#define RC32 32 +#define RC33 33 +#define RC34 34 +#define RC35 35 +#define RC36 36 +#define RC37 37 +#define RC38 38 +#define RC39 39 +#define RC40 40 +#define RC41 41 +#define RC42 42 +#define RC43 43 +#define RC44 44 +#define RC45 45 +#define RC46 46 +#define RC47 47 +#define RC48 48 +#define RC49 49 +#define RC50 50 +#define RC51 51 +#define RC52 52 +#define RC53 53 +#define RC54 54 +#define RC55 55 +#define RC56 56 +#define RC57 57 +#define RC58 58 +#define RC59 59 +#define RC60 60 +#define RC61 61 +#define RC62 62 +#define RC63 63 + + +#define DIMM0 0x50 +#define DIMM1 0x51 +#define DIMM2 0x52 +#define DIMM3 0x53 +#define DIMM4 0x54 +#define DIMM5 0x55 +#define DIMM6 0x56 +#define DIMM7 0x57 + + +static const u8 spd_addr[] = { + //first node + RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + //second node + RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, +#endif +}; + Added: trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/Config-abuild.lb (rev 0) +++ trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/Config-abuild.lb 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,30 @@ +# This will make a target directory of ./VENDOR_MAINBOARD + +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD + +option CC="CROSSCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + +__COMPRESSION__ +__LOGLEVEL__ + +romimage "normal" + option COREBOOT_EXTRA_VERSION=".0-normal" + payload __PAYLOAD__ +end + +romimage "fallback" + option CONFIG_USE_FALLBACK_IMAGE=1 + option COREBOOT_EXTRA_VERSION=".0-fallback" + payload __PAYLOAD__ +end + +romimage "failover" + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option COREBOOT_EXTRA_VERSION=".0-failover" +end + +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" Added: trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/Config-lab.lb =================================================================== --- trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/Config-lab.lb (rev 0) +++ trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/Config-lab.lb 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,37 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 AMD +## Written by Yinghai Lu <yinghailu(a)gmail.com> for AMD. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target h8dmr_fam10 +mainboard supermicro/h8dmr_fam10 + +romimage "fallback" + option CONFIG_USE_FALLBACK_IMAGE=1 + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + payload ../payload.elf +end + +romimage "failover" + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" +end + +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover" Added: trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/Config.lb =================================================================== --- trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/Config.lb (rev 0) +++ trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/Config.lb 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,44 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 AMD +## Written by Yinghai Lu <yinghailu(a)gmail.com> for AMD. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target h8dmr_fam10 +mainboard supermicro/h8dmr_fam10 + +romimage "normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + payload /personal/projects/coreboot/payloads/seabios.elf +# payload ../payload.elf +end + +romimage "fallback" + option CONFIG_USE_FALLBACK_IMAGE=1 + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + payload /personal/projects/coreboot/payloads/seabios.elf +# payload ../payload.elf +end + +romimage "failover" + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" +end + +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" Added: trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/Config.lb.kernel =================================================================== --- trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/Config.lb.kernel (rev 0) +++ trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/Config.lb.kernel 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1,75 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 AMD +## Written by Yinghai Lu <yinghailu(a)gmail.com> for AMD. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target h8dmr +mainboard supermicro/h8dmr + +option ROM_SIZE=0x200000 +option FALLBACK_SIZE=(ROM_SIZE-0x1000) + +romimage "fallback" + option USE_FAILOVER_IMAGE=0 + option USE_FALLBACK_IMAGE=1 + option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 + option CONFIG_PRECOMPRESSED_PAYLOAD=1 +# option ROM_IMAGE_SIZE=0x19800 + option ROM_IMAGE_SIZE=0x18000 +# option ROM_IMAGE_SIZE=0x15800 +# option ROM_IMAGE_SIZE=0x13800 + option XIP_ROM_SIZE=0x40000 + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" +# payload ../../../payloads/tg3--ide_disk.zelf +# payload ../../../payloads/filo.elf +# payload ../../../payloads/filo_mem.elf +# payload ../../../payloads/filo.zelf +# payload ../../../payloads/tg3--filo_hda2.zelf +# payload ../../../payloads/tg3.zelf +# payload ../../../../payloads/tg3_vga.zelf +# payload ../../../../payloads/memtest +# payload ../../../../payloads/adlo.elf +# payload ../../../../payloads/e1000_vga.zelf +# payload ../../../../payloads/filo_hda.zelf +# payload ../../../../payloads/tg3--filo_hda2_vga.zelf +# payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf +# payload ../../../../payloads/tg3--filo_hda2_vga_5.4.1.zelf +# payload ../../../../payloads/tg3--filo_hda2_vga_5.4.2.zelf + payload /home/yhlu/olpc-payload.elf.lzma +# payload ../../../../payloads/filo_hda.zelf +# payload ../../../../payloads/filo_hda2_novga.zelf +# payload ../../../payloads/tg3_com2.zelf +# payload ../../../payloads/e1000--filo.zelf +# payload ../../../payloads/tg3--e1000--filo.zelf +# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf +# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf +# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf +end + +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" +end + + +buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" +#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" Added: trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/VERSION =================================================================== --- trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/VERSION (rev 0) +++ trunk/coreboot-v2/targets/supermicro/h8dmr_fam10/VERSION 2009-09-30 14:46:43 UTC (rev 4693) @@ -0,0 +1 @@ +_h8dmr

1 0

Corebootv2 failing to build
by David Houston 30 Sep '09

30 Sep '09

Not sure why? Believe it has something to do with the bold. I am trying to build a 1mb rom. Where is the best place to set this? ---->snip<---- /home/dave/code/cbtmp/coreboot-v2/src/cpu/x86/mtrr/earlymtrr.c:22:3: error: #error *"CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"* In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:115: /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h:522: warning: redundant redeclaration of ‘soft_reset’ /home/dave/code/cbtmp/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c:51: note: previous definition of ‘soft_reset’ was here In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:118: /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:841: warning: redundant redeclaration of ‘get_nodes’ /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c:1747: note: previous definition of ‘get_nodes’ was here In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:120: /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c:732:2: warning: #warning "FIXME implement a better test for opterons" In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:120: /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c:1261: warning: no previous prototype for ‘memory_end_k’ In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:120: /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c:1701: warning: no previous prototype for ‘find_optimum_spd_latency’ /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c:1949: warning: no previous prototype for ‘get_dimm_Trc_clocks’ /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c:1970:2: warning: #warning We should die here or at least disable this bank. In file included from /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c:2883, from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:120: /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c:134: warning: function declaration isn’t a prototype /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c:142: warning: function declaration isn’t a prototype /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c:1832: warning: no previous prototype for ‘s3_save_nvram_early’ /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c:1837: warning: no previous prototype for ‘s3_load_nvram_early’ In file included from /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c:2994, from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:120: /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/exit_from_self.c:20: warning: no previous prototype for ‘exit_from_self’ In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:122: /home/dave/code/cbtmp/coreboot-v2/src/lib/generic_sdram.c:15: warning: no previous prototype for ‘sdram_no_memory’ /home/dave/code/cbtmp/coreboot-v2/src/lib/generic_sdram.c:25: warning: no previous prototype for ‘sdram_initialize’ In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:143: /home/dave/code/cbtmp/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c:22: warning: redundant redeclaration of ‘set_ht_link_buffer_counts_chain’ /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:723: note: previous definition of ‘set_ht_link_buffer_counts_chain’ was here /home/dave/code/cbtmp/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c: In function ‘mcp55_early_pcie_setup’: /home/dave/code/cbtmp/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c:180: warning: large integer implicitly truncated to unsigned type /home/dave/code/cbtmp/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c: In function ‘mcp55_early_setup_x’: /home/dave/code/cbtmp/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c:391: warning: unused variable ‘j’ /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c: At top level: /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:233: warning: no previous prototype for ‘cache_as_ram_main’ /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c: In function ‘real_main’: /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:262: warning: initialization makes pointer from integer without a cast make[1]: *** [cache_as_ram_auto.inc] Error 1 make: *** [normal/coreboot.rom] Error 2 :In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:60: /home/dave/code/cbtmp/coreboot-v2/src/pc80/serial.c:101: warning: no previous prototype for ‘uart_init’ In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:66: /home/dave/code/cbtmp/coreboot-v2/src/lib/ramtest.c:137: warning: no previous prototype for ‘ram_check’ In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:72: /home/dave/code/cbtmp/coreboot-v2/src/cpu/amd/model_fxx/apic_timer.c:6: warning: no previous prototype for ‘init_timer’ /home/dave/code/cbtmp/coreboot-v2/src/cpu/amd/model_fxx/apic_timer.c:19: warning: no previous prototype for ‘udelay’ In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:73: /home/dave/code/cbtmp/coreboot-v2/src/lib/delay.c:2: warning: no previous prototype for ‘mdelay’ /home/dave/code/cbtmp/coreboot-v2/src/lib/delay.c:9: warning: no previous prototype for ‘delay’ In file included from /home/dave/code/cbtmp/coreboot-v2/src/cpu/amd/mtrr/amd_earlymtrr.c:5, from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:88: /home/dave/code/cbtmp/coreboot-v2/src/cpu/x86/mtrr/earlymtrr.c:22:3: error: #error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE" In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:115: /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h:522: warning: redundant redeclaration of ‘soft_reset’ /home/dave/code/cbtmp/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c:51: note: previous definition of ‘soft_reset’ was here In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:118: /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:841: warning: redundant redeclaration of ‘get_nodes’ /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c:1747: note: previous definition of ‘get_nodes’ was here In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:120: /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c:732:2: warning: #warning "FIXME implement a better test for opterons" In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:120: /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c:1261: warning: no previous prototype for ‘memory_end_k’ In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:120: /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c:1701: warning: no previous prototype for ‘find_optimum_spd_latency’ /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c:1949: warning: no previous prototype for ‘get_dimm_Trc_clocks’ /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c:1970:2: warning: #warning We should die here or at least disable this bank. In file included from /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c:2883, from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:120: /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c:134: warning: function declaration isn’t a prototype /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c:142: warning: function declaration isn’t a prototype /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c:1832: warning: no previous prototype for ‘s3_save_nvram_early’ /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c:1837: warning: no previous prototype for ‘s3_load_nvram_early’ In file included from /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c:2994, from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:120: /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/exit_from_self.c:20: warning: no previous prototype for ‘exit_from_self’ In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:122: /home/dave/code/cbtmp/coreboot-v2/src/lib/generic_sdram.c:15: warning: no previous prototype for ‘sdram_no_memory’ /home/dave/code/cbtmp/coreboot-v2/src/lib/generic_sdram.c:25: warning: no previous prototype for ‘sdram_initialize’ In file included from /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:143: /home/dave/code/cbtmp/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c:22: warning: redundant redeclaration of ‘set_ht_link_buffer_counts_chain’ /home/dave/code/cbtmp/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:723: note: previous definition of ‘set_ht_link_buffer_counts_chain’ was here /home/dave/code/cbtmp/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c: In function ‘mcp55_early_pcie_setup’: /home/dave/code/cbtmp/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c:180: warning: large integer implicitly truncated to unsigned type /home/dave/code/cbtmp/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c: In function ‘mcp55_early_setup_x’: /home/dave/code/cbtmp/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c:391: warning: unused variable ‘j’ /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c: At top level: /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:233: warning: no previous prototype for ‘cache_as_ram_main’ /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c: In function ‘real_main’: /home/dave/code/cbtmp/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c:262: warning: initialization makes pointer from integer without a cast make[1]: *** [cache_as_ram_auto.inc] Error 1 make: *** [normal/coreboot.rom] Error 2 ---->snip<---- -- Dave ------------- root(a)crankyadmin.net cranky(a)archlinux.us

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coreboot September 2009