coreboot September 2009

coreboot@coreboot.org

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305 discussions

#144: TYAN S7012 support
by coreboot 15 Jan '10

15 Jan '10

#144: TYAN S7012 support --------------------------------------------------------+------------------- Reporter: john@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Keywords: TYAN S7012 Intel ICH10R SST SST25VF032B | Dependencies: Patchstatus: there is no patch | --------------------------------------------------------+------------------- I'm unable to flash a system that runs on a TYAN S7012 motherboard. # flashrom -w bios.bin flashrom v0.9.0-r659 No coreboot table found. Found chipset "Intel ICH10R", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "SST SST25VF032B" (4096 KB, SPI) at physical address 0xffc00000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... COMPLETE. Verifying flash... VERIFY FAILED at 0x00002000! Expected=0x00, Read=0xff Running it with verbose the following error messages are printed out (repeating). Writing flash chip... Invalid OPCODE 0x06 due to SPI master limitation, ignoring and hoping it will be run as PREOP Transaction error! run OPCODE 0x02 failed spi_byte_program failed during command execution Invalid OPCODE 0x06 due to SPI master limitation, ignoring and hoping it will be run as PREOP Transaction error! run OPCODE 0x02 failed spi_byte_program failed during command execution Invalid OPCODE 0x06 CONFIG_STRICT_DEVMEM is not set in my kernel. Anything I should try out? -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/144> coreboot <http://www.coreboot.org/>

1 2

LED Postcode on Mainboard
by Crankyadmin 17 Oct '09

17 Oct '09

Hi all, Are these unique to the mainboard or are they generic of the bios in this case Coreboot? I have a build of coreboot that builds and then displays a few numbers and bombs out on FF. Does anybody know that FF is stands for? Mainboard: Sun Workstation Ultra 20 M2 (Tyan made maybe) Chipset: MCP55

6 10

How do I turn on display with RS690 ?
by 유택연 17 Oct '09

17 Oct '09

I used coreboot with SeaBIOS and AMD's vBIOS. System booted successfully except display not turned on. I used DirectTMDS for primay display. BIOS had been red my display's EDID rom. I had seen this signals with an oscilloscope. Error ocurred on executing VGA BIOS code. How do I turn on display? Here is log message. ------------- ..... Start bios (version pre-0.4.2-20090903_180544-azalea) init ivt init bda init pic init timer tsc calibrate start=2407971776 end=2410548093 diff=2576317 CPU Mhz=1500 math cp init Find memory size Attempting to find coreboot table Found coreboot table forwarder. Now attempting to find coreboot memory map Found mainboard amd dbm690t Found CBFS header at 0xfffdffe0 Ram Size=0x1c000000 Found 1 cpu(s) malloc setup init PMM init PNPBIOS table Scan for VGA option rom Attempting to init PCI bdf 01:05.0 (dev/ven 791f1002) Searching CBFS for prefix pci1002,791f.rom Found CBFS file fallback/payload Found CBFS file fallback/coreboot_ram Found CBFS file vgaroms/radeon.rom Found CBFS file img/filo Found CBFS file Attempting to map option rom on dev 01:05.0 Option rom sizing returned 0 0 Searching CBFS for prefix vgaroms/ Found CBFS file fallback/payload Found CBFS file fallback/coreboot_ram Found CBFS file vgaroms/radeon.rom Copying data 55296@0xfff20678 to 196608@0x000c0000 Checking rom 0x000c0000 (sig aa55 size 108) Running option rom at c000:0003 fail handle_15XX:294(86): a=00004e08 b=00000080 c=00000000 d=0000c000 ds=c000 es=f000 ss=0000 si=0000abc8 di=0000b0b6 bp=00000000 sp=000079f2 cs=c000 ip=2cc2 f=0046 fail handle_15XX:294(86): a=07ff4e08 b=00000005 c=00004e17 d=0000c002 ds=c000 es=f000 ss=0000 si=00002d58 di=0000b0b6 bp=000079d6 sp=000079f2 cs=c000 ip=2c5f f=0046 fail handle_15XX:294(86): a=00004e08 b=00000000 c=0000a401 d=00000080 ds=c000 es=f000 ss=0000 si=0000abc8 di=0000b0b6 bp=000079d6 sp=000079f0 cs=c000 ip=2c19 f=0046 Searching CBFS for prefix vgaroms/ Found CBFS file img/filo Found CBFS file Turning on vga console Starting SeaBIOS (version pre-0.4.2-20090903_180544-azalea) init keyboard i8042 timeout on flush init serial Found 2 serial ports Relocating coreboot bios tables init SMBIOS tables SMBIOS ptr=0x000fdce0 table=0x1bfff800 init boot device ordering init hard drives ATA controller 0 at 2020/2040 (dev 90 prog_if 8f) ATA controller 1 at 2028/2044 (dev 90 prog_if 8f) powerup iobase=2020 st=7f powerup iobase=2020 st=7f ata_detect ataid=0 sc=7f sn=7f dh=7f powerup iobase=2020 st=7f powerup iobase=2020 st=7f ata_detect ataid=1 sc=7f sn=7f dh=7f powerup iobase=2028 st=7f powerup iobase=2028 st=7f ata_detect ataid=2 sc=7f sn=7f dh=7f powerup iobase=2028 st=7f powerup iobase=2028 st=7f ata_detect ataid=3 sc=7f sn=7f dh=7f ..... ------------------- Jaagar

2 1

[PATCH] Fix AMD 690 HIGH_TABLES
by Carl-Daniel Hailfinger 15 Oct '09

15 Oct '09

Zheng, can you please test this with HIGH_TABLES enabled (and a new FILO)? A full log would be appreciated. Thanks. This hopefully will fix AMD 690 HIGH_TABLES or at least give me an insight into why HIGH_TABLES fails. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c (Revision 4339) +++ LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c (Arbeitskopie) @@ -896,6 +896,7 @@ #if HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; +extern uint64_t uma_memory_base, uma_memory_size; #endif static void pci_domain_set_resources(device_t dev) @@ -1066,7 +1067,9 @@ } -// printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu + printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); + if ((uma_memory_base >> 10) < mmio_basek) + printk_alert("node %d: UMA memory starts below mmio_basek\n", i); /* See if I need to split the region to accomodate pci memory space */ if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { @@ -1080,7 +1083,7 @@ #if HAVE_HIGH_TABLES==1 if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = ((uma_memory_base >> 10) - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE, high_tables_base); @@ -1105,6 +1108,9 @@ sizek -= (4*1024*1024 - mmio_basek); } } + + printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); + /* If sizek == 0, it was split at mmio_basek without a hole. * Don't create an empty ram_resource. */ @@ -1116,7 +1122,7 @@ i, mmio_basek, basek, limitk); if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = ((uma_memory_base >> 10) - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; } #endif -- http://www.hailfinger.org/ Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c (Revision 4339) +++ LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c (Arbeitskopie) @@ -896,6 +896,7 @@ #if HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; +extern uint64_t uma_memory_base, uma_memory_size; #endif static void pci_domain_set_resources(device_t dev) @@ -1066,7 +1067,9 @@ } -// printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu + printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); + if ((uma_memory_base >> 10) < mmio_basek) + printk_alert("node %d: UMA memory starts below mmio_basek\n", i); /* See if I need to split the region to accomodate pci memory space */ if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { @@ -1080,7 +1083,7 @@ #if HAVE_HIGH_TABLES==1 if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = ((uma_memory_base >> 10) - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE, high_tables_base); @@ -1105,6 +1108,9 @@ sizek -= (4*1024*1024 - mmio_basek); } } + + printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); + /* If sizek == 0, it was split at mmio_basek without a hole. * Don't create an empty ram_resource. */ @@ -1116,7 +1122,7 @@ i, mmio_basek, basek, limitk); if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = ((uma_memory_base >> 10) - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; } #endif

3 6

[PATCH] Die properly if CBFS can't find a stage
by Carl-Daniel Hailfinger 14 Oct '09

14 Oct '09

cbfs_and_run_core() did not check the return code of cbfs_load_stage() and jumped to (void*)-1 on error. Die properly instead. I didn't use die() because that caused a linker error. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-asus_m2a-vm/src/arch/i386/lib/cbfs_and_run.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/arch/i386/lib/cbfs_and_run.c (Revision 4589) +++ LinuxBIOSv2-asus_m2a-vm/src/arch/i386/lib/cbfs_and_run.c (Arbeitskopie) @@ -11,6 +11,11 @@ u8 *dst; print_debug("Jumping to image.\r\n"); dst = cbfs_load_stage(filename); + if (dst == (void *) -1) { + /* We should use die() here. */ + print_emerg("Loading stage failed!\n"); + for (;;); + } print_debug("Jumping to image.\r\n"); __asm__ volatile ( -- http://www.hailfinger.org/

6 8

flashrom on MCP73
by Fabrício Ceolin 08 Oct '09

08 Oct '09

Hi guys, We are trying to make flashrom work on http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=858&… Chipset MCP73 / SIP chipset Macronix MX25L8005. We made modifications using a enable_flash_mcp55 function, but does't work. ./flashrom -V -c MX25L8005 -r -f rom Calibrating delay loop... 627M loops per second, 100 myus = 199 us. OK. No coreboot table found. Found chipset "NVIDIA MCP73", enabling flash write... OK. Probing for Macronix MX25L8005, 1024 KB: spi_command called, but no SPI chipset/strapping detected No EEPROM/flash device found. Force read (-f -r -c) requested, forcing chip probe success: Probing for Macronix MX25L8005, 1024 KB: Found chip "Macronix MX25L8005" (1024 KB) at physical address 0xfff00000. Force reading flash... spi_chip_read called, but no SPI chipset/strapping detected 0 done. How can I do works? Are there any hints? Thanks! -- Fabrício Ceolin

3 4

GPIOs on CS5536 based boards
by Daniel Mack 06 Oct '09

06 Oct '09

Hi, I'm developing on a CS5536 based board (ALIX.2D) and I'm trying to get access to the GPIO registers in order to set the LEDs on bootup. However, I seem to miss an mandatory point when trying so. As a quick hack, I added these lines to the end of southbridge_init() in coreboot-v3/southbridge/amd/cs5536/cs5536.c: outl(GPIOL_6_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); outl(GPIOL_6_CLEAR, GPIO_IO_BASE + GPIOL_OUTPUT_VALUE); According to the schematics, GPIO6 is connected to one of the LEDs found on the board, but the GPIO level does not change. I tried reading back another GPIO but the READ_BACK register reads 0xffffffff, even though the uppermost 16 bits are supposed to be 0 always. So I assume I missed some basic point. The MSR mapping should be set up at this point, as there are accesses to other GPIO related registers called from the same function. Any pointers, anyone? Thanks, Daniel

6 16

AMD 690/SB600 ACPI bug?
by Carl-Daniel Hailfinger 04 Oct '09

04 Oct '09

Hi, I read through the AMD 690/SB600 ACPI code and saw that src/mainboard/amd/pistachio/acpi/dsdt.asl src/mainboard/amd/dbm690t/acpi/dsdt.asl src/mainboard/technexion/tim8690/acpi/dsdt.asl all read STB5 from PCIe config space and then use the result as address of the SATA BAR5 without any proper bitmasking. For non-prefetchable 32-bit memory BARs this is OK, but if the BAR is either 64-bit or prefetchable or not memory, accesses to BAR5 will be screwed up. Comments are appreciated. I think that SATA BAR5 is 32-bit no-prefetch memory, but since SATA does not work if I boot with 4 GB RAM, I'm pretty paranoid about everything related to 32/64 bit issues. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[PATCH] Kill dead code in Intel E7520 raminit_test
by Carl-Daniel Hailfinger 04 Oct '09

04 Oct '09

/src/northbridge/intel/e7520/raminit_test.c is _the_ file which caused the stongest WTF!?! reaction ever when I read it. If redefines pci_read_config*() and pci_write_config*() as simple memory accesses to a local array without _any_ side effects. Same for pci_locate_device() which essentially operates on the fake pci_read_config*(). Its rdmsr() function is hardcoded to return zero and wrmsr() is empty. It has fake SPD arrays which are ignored. spd_read_byte() accesses the fake SPD arrays, then the result of spd_read_byte is discarded. It messes with setjmp() and longjmp(), but basically only uses them to hlt() upon invalid parameters to log2(). It calls raminit_main() at least 1 times and at most 73 times. It uses AMD Athlon dualcore PCI BDF in sdram_initialize() although it is an Intel chipset. It writes to stdout and stderr. (Yes, really.) Looking at this file is like watching a mass freeway pile-up. It's horrible, but you can't stop looking. Fix the majority of WTFs. Can we just rip this file out? Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-raminit_test_cleanup/src/northbridge/intel/e7520/raminit_test.c =================================================================== --- LinuxBIOSv2-raminit_test_cleanup/src/northbridge/intel/e7520/raminit_test.c (Revision 4591) +++ LinuxBIOSv2-raminit_test_cleanup/src/northbridge/intel/e7520/raminit_test.c (Arbeitskopie) @@ -14,112 +14,18 @@ return 0; } -#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \ - (((BUS) & 0xFF) << 16) | \ - (((DEV) & 0x1f) << 11) | \ - (((FN) & 0x07) << 8) | \ - ((WHERE) & 0xFF)) - #define PCI_DEV(BUS, DEV, FN) ( \ (((BUS) & 0xFF) << 16) | \ (((DEV) & 0x1f) << 11) | \ (((FN) & 0x7) << 8)) -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) - typedef unsigned device_t; -unsigned char pci_register[256*5*3*256]; - -static uint8_t pci_read_config8(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - return pci_register[addr]; -} - -static uint16_t pci_read_config16(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - return pci_register[addr] | (pci_register[addr + 1] << 8); -} - -static uint32_t pci_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - uint32_t value; - addr = dev | where; - value = pci_register[addr] | - (pci_register[addr + 1] << 8) | - (pci_register[addr + 2] << 16) | - (pci_register[addr + 3] << 24); - -#if 0 - print_debug("pcir32("); - print_debug_hex32(addr); - print_debug("):"); - print_debug_hex32(value); - print_debug("\n"); -#endif - return value; - -} - -static void pci_write_config8(device_t dev, unsigned where, uint8_t value) -{ - unsigned addr; - addr = dev | where; - pci_register[addr] = value; -} - -static void pci_write_config16(device_t dev, unsigned where, uint16_t value) -{ - unsigned addr; - addr = dev | where; - pci_register[addr] = value & 0xff; - pci_register[addr + 1] = (value >> 8) & 0xff; -} - -static void pci_write_config32(device_t dev, unsigned where, uint32_t value) -{ - unsigned addr; - addr = dev | where; - pci_register[addr] = value & 0xff; - pci_register[addr + 1] = (value >> 8) & 0xff; - pci_register[addr + 2] = (value >> 16) & 0xff; - pci_register[addr + 3] = (value >> 24) & 0xff; - -#if 0 - print_debug("pciw32("); - print_debug_hex32(addr); - print_debug(", "); - print_debug_hex32(value); - print_debug(")\n"); -#endif -} - -#define PCI_DEV_INVALID (0xffffffffU) -static device_t pci_locate_device(unsigned pci_id, device_t dev) -{ - for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return PCI_DEV_INVALID; -} - - - - static void uart_tx_byte(unsigned char data) { write(STDOUT_FILENO, &data, 1); } + static void hlt(void) { longjmp(end_buf, 2); @@ -144,161 +50,10 @@ return pow; } -typedef struct msr_struct -{ - unsigned lo; - unsigned hi; -} msr_t; - -static inline msr_t rdmsr(unsigned index) -{ - msr_t result; - result.lo = 0; - result.hi = 0; - return result; -} - -static inline void wrmsr(unsigned index, msr_t msr) -{ -} - #include "raminit.h" #define SIO_BASE 0x2e -static void hard_reset(void) -{ - /* FIXME implement the hard reset case... */ - longjmp(end_buf, 3); -} - -static void memreset_setup(void) -{ - /* Nothing to do */ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ - /* Nothing to do */ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - - -static uint8_t spd_mt4lsdt464a[256] = -{ - 0x80, 0x08, 0x04, 0x0C, 0x08, 0x01, 0x40, 0x00, 0x01, 0x70, - 0x54, 0x00, 0x80, 0x10, 0x00, 0x01, 0x8F, 0x04, 0x06, 0x01, - 0x01, 0x00, 0x0E, 0x75, 0x54, 0x00, 0x00, 0x0F, 0x0E, 0x0F, - - 0x25, 0x08, 0x15, 0x08, 0x15, 0x08, 0x00, 0x12, 0x01, 0x4E, - 0x9C, 0xE4, 0xB7, 0x46, 0x2C, 0xFF, 0x01, 0x02, 0x03, 0x04, - 0x05, 0x06, 0x07, 0x08, 0x09, 0x01, 0x02, 0x03, 0x04, 0x05, - 0x06, 0x07, 0x08, 0x09, 0x00, -}; - -static uint8_t spd_micron_512MB_DDR333[256] = -{ - 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x02, 0x48, 0x00, 0x04, 0x60, - 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01, - 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, - 0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x01, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x10, 0x6f, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0x01, 0x33, 0x36, 0x56, 0x44, 0x44, 0x46, 0x31, - 0x32, 0x38, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, - 0x33, 0x03, 0x00, 0x03, 0x23, 0x17, 0x07, 0x5a, 0xb2, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff -}; - -static uint8_t spd_micron_256MB_DDR333[256] = -{ - 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00, 0x04, 0x60, - 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01, - 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, - 0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x3c, 0x48, 0x30, 0x23, 0x50, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x58, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0x01, 0x31, 0x38, 0x56, 0x44, 0x44, 0x46, 0x36, - 0x34, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, 0x31, - 0x20, 0x01, 0x00, 0x03, 0x19, 0x17, 0x05, 0xb2, 0xf4, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -}; - -#define MAX_DIMMS 16 -static uint8_t spd_data[MAX_DIMMS*256]; - -static unsigned spd_count, spd_fail_count; -static int spd_read_byte(unsigned device, unsigned address) -{ - int result; - spd_count++; - if ((device < 0x50) || (device >= (0x50 +MAX_DIMMS))) { - result = -1; - } - else { - device -= 0x50; - - if (address > 256) { - result = -1; - } - else if (spd_data[(device << 8) | 2] != 7) { - result = -1; - } - else { - result = spd_data[(device << 8) | address]; - } - } -#if 0 - print_debug("spd_read_byte("); - print_debug_hex32(device); - print_debug(", "); - print_debug_hex32(address); - print_debug(") -> "); - print_debug_hex32(result); - print_debug("\n"); -#endif - if (spd_count >= spd_fail_count) { - result = -1; - } - return result; -} - /* no specific code here. this should go away completely */ static void coherent_ht_mainboard(unsigned cpus) { @@ -341,62 +96,13 @@ #endif }; console_init(); - memreset_setup(); sdram_initialize(ARRAY_SIZE(cpu), cpu); } -static void reset_tests(void) -{ - /* Clear the results of any previous tests */ - memset(pci_register, 0, sizeof(pci_register)); - memset(spd_data, 0, sizeof(spd_data)); - spd_count = 0; - spd_fail_count = UINT_MAX; - - pci_write_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP, - NBCAP_128Bit | - NBCAP_MP| NBCAP_BIG_MP | - /* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */ - (NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) | - NBCAP_MEMCTRL); - - pci_write_config32(PCI_DEV(0, 0x19, 3), NORTHBRIDGE_CAP, - NBCAP_128Bit | - NBCAP_MP| NBCAP_BIG_MP | - /* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */ - (NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) | - NBCAP_MEMCTRL); - -#if 0 - pci_read_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP); -#endif -} - static void test1(void) { - reset_tests(); - - memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256); -#if 0 - memcpy(&spd_data[2*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[3*256], spd_micron_512MB_DDR333, 256); - - memcpy(&spd_data[8*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[9*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[10*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[11*256], spd_micron_512MB_DDR333, 256); -#endif - raminit_main(); - -#if 0 - print_debug("spd_count: "); - print_debug_hex32(spd_count); - print_debug("\r\n"); -#endif - } @@ -407,16 +113,7 @@ if (setjmp(end_buf) != 0) { goto done; } - reset_tests(); - spd_fail_count = i; - print_debug("\r\nSPD will fail after: "); - print_debug_hex32(spd_fail_count); - print_debug(" accesses.\r\n"); - - memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256); - raminit_main(); done: -- http://www.hailfinger.org/

3 2

[PATCH]Remove non-CBFS
by Patrick Georgi 03 Oct '09

03 Oct '09

Hi, attached patch removes: - CONFIG_CBFS - anything that's conditional on CONFIG_CBFS == 0 - files that were only included for CONFIG_CBFS == 0 In particular: - elfboot - stream boot code - mini-filo and filesystems (depends on stream boot code) After this patch, there is no way to build an image that is not using CBFS anymore. I might not have caught everything, but an abuild run over everything built fine, and there is no mention of "CBFS" in the tree anymore that doesn't belong there. Kconfig is almost not affected, as it's CBFS-only, anyway. I only had to remove the CBFS configuration variable that defaulted to "true". I consider the tree ready for this as there are no known bugs anymore (except the one fixed by that other patch). Speak up if you disagree (I intend to wait with committing this patch until saturday evening CEST) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

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coreboot September 2009