coreboot September 2009

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[v2] r4674 - trunk/coreboot-v2/src/mainboard
by svn＠coreboot.org 25 Sep '09

25 Sep '09

Author: myles Date: 2009-09-25 21:09:23 +0200 (Fri, 25 Sep 2009) New Revision: 4674 Modified: trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc Log: Fix build of romcc boards. Invalid option specified: -mcpu=-mcpu=p2 romcc 0.71 released 03 April 2009 Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc 2009-09-25 18:43:02 UTC (rev 4673) +++ trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc 2009-09-25 19:09:23 UTC (rev 4674) @@ -47,14 +47,14 @@ ROMCCFLAGS ?= -mcpu=p2 $(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c - $(obj)/romcc -mcpu=$(ROMCCFLAGS) -O2 --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@ + $(obj)/romcc $(ROMCCFLAGS) -O2 --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@ ifeq ($(CONFIG_HAVE_OPTION_TABLE),y) $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h - $(obj)/romcc -mcpu=$(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + $(obj)/romcc $(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ else $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c - $(obj)/romcc -mcpu=$(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + $(obj)/romcc $(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ endif endif

1 0

build service results for r4673
by coreboot information 25 Sep '09

25 Sep '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 4673 to the coreboot repository. This caused the following changes: Change Log: some progress on kconfig: - northbridges are done - southbridges are done - Intel CPUs are done, with a design that the board only has to specify the socket it has, and the CPUs are pulled in automatically. There is some more cleanup possible in that area, but I'll do that later - a couple more mainboards compile: - intel/eagleheights - intel/jarrell - intel/mtarvon - intel/truxton - intel/xe7501devkit - sunw/ultra40 - supermicro/h8dme - tyan/s2850 - tyan/s2875 - via/epia - via/epia-cn - via/epia-m - via/epia-m700 - via/epia-n - via/pc2500e (PPC not considered, probably overlooked something) All of them only _build_, but some options are probably completely wrong. To be fixed later Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4673&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4673&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4673&device=briq&vendor=to… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

25 Sep '09

Author: oxygene Date: 2009-09-25 20:43:02 +0200 (Fri, 25 Sep 2009) New Revision: 4673 Added: trunk/coreboot-v2/src/cpu/intel/bga956/Kconfig trunk/coreboot-v2/src/cpu/intel/bga956/Makefile.inc trunk/coreboot-v2/src/cpu/intel/ep80579/Kconfig trunk/coreboot-v2/src/cpu/intel/ep80579/Makefile.inc trunk/coreboot-v2/src/cpu/intel/model_1067x/Kconfig trunk/coreboot-v2/src/cpu/intel/model_1067x/Makefile.inc trunk/coreboot-v2/src/cpu/intel/model_69x/Kconfig trunk/coreboot-v2/src/cpu/intel/model_6dx/Kconfig trunk/coreboot-v2/src/cpu/intel/model_6xx/Kconfig trunk/coreboot-v2/src/cpu/intel/model_f0x/Kconfig trunk/coreboot-v2/src/cpu/intel/model_f0x/Makefile.inc trunk/coreboot-v2/src/cpu/intel/model_f1x/Kconfig trunk/coreboot-v2/src/cpu/intel/model_f1x/Makefile.inc trunk/coreboot-v2/src/cpu/intel/model_f2x/Kconfig trunk/coreboot-v2/src/cpu/intel/model_f2x/Makefile.inc trunk/coreboot-v2/src/cpu/intel/model_f3x/Kconfig trunk/coreboot-v2/src/cpu/intel/model_f3x/Makefile.inc trunk/coreboot-v2/src/cpu/intel/model_f4x/Kconfig trunk/coreboot-v2/src/cpu/intel/model_f4x/Makefile.inc trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Kconfig trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Makefile.inc trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Kconfig trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Makefile.inc trunk/coreboot-v2/src/cpu/intel/socket_mPGA603/Kconfig trunk/coreboot-v2/src/cpu/intel/socket_mPGA603/Makefile.inc trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Kconfig trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Makefile.inc trunk/coreboot-v2/src/mainboard/intel/eagleheights/Kconfig trunk/coreboot-v2/src/mainboard/intel/eagleheights/Makefile.inc trunk/coreboot-v2/src/mainboard/intel/eagleheights/devicetree.cb trunk/coreboot-v2/src/mainboard/intel/jarrell/Kconfig trunk/coreboot-v2/src/mainboard/intel/jarrell/Makefile.inc trunk/coreboot-v2/src/mainboard/intel/mtarvon/Kconfig trunk/coreboot-v2/src/mainboard/intel/mtarvon/Makefile.inc trunk/coreboot-v2/src/mainboard/intel/truxton/Kconfig trunk/coreboot-v2/src/mainboard/intel/truxton/Makefile.inc trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Kconfig trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Makefile.inc trunk/coreboot-v2/src/mainboard/sunw/ultra40/Kconfig trunk/coreboot-v2/src/mainboard/sunw/ultra40/Makefile.inc trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Makefile.inc trunk/coreboot-v2/src/mainboard/tyan/s2850/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2850/Makefile.inc trunk/coreboot-v2/src/mainboard/tyan/s2875/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2875/Makefile.inc trunk/coreboot-v2/src/mainboard/via/epia-cn/Kconfig trunk/coreboot-v2/src/mainboard/via/epia-cn/Makefile.inc trunk/coreboot-v2/src/mainboard/via/epia-m/Kconfig trunk/coreboot-v2/src/mainboard/via/epia-m/Makefile.inc trunk/coreboot-v2/src/mainboard/via/epia-m700/Kconfig trunk/coreboot-v2/src/mainboard/via/epia-m700/Makefile.inc trunk/coreboot-v2/src/mainboard/via/epia/Kconfig trunk/coreboot-v2/src/mainboard/via/epia/Makefile.inc trunk/coreboot-v2/src/mainboard/via/pc2500e/Kconfig trunk/coreboot-v2/src/mainboard/via/pc2500e/Makefile.inc trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig trunk/coreboot-v2/src/northbridge/amd/amdfam10/Makefile.inc trunk/coreboot-v2/src/northbridge/amd/amdfam10/root_complex/Kconfig trunk/coreboot-v2/src/northbridge/intel/e7501/Kconfig trunk/coreboot-v2/src/northbridge/intel/e7501/Makefile.inc trunk/coreboot-v2/src/northbridge/intel/e7520/Kconfig trunk/coreboot-v2/src/northbridge/intel/e7520/Makefile.inc trunk/coreboot-v2/src/northbridge/intel/e7525/Kconfig trunk/coreboot-v2/src/northbridge/intel/e7525/Makefile.inc trunk/coreboot-v2/src/northbridge/intel/i3100/Kconfig trunk/coreboot-v2/src/northbridge/intel/i3100/Makefile.inc trunk/coreboot-v2/src/northbridge/intel/i82830/Kconfig trunk/coreboot-v2/src/northbridge/intel/i82830/Makefile.inc trunk/coreboot-v2/src/northbridge/intel/i855gme/Kconfig trunk/coreboot-v2/src/northbridge/intel/i855gme/Makefile.inc trunk/coreboot-v2/src/northbridge/intel/i855pm/Kconfig trunk/coreboot-v2/src/northbridge/intel/i855pm/Makefile.inc trunk/coreboot-v2/src/northbridge/via/cn700/Kconfig trunk/coreboot-v2/src/northbridge/via/cn700/Makefile.inc trunk/coreboot-v2/src/northbridge/via/vt8601/Kconfig trunk/coreboot-v2/src/northbridge/via/vt8601/Makefile.inc trunk/coreboot-v2/src/northbridge/via/vt8623/Kconfig trunk/coreboot-v2/src/northbridge/via/vt8623/Makefile.inc trunk/coreboot-v2/src/northbridge/via/vx800/Kconfig trunk/coreboot-v2/src/northbridge/via/vx800/Makefile.inc trunk/coreboot-v2/src/southbridge/amd/amd8132/Kconfig trunk/coreboot-v2/src/southbridge/amd/amd8132/Makefile.inc trunk/coreboot-v2/src/southbridge/amd/amd8151/Kconfig trunk/coreboot-v2/src/southbridge/amd/amd8151/Makefile.inc trunk/coreboot-v2/src/southbridge/amd/cs5530/Kconfig trunk/coreboot-v2/src/southbridge/amd/cs5530/Makefile.inc trunk/coreboot-v2/src/southbridge/amd/cs5535/Kconfig trunk/coreboot-v2/src/southbridge/amd/cs5535/Makefile.inc trunk/coreboot-v2/src/southbridge/broadcom/bcm21000/Kconfig trunk/coreboot-v2/src/southbridge/broadcom/bcm21000/Makefile.inc trunk/coreboot-v2/src/southbridge/broadcom/bcm5780/Kconfig trunk/coreboot-v2/src/southbridge/broadcom/bcm5780/Makefile.inc trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/Kconfig trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/Makefile.inc trunk/coreboot-v2/src/southbridge/intel/esb6300/Kconfig trunk/coreboot-v2/src/southbridge/intel/esb6300/Makefile.inc trunk/coreboot-v2/src/southbridge/intel/i3100/Kconfig trunk/coreboot-v2/src/southbridge/intel/i3100/Makefile.inc trunk/coreboot-v2/src/southbridge/intel/i82801ca/Kconfig trunk/coreboot-v2/src/southbridge/intel/i82801ca/Makefile.inc trunk/coreboot-v2/src/southbridge/intel/i82801dbm/Kconfig trunk/coreboot-v2/src/southbridge/intel/i82801dbm/Makefile.inc trunk/coreboot-v2/src/southbridge/intel/i82801er/Kconfig trunk/coreboot-v2/src/southbridge/intel/i82801er/Makefile.inc trunk/coreboot-v2/src/southbridge/intel/i82870/Kconfig trunk/coreboot-v2/src/southbridge/intel/i82870/Makefile.inc trunk/coreboot-v2/src/southbridge/intel/pxhd/Kconfig trunk/coreboot-v2/src/southbridge/intel/pxhd/Makefile.inc trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/Kconfig trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/Makefile.inc trunk/coreboot-v2/src/southbridge/sis/sis966/Kconfig trunk/coreboot-v2/src/southbridge/sis/sis966/Makefile.inc trunk/coreboot-v2/src/southbridge/via/k8t890/Kconfig trunk/coreboot-v2/src/southbridge/via/k8t890/Makefile.inc trunk/coreboot-v2/src/southbridge/via/vt8231/Kconfig trunk/coreboot-v2/src/southbridge/via/vt8231/Makefile.inc trunk/coreboot-v2/src/southbridge/via/vt8235/Kconfig trunk/coreboot-v2/src/southbridge/via/vt8235/Makefile.inc trunk/coreboot-v2/src/southbridge/winbond/w83c553/Kconfig trunk/coreboot-v2/src/southbridge/winbond/w83c553/Makefile.inc Modified: trunk/coreboot-v2/Makefile trunk/coreboot-v2/src/cpu/Kconfig trunk/coreboot-v2/src/cpu/intel/Kconfig trunk/coreboot-v2/src/cpu/intel/Makefile.inc trunk/coreboot-v2/src/cpu/intel/model_6xx/Makefile.inc trunk/coreboot-v2/src/cpu/x86/Kconfig trunk/coreboot-v2/src/mainboard/Kconfig trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc trunk/coreboot-v2/src/mainboard/intel/Kconfig trunk/coreboot-v2/src/mainboard/sunw/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/Kconfig trunk/coreboot-v2/src/mainboard/via/Kconfig trunk/coreboot-v2/src/mainboard/via/epia-m/auto.c trunk/coreboot-v2/src/mainboard/via/epia-n/Kconfig trunk/coreboot-v2/src/mainboard/via/epia-n/Makefile.inc trunk/coreboot-v2/src/mainboard/via/epia/auto.c trunk/coreboot-v2/src/northbridge/amd/Kconfig trunk/coreboot-v2/src/northbridge/amd/Makefile.inc trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig trunk/coreboot-v2/src/northbridge/intel/Kconfig trunk/coreboot-v2/src/northbridge/intel/Makefile.inc trunk/coreboot-v2/src/northbridge/intel/i440bx/Kconfig trunk/coreboot-v2/src/northbridge/intel/i440bx/Makefile.inc trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig trunk/coreboot-v2/src/northbridge/intel/i82810/Makefile.inc trunk/coreboot-v2/src/northbridge/intel/i945/Kconfig trunk/coreboot-v2/src/northbridge/intel/i945/Makefile.inc trunk/coreboot-v2/src/northbridge/via/Kconfig trunk/coreboot-v2/src/northbridge/via/Makefile.inc trunk/coreboot-v2/src/southbridge/Kconfig trunk/coreboot-v2/src/southbridge/Makefile.inc trunk/coreboot-v2/src/southbridge/amd/Kconfig trunk/coreboot-v2/src/southbridge/broadcom/Makefile.inc trunk/coreboot-v2/src/southbridge/intel/Kconfig trunk/coreboot-v2/src/southbridge/intel/Makefile.inc trunk/coreboot-v2/src/southbridge/intel/i82371eb/Makefile.inc trunk/coreboot-v2/src/southbridge/intel/i82801gx/Makefile.inc trunk/coreboot-v2/src/southbridge/intel/i82801xx/Makefile.inc trunk/coreboot-v2/src/southbridge/ricoh/Makefile.inc trunk/coreboot-v2/src/southbridge/sis/Makefile.inc trunk/coreboot-v2/src/southbridge/via/Kconfig trunk/coreboot-v2/src/southbridge/via/Makefile.inc trunk/coreboot-v2/src/southbridge/winbond/Makefile.inc Log: some progress on kconfig: - northbridges are done - southbridges are done - Intel CPUs are done, with a design that the board only has to specify the socket it has, and the CPUs are pulled in automatically. There is some more cleanup possible in that area, but I'll do that later - a couple more mainboards compile: - intel/eagleheights - intel/jarrell - intel/mtarvon - intel/truxton - intel/xe7501devkit - sunw/ultra40 - supermicro/h8dme - tyan/s2850 - tyan/s2875 - via/epia - via/epia-cn - via/epia-m - via/epia-m700 - via/epia-n - via/pc2500e (PPC not considered, probably overlooked something) All of them only _build_, but some options are probably completely wrong. To be fixed later Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/Makefile =================================================================== --- trunk/coreboot-v2/Makefile 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/Makefile 2009-09-25 18:43:02 UTC (rev 4673) @@ -145,6 +145,14 @@ $(eval $(call evaluate_subdirs)) +define c_dsl_template +$(obj)/$(1)%.c: src/$(1)%.dsl + @printf " IASL $$(subst $$(shell pwd)/,,$$(@))\n" + iasl -p $$(basename $$@) -tc $$< + perl -pi -e 's/AmlCode/AmlCode_$$(notdir $$(basename $$@))/g' $$(basename $$(a)).hex + mv $$(basename $$(a)).hex $$@ +endef + define objs_c_template $(obj)/$(1)%.o: src/$(1)%.c @printf " CC $$(subst $$(shell pwd)/,,$$(@))\n" @@ -195,6 +203,7 @@ usetemplate=$(foreach d,$(sort $(dir $($(1)))),$(eval $(call $(1)_$(2)_template,$(subst $(obj)/,,$(d))))) usetemplate=$(foreach d,$(sort $(dir $($(1)))),$(eval $(call $(1)_$(2)_template,$(subst $(obj)/,,$(d))))) +$(eval $(call usetemplate,c,dsl)) $(eval $(call usetemplate,objs,c)) $(eval $(call usetemplate,objs,S)) $(eval $(call usetemplate,initobjs,c)) @@ -233,7 +242,7 @@ CFLAGS = $(STACKPROTECT) $(INCLUDES) $(MAINBOARD_OPTIONS) -Os -nostdinc CFLAGS += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS +=-Wwrite-strings -Wredundant-decls -Wno-trigraphs -CFLAGS += -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow +CFLAGS += -Wstrict-aliasing -Wshadow CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CBFS_COMPRESS_FLAG:=l Modified: trunk/coreboot-v2/src/cpu/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/cpu/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -17,6 +17,10 @@ hex default 0x8000 if CPU_INTEL_CORE +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0 + config SMP bool default y if MAX_CPUS != 1 Modified: trunk/coreboot-v2/src/cpu/intel/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/cpu/intel/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -1,5 +1,15 @@ +source src/cpu/intel/model_69x/Kconfig +source src/cpu/intel/model_6dx/Kconfig source src/cpu/intel/model_6ex/Kconfig source src/cpu/intel/model_6fx/Kconfig +source src/cpu/intel/model_1067x/Kconfig + +source src/cpu/intel/bga956/Kconfig +source src/cpu/intel/ep80579/Kconfig +source src/cpu/intel/slot_2/Kconfig source src/cpu/intel/socket_mFCPGA478/Kconfig +source src/cpu/intel/socket_mPGA478/Kconfig +source src/cpu/intel/socket_mPGA479M/Kconfig +#source src/cpu/intel/socket_mPGA603/Kconfig +source src/cpu/intel/socket_mPGA604/Kconfig source src/cpu/intel/socket_PGA370/Kconfig -source src/cpu/intel/slot_2/Kconfig Modified: trunk/coreboot-v2/src/cpu/intel/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/cpu/intel/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -3,13 +3,15 @@ # # Therefore: ONLY include Makefile.inc from socket directories! +subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += bga956 +subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478) += socket_mPGA478 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA479M) += socket_mPGA479M +subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370 subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2 -#socket_mPGA478 -#socket_mPGA479M -#socket_mPGA603 -#socket_mPGA604 #socket_mPGA604_533Mhz #socket_mPGA604_800Mhz Added: trunk/coreboot-v2/src/cpu/intel/bga956/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/bga956/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/bga956/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,4 @@ +config CPU_INTEL_SOCKET_BGA956 + bool + default n + select CPU_INTEL_CORE2 Added: trunk/coreboot-v2/src/cpu/intel/bga956/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/bga956/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/bga956/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,13 @@ +obj-y += bga956.o +subdirs-y += ../model_1067x +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/fpu +subdirs-y += ../../x86/mmx +subdirs-y += ../../x86/sse +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading + Added: trunk/coreboot-v2/src/cpu/intel/ep80579/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/ep80579/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/ep80579/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +config CPU_INTEL_EP80579 + bool + default false Added: trunk/coreboot-v2/src/cpu/intel/ep80579/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/ep80579/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/ep80579/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,12 @@ +obj-y += ep80579.o +driver-y += ep80579_init.o +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/fpu +subdirs-y += ../../x86/mmx +subdirs-y += ../../x86/sse +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode + Added: trunk/coreboot-v2/src/cpu/intel/model_1067x/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_1067x/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_1067x/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,5 @@ +config CPU_INTEL_CORE2 + bool + default y + select SMP + select HAVE_MOVNTI Added: trunk/coreboot-v2/src/cpu/intel/model_1067x/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_1067x/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_1067x/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1 @@ +driver-y += model_1067x_init.o Added: trunk/coreboot-v2/src/cpu/intel/model_69x/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_69x/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_69x/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,4 @@ +config CPU_INTEL_MODEL_69X + bool + default n + select SMP Added: trunk/coreboot-v2/src/cpu/intel/model_6dx/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6dx/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6dx/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,4 @@ +config CPU_INTEL_MODEL_6DX + bool + default n + select SMP Added: trunk/coreboot-v2/src/cpu/intel/model_6xx/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6xx/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6xx/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,4 @@ +config CPU_INTEL_MODEL_6XX + bool + default n + select SMP Modified: trunk/coreboot-v2/src/cpu/intel/model_6xx/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6xx/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/cpu/intel/model_6xx/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -1,22 +1 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ron Minnich <rminnich(a)gmail.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - driver-y += model_6xx_init.o - Added: trunk/coreboot-v2/src/cpu/intel/model_f0x/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f0x/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_f0x/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,5 @@ +config CPU_INTEL_MODEL_F0X + bool + default n + select SMP + select HAVE_MOVNTI Added: trunk/coreboot-v2/src/cpu/intel/model_f0x/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f0x/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_f0x/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1 @@ +driver-y += model_f0x_init.o Added: trunk/coreboot-v2/src/cpu/intel/model_f1x/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f1x/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_f1x/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,5 @@ +config CPU_INTEL_MODEL_F1X + bool + default n + select SMP + select HAVE_MOVNTI Added: trunk/coreboot-v2/src/cpu/intel/model_f1x/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f1x/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_f1x/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1 @@ +driver-y += model_f1x_init.o Added: trunk/coreboot-v2/src/cpu/intel/model_f2x/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f2x/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_f2x/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,5 @@ +config CPU_INTEL_MODEL_F2X + bool + default n + select SMP + select HAVE_MOVNTI Added: trunk/coreboot-v2/src/cpu/intel/model_f2x/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f2x/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_f2x/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1 @@ +driver-y += model_f2x_init.o Added: trunk/coreboot-v2/src/cpu/intel/model_f3x/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f3x/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_f3x/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,5 @@ +config CPU_INTEL_MODEL_F3X + bool + default n + select SMP + select HAVE_MOVNTI Added: trunk/coreboot-v2/src/cpu/intel/model_f3x/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f3x/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_f3x/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1 @@ +driver-y += model_f3x_init.o Added: trunk/coreboot-v2/src/cpu/intel/model_f4x/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f4x/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_f4x/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,5 @@ +config CPU_INTEL_MODEL_F4X + bool + default n + select SMP + select HAVE_MOVNTI Added: trunk/coreboot-v2/src/cpu/intel/model_f4x/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f4x/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_f4x/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1 @@ +driver-y += model_f4x_init.o Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,5 @@ +config CPU_INTEL_SOCKET_MPGA478 + bool + default false + select CPU_INTEL_MODEL_69X + select CPU_INTEL_MODEL_6DX Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,14 @@ +obj-y += socket_mPGA478.o +subdirs-y += ../model_69x +subdirs-y += ../model_6dx +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/fpu +subdirs-y += ../../x86/mmx +subdirs-y += ../../x86/sse +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading + Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,5 @@ +config CPU_INTEL_SOCKET_MPGA479M + bool + default false + select CPU_INTEL_MODEL_69X + select CPU_INTEL_MODEL_6DX Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,14 @@ +obj-y += socket_mPGA479M.o +subdirs-y += ../model_69x +subdirs-y += ../model_6dx +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/fpu +subdirs-y += ../../x86/mmx +subdirs-y += ../../x86/sse +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading + Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA603/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA603/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA603/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,6 @@ +config CPU_INTEL_SOCKET_MPGA603 + bool + default false + select CPU_INTEL_MODEL_F0X + select CPU_INTEL_MODEL_F1X + select CPU_INTEL_MODEL_F2X Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA603/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA603/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA603/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,15 @@ +obj-y += socket_mPGA603_400Mhz.o +subdirs-y += ../model_f0x +subdirs-y += ../model_f1x +subdirs-y += ../model_f2x +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/fpu +subdirs-y += ../../x86/mmx +subdirs-y += ../../x86/sse +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading + Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,6 @@ +config CPU_INTEL_SOCKET_MPGA604 + bool + default false + select CPU_INTEL_MODEL_F2X + select CPU_INTEL_MODEL_F3X + select CPU_INTEL_MODEL_F4X Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,15 @@ +obj-y += socket_mPGA604.o +subdirs-y += ../model_f2x +subdirs-y += ../model_f3x +subdirs-y += ../model_f4x +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/fpu +subdirs-y += ../../x86/mmx +subdirs-y += ../../x86/sse +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading + Modified: trunk/coreboot-v2/src/cpu/x86/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/x86/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/cpu/x86/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -2,6 +2,10 @@ bool default y +config WAIT_BEFORE_CPUS_INIT + bool + default n + config UDELAY_TSC bool default n Modified: trunk/coreboot-v2/src/mainboard/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/mainboard/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -441,5 +441,14 @@ help Map the config names to an integer. +config ROM_SIZE + hex + default 0x20000 if COREBOOT_ROMSIZE_KB_128 + default 0x40000 if COREBOOT_ROMSIZE_KB_256 + default 0x80000 if COREBOOT_ROMSIZE_KB_512 + default 0x100000 if COREBOOT_ROMSIZE_KB_1024 + default 0x200000 if COREBOOT_ROMSIZE_KB_2048 + default 0x400000 if COREBOOT_ROMSIZE_KB_4096 + endmenu Modified: trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -44,15 +44,17 @@ ifdef POST_EVALUATION +ROMCCFLAGS ?= -mcpu=p2 + $(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c - $(obj)/romcc -mcpu=p2 -O2 --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@ + $(obj)/romcc -mcpu=$(ROMCCFLAGS) -O2 --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@ ifeq ($(CONFIG_HAVE_OPTION_TABLE),y) $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h - $(obj)/romcc -mcpu=p2 -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + $(obj)/romcc -mcpu=$(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ else $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c - $(obj)/romcc -mcpu=p2 -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + $(obj)/romcc -mcpu=$(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ endif endif Modified: trunk/coreboot-v2/src/mainboard/intel/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/mainboard/intel/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -1 +1,12 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_INTEL + +source "src/mainboard/intel/eagleheights/Kconfig" +source "src/mainboard/intel/jarrell/Kconfig" +source "src/mainboard/intel/mtarvon/Kconfig" +source "src/mainboard/intel/truxton/Kconfig" +source "src/mainboard/intel/xe7501devkit/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/intel/eagleheights/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/eagleheights/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,48 @@ +config BOARD_INTEL_EAGLEHEIGHTS + bool "EagleHeights" + select ARCH_X86 + select CPU_INTEL_SOCKET_BGA956 + select NORTHBRIDGE_INTEL_I3100 + select SOUTHBRIDGE_INTEL_I3100 + select SUPERIO_INTEL_I3100 + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select HAVE_HIGH_TABLES + select MMCONF_SUPPORT + select USE_PRINTK_IN_CAR + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + select AP_IN_SIPI_WAIT + help + Intel EagleHeights mainboard. + +config MAINBOARD_DIR + string + default intel/eagleheights + depends on BOARD_INTEL_EAGLEHEIGHTS + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + depends on BOARD_INTEL_EAGLEHEIGHTS + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_INTEL_EAGLEHEIGHTS + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_INTEL_EAGLEHEIGHTS + +config LB_CKS_LOC + int + default 123 + depends on BOARD_INTEL_EAGLEHEIGHTS + +config MAINBOARD_PART_NUMBER + string + default "EagleHeights" + depends on BOARD_INTEL_EAGLEHEIGHTS + Added: trunk/coreboot-v2/src/mainboard/intel/eagleheights/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/eagleheights/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,38 @@ +driver-y += mainboard.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-y += reset.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/intel/model_6ex/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS=\ + -DCONFIG_MMCONF_SUPPORT=1 \ + -DCONFIG_MMCONF_BASE_ADDRESS=0xe0000000 + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/intel/eagleheights/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/eagleheights/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/devicetree.cb 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,73 @@ +chip northbridge/intel/i3100 + device pci_domain 0 on + device pci 00.0 on end # IMCH + device pci 00.1 on end # IMCH error status + device pci 01.0 on end # IMCH EDMA engine + device pci 02.0 on end # PCIe port A/A0 + device pci 03.0 on end # PCIe port A1 + chip southbridge/intel/i3100 + # PIRQ line -> legacy IRQ mappings + register "pirq_a_d" = "0x8b808a8a" + register "pirq_e_h" = "0x85808080" + + device pci 1c.0 on end # PCIe port B0 + device pci 1c.1 off end # PCIe port B1 + device pci 1c.2 off end # PCIe port B2 + device pci 1c.3 off end # PCIe port B3 + device pci 1d.0 on end # USB (UHCI) 1 + device pci 1d.1 on end # USB (UHCI) 2 + device pci 1d.7 on end # USB (EHCI) + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/intel/i3100 + device pnp 4e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + chip superio/smsc/smscsuperio + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.2 off # Serial Port 4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 2 + end + device pnp 2e.4 off # Serial Port 3 + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.7 on # PS/2 Keyboard / Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 2e.a off # Runtime registers + io 0x60 = 0x600 + end + end + end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + device pci 1f.4 on end # Performance counters + end + end + device apic_cluster 0 on + chip cpu/intel/bga956 + device apic 0 on end + end + end +end + Added: trunk/coreboot-v2/src/mainboard/intel/jarrell/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,33 @@ +config BOARD_INTEL_JARRELL + bool "Jarrell" + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA604 + select NORTHBRIDGE_INTEL_E7520 + select SOUTHBRIDGE_INTEL_PXHD + select SOUTHBRIDGE_INTEL_I82801ER + select SUPERIO_NSC_PC87427 + select HAVE_PIRQ_TABLE + select UDELAY_TSC + help + Intel Jarrell mainboard. + +config MAINBOARD_DIR + string + default intel/jarrell + depends on BOARD_INTEL_JARRELL + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_INTEL_JARRELL + +config LB_CKS_LOC + int + default 123 + depends on BOARD_INTEL_JARRELL + +config MAINBOARD_PART_NUMBER + string + default "Jarrell" + depends on BOARD_INTEL_JARRELL + Added: trunk/coreboot-v2/src/mainboard/intel/jarrell/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,4 @@ +obj-y += reset.o +ROMCCFLAGS := -mcpu=p4 +include $(src)/mainboard/Makefile.romccboard.inc + Added: trunk/coreboot-v2/src/mainboard/intel/mtarvon/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/mtarvon/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,41 @@ +config BOARD_INTEL_MTARVON + bool "Mt. Arvon" + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA479M + select NORTHBRIDGE_INTEL_I3100 + select SOUTHBRIDGE_INTEL_I3100 + select SUPERIO_INTEL_I3100 + select HAVE_PIRQ_TABLE + select UDELAY_TSC + help + Intel Mt. Arvon mainboard. + +config MAINBOARD_DIR + string + default intel/mtarvon + depends on BOARD_INTEL_MTARVON + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_INTEL_MTARVON + +config LB_CKS_LOC + int + default 123 + depends on BOARD_INTEL_MTARVON + +config MAINBOARD_PART_NUMBER + string + default "Mt. Arvon" + depends on BOARD_INTEL_MTARVON + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_INTEL_MTARVON + +config IRQ_SLOT_COUNT + int + default 1 + depends on BOARD_INTEL_MTARVON Added: trunk/coreboot-v2/src/mainboard/intel/mtarvon/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/mtarvon/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +ROMCCFLAGS := -mcpu=p4 +include $(src)/mainboard/Makefile.romccboard.inc + Added: trunk/coreboot-v2/src/mainboard/intel/truxton/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/truxton/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/intel/truxton/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,43 @@ +config BOARD_INTEL_TRUXTON + bool "Truxton" + select ARCH_X86 + select CPU_INTEL_EP80579 + select NORTHBRIDGE_INTEL_I3100 + select SOUTHBRIDGE_INTEL_I3100 + select SUPERIO_INTEL_I3100 + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select UDELAY_TSC + help + Intel Truxton mainboard. + +config MAINBOARD_DIR + string + default intel/truxton + depends on BOARD_INTEL_TRUXTON + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_INTEL_TRUXTON + +config LB_CKS_LOC + int + default 123 + depends on BOARD_INTEL_TRUXTON + +config MAINBOARD_PART_NUMBER + string + default "Truxton" + depends on BOARD_INTEL_TRUXTON + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_INTEL_TRUXTON + +config IRQ_SLOT_COUNT + int + default 1 + depends on BOARD_INTEL_TRUXTON + Added: trunk/coreboot-v2/src/mainboard/intel/truxton/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/truxton/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/intel/truxton/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi +include $(src)/mainboard/Makefile.romccboard.inc + Added: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,47 @@ +config BOARD_INTEL_XE7501DEVKIT + bool "xe7501 DevKit" + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA604 + select NORTHBRIDGE_INTEL_E7501 + select SOUTHBRIDGE_INTEL_I82870 + select SOUTHBRIDGE_INTEL_I82801CA + select SUPERIO_SMSC_LPC47B272 + select HAVE_PIRQ_TABLE + select UDELAY_TSC + help + Intel xe7501 devkit mainboard. + +config MAINBOARD_DIR + string + default intel/xe7501devkit + depends on BOARD_INTEL_XE7501DEVKIT + +config LB_CKS_RANGE_START + int + default 128 + depends on BOARD_INTEL_XE7501DEVKIT + +config LB_CKS_RANGE_END + int + default 130 + depends on BOARD_INTEL_XE7501DEVKIT + +config LB_CKS_LOC + int + default 131 + depends on BOARD_INTEL_XE7501DEVKIT + +config MAINBOARD_PART_NUMBER + string + default "EIDXE7501DEVKIT" + depends on BOARD_INTEL_XE7501DEVKIT + +config HAVE_OPTION_TABLE + bool + default y + depends on BOARD_INTEL_XE7501DEVKIT + +config IRQ_SLOT_COUNT + int + default 12 + depends on BOARD_INTEL_XE7501DEVKIT Added: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,13 @@ +ROMCCFLAGS := -mcpu=p4 +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o +ifeq ($(CONFIG_PCI_ROM_RUN),y) + ifeq ($(CONFIG_PCI_ROM_RUN),y) + obj-y += vgarom.o + else + obj-y += no_vgarom.o + endif +else + obj-y += no_vgarom.o +endif +include $(src)/mainboard/Makefile.romccboard.inc + Modified: trunk/coreboot-v2/src/mainboard/sunw/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/mainboard/sunw/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -1 +1,8 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_SUNW + +source "src/mainboard/sunw/ultra40/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,130 @@ +config BOARD_SUNW_ULTRA40 + bool "Ultra40" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_CK804 + select SUPERIO_SMSC_LPC47M10X + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + help + Sun Ultra40. + +config MAINBOARD_DIR + string + default sunw/ultra40 + depends on BOARD_SUNW_ULTRA40 + +config DCACHE_RAM_BASE + hex + default 0xcf000 + depends on BOARD_SUNW_ULTRA40 + +config DCACHE_RAM_SIZE + hex + default 0x01000 + depends on BOARD_SUNW_ULTRA40 + +config APIC_ID_OFFSET + hex + default 0x10 + depends on BOARD_SUNW_ULTRA40 + +config HAVE_HARD_RESET + bool + default y + depends on BOARD_SUNW_ULTRA40 + +config IOAPIC + bool + default y + depends on BOARD_SUNW_ULTRA40 + +config K8_REV_F_SUPPORT + bool + default n + depends on BOARD_SUNW_ULTRA40 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_SUNW_ULTRA40 + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_SUNW_ULTRA40 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_SUNW_ULTRA40 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_SUNW_ULTRA40 + +config MAINBOARD_PART_NUMBER + string + default "ultra40" + depends on BOARD_SUNW_ULTRA40 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_SUNW_ULTRA40 + +config HAVE_FAILOVER_BOOT + bool + default n + depends on BOARD_SUNW_ULTRA40 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_SUNW_ULTRA40 + +config MAX_CPUS + int + default 4 + depends on BOARD_SUNW_ULTRA40 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_SUNW_ULTRA40 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_SUNW_ULTRA40 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_SUNW_ULTRA40 + +config USE_INIT + bool + default n + depends on BOARD_SUNW_ULTRA40 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_SUNW_ULTRA40 + +config CONSOLE_VGA + bool + default y + depends on BOARD_SUNW_ULTRA40 + +config PCI_ROM_RUN + bool + default y + depends on BOARD_SUNW_ULTRA40 + Added: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,81 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS=\ + -DCONFIG_AP_IN_SIPI_WAIT=0 \ + -DCONFIG_USE_PRINTK_IN_CAR=1 \ + -DCONFIG_HAVE_HIGH_TABLES=1 + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl + iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex + mv pci2.hex ssdt2.c + +$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl" + iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/ + perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex + mv pci3.hex ssdt3.c + +$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl" + iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex + mv pci4.hex ssdt4.c + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/mainboard/supermicro/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/mainboard/supermicro/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -1 +1,14 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_SUPERMICRO + +source "src/mainboard/supermicro/h8dme/Kconfig" +#source "src/mainboard/supermicro/h8dmr/Kconfig" +#source "src/mainboard/supermicro/x6dai_g/Kconfig" +#source "src/mainboard/supermicro/x6dhe_g/Kconfig" +#source "src/mainboard/supermicro/x6dhe_g2/Kconfig" +#source "src/mainboard/supermicro/x6dhr_ig/Kconfig" +#source "src/mainboard/supermicro/x6dhr_ig2/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,130 @@ +config BOARD_SUPERMICRO_H8DME + bool "h8dme" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_F + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_MCP55 + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + help + h8dme + +config MAINBOARD_DIR + string + default supermicro/h8dme + depends on BOARD_SUPERMICRO_H8DME + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_SUPERMICRO_H8DME + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_SUPERMICRO_H8DME + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_SUPERMICRO_H8DME + +config APIC_ID_OFFSET + hex + default 0x10 + depends on BOARD_SUPERMICRO_H8DME + +config HAVE_HARD_RESET + bool + default y + depends on BOARD_SUPERMICRO_H8DME + +config IOAPIC + bool + default y + depends on BOARD_SUPERMICRO_H8DME + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_SUPERMICRO_H8DME + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_SUPERMICRO_H8DME + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_SUPERMICRO_H8DME + +config LB_CKS_LOC + int + default 123 + depends on BOARD_SUPERMICRO_H8DME + +config MAINBOARD_PART_NUMBER + string + default "ultra40" + depends on BOARD_SUPERMICRO_H8DME + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_SUPERMICRO_H8DME + +config HAVE_FAILOVER_BOOT + bool + default n + depends on BOARD_SUPERMICRO_H8DME + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_SUPERMICRO_H8DME + +config MAX_CPUS + int + default 4 + depends on BOARD_SUPERMICRO_H8DME + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_SUPERMICRO_H8DME + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_SUPERMICRO_H8DME + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_SUPERMICRO_H8DME + +config USE_INIT + bool + default n + depends on BOARD_SUPERMICRO_H8DME + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_SUPERMICRO_H8DME + +config CONSOLE_VGA + bool + default y + depends on BOARD_SUPERMICRO_H8DME + +config PCI_ROM_RUN + bool + default y + depends on BOARD_SUPERMICRO_H8DME + Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,82 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o +driver-y += ../../../drivers/i2c/i2cmux2/i2cmux2.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS=\ + -DCONFIG_AP_IN_SIPI_WAIT=0 \ + -DCONFIG_USE_PRINTK_IN_CAR=1 \ + -DCONFIG_HAVE_HIGH_TABLES=1 + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl + iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex + mv pci2.hex ssdt2.c + +$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl" + iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/ + perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex + mv pci3.hex ssdt3.c + +$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl" + iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex + mv pci4.hex ssdt4.c + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/tyan/s2850/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,65 @@ +config BOARD_TYAN_S2850 + bool "Tyan S2850" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_AMD8111 + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + +config MAINBOARD_DIR + string + default tyan/s2850 + depends on BOARD_TYAN_S2850 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_TYAN_S2850 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_TYAN_S2850 + +config MAINBOARD_PART_NUMBER + string + default "s2850" + depends on BOARD_TYAN_S2850 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2850 + depends on BOARD_TYAN_S2850 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_TYAN_S2850 + +config HAVE_FAILOVER_BOOT + bool + default n + depends on BOARD_TYAN_S2850 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_TYAN_S2850 + +config MAX_CPUS + int + default 2 + depends on BOARD_TYAN_S2850 + +config MAX_PHYSICAL_CPUS + int + default 1 + depends on BOARD_TYAN_S2850 + +config USE_INIT + bool + default n + depends on BOARD_TYAN_S2850 Added: trunk/coreboot-v2/src/mainboard/tyan/s2850/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1 @@ +include $(src)/mainboard/tyan/Makefile.s289x.inc Added: trunk/coreboot-v2/src/mainboard/tyan/s2875/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,71 @@ +config BOARD_TYAN_S2875 + bool "Tyan S2875" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_AMD8151 + select SOUTHBRIDGE_AMD_AMD8111 + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + +config MAINBOARD_DIR + string + default tyan/s2875 + depends on BOARD_TYAN_S2875 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_TYAN_S2875 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_TYAN_S2875 + +config MAINBOARD_PART_NUMBER + string + default "s2875" + depends on BOARD_TYAN_S2875 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2875 + depends on BOARD_TYAN_S2875 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_TYAN_S2875 + +config HAVE_FAILOVER_BOOT + bool + default n + depends on BOARD_TYAN_S2875 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_TYAN_S2875 + +config MAX_CPUS + int + default 4 + depends on BOARD_TYAN_S2875 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_TYAN_S2875 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_TYAN_S2875 + +config USE_INIT + bool + default n + depends on BOARD_TYAN_S2875 Added: trunk/coreboot-v2/src/mainboard/tyan/s2875/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1 @@ +include $(src)/mainboard/tyan/Makefile.s289x.inc Modified: trunk/coreboot-v2/src/mainboard/via/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/via/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/mainboard/via/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -2,8 +2,13 @@ prompt "Mainboard model" depends on VENDOR_VIA +source "src/mainboard/via/epia/Kconfig" +source "src/mainboard/via/epia-cn/Kconfig" +source "src/mainboard/via/epia-m/Kconfig" +source "src/mainboard/via/epia-m700/Kconfig" +source "src/mainboard/via/epia-n/Kconfig" +source "src/mainboard/via/pc2500e/Kconfig" source "src/mainboard/via/vt8454c/Kconfig" -source "src/mainboard/via/epia-n/Kconfig" endchoice Added: trunk/coreboot-v2/src/mainboard/via/epia/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,35 @@ +config BOARD_VIA_EPIA + bool "EPIA" + select ARCH_X86 + select CPU_VIA_C3 + select NORTHBRIDGE_VIA_VT8601 + select SOUTHBRIDGE_VIA_VT8231 + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + help + VIA EPIA mainboard. + +config MAINBOARD_DIR + string + default via/epia + depends on BOARD_VIA_EPIA + +#config DCACHE_RAM_BASE +# hex +# default 0xffef0000 +# depends on BOARD_VIA_EPIA +# +#config DCACHE_RAM_SIZE +# hex +# default 0x8000 +# depends on BOARD_VIA_EPIA + +config MAINBOARD_PART_NUMBER + string + default "EPIA" + depends on BOARD_VIA_EPIA + +config RAMBASE + hex + default 0x4000 + depends on BOARD_VIA_EPIA Added: trunk/coreboot-v2/src/mainboard/via/epia/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,58 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 VIA Technologies, Inc. +## (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +initobj-y += crt0.o +obj-y += mainboard.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc +crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc +crt0-y += auto.inc +crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS= + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/mainboard/via/epia/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia/auto.c 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/mainboard/via/epia/auto.c 2009-09-25 18:43:02 UTC (rev 4673) @@ -16,7 +16,7 @@ /* */ -void udelay(int usecs) +void udelay(unsigned usecs) { int i; for (i = 0; i < usecs; i++) Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,45 @@ +config BOARD_VIA_EPIA_CN + bool "EPIA-CN" + select ARCH_X86 + select CPU_VIA_C7 + select NORTHBRIDGE_VIA_CN700 + select SOUTHBRIDGE_VIA_VT8237R + select SUPERIO_VIA_VT1211 + select HAVE_PIRQ_TABLE + help + VIA EPIA-CN mainboard. + +config MAINBOARD_DIR + string + default via/epia-cn + depends on BOARD_VIA_EPIA_CN + +#config DCACHE_RAM_BASE +# hex +# default 0xffef0000 +# depends on BOARD_VIA_EPIA_CN +# +#config DCACHE_RAM_SIZE +# hex +# default 0x8000 +# depends on BOARD_VIA_EPIA_CN + +config MAINBOARD_PART_NUMBER + string + default "EPIA_CN" + depends on BOARD_VIA_EPIA_CN + +config VIDEO_MB + int + default 32 + depends on BOARD_VIA_EPIA_CN + +config RAMBASE + hex + default 0x4000 + depends on BOARD_VIA_EPIA_CN + +config IRQ_SLOT_COUNT + int + default 9 + depends on BOARD_VIA_EPIA_CN Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,63 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 VIA Technologies, Inc. +## (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +initobj-y += crt0.o +obj-y += mainboard.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o + +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc +crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc +crt0-y += auto.inc +crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS= + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/via/epia-m/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,41 @@ +config BOARD_VIA_EPIA_M + bool "EPIA-M" + select ARCH_X86 + select CPU_VIA_C3 + select NORTHBRIDGE_VIA_VT8623 + select SOUTHBRIDGE_VIA_VT8235 + select SOUTHBRIDGE_RICOH_RL5C476 + select SUPERIO_VIA_VT1211 + select HAVE_PIRQ_TABLE + help + VIA EPIA-M mainboard. + +config MAINBOARD_DIR + string + default via/epia-m + depends on BOARD_VIA_EPIA_M + +#config DCACHE_RAM_BASE +# hex +# default 0xffef0000 +# depends on BOARD_VIA_EPIA_M + +#config DCACHE_RAM_SIZE +# hex +# default 0x8000 +# depends on BOARD_VIA_EPIA_M + +config MAINBOARD_PART_NUMBER + string + default "EPIA_M" + depends on BOARD_VIA_EPIA_M + +config RAMBASE + hex + default 0x4000 + depends on BOARD_VIA_EPIA_M + +config IRQ_SLOT_COUNT + int + default 5 + depends on BOARD_VIA_EPIA_M Added: trunk/coreboot-v2/src/mainboard/via/epia-m/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,65 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 VIA Technologies, Inc. +## (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +initobj-y += crt0.o +obj-y += mainboard.o +obj-y += vgabios.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/northbridge/via/vx800/romstrap.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/northbridge/via/vx800/romstrap.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc +crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc +crt0-y += auto.inc +crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS= + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/auto.c 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/auto.c 2009-09-25 18:43:02 UTC (rev 4673) @@ -20,7 +20,7 @@ /* */ -void udelay(int usecs) +void udelay(unsigned usecs) { int i; for(i = 0; i < usecs; i++) Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,44 @@ +config BOARD_VIA_EPIA_M700 + bool "EPIA-M700" + select ARCH_X86 + select CPU_VIA_C7 + select NORTHBRIDGE_VIA_VX800 + select SUPERIO_WINBOND_W83697HF + select HAVE_PIRQ_TABLE + help + VIA EPIA-M700 mainboard. + +config MAINBOARD_DIR + string + default via/epia-m700 + depends on BOARD_VIA_EPIA_M700 + +config DCACHE_RAM_BASE + hex + default 0xffef0000 + depends on BOARD_VIA_EPIA_M700 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_VIA_EPIA_M700 + +config MAINBOARD_PART_NUMBER + string + default "EPIA_M700" + depends on BOARD_VIA_EPIA_M700 + +config VIDEO_MB + int + default 64 + depends on BOARD_VIA_EPIA_M700 + +config RAMBASE + hex + default 0x4000 + depends on BOARD_VIA_EPIA_M700 + +config IRQ_SLOT_COUNT + int + default 13 + depends on BOARD_VIA_EPIA_M700 Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,64 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 VIA Technologies, Inc. +## (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +initobj-y += crt0.o +obj-y += mainboard.o +obj-y += wakeup.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o + +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/northbridge/via/vx800/romstrap.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/northbridge/via/vx800/romstrap.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/via/car/cache_as_ram.inc +crt0-y += cache_as_ram_auto.inc + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS= + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/mainboard/via/epia-n/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-n/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/mainboard/via/epia-n/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -6,7 +6,6 @@ select SOUTHBRIDGE_VIA_VT8237R select SUPERIO_WINBOND_W83697HF select HAVE_PIRQ_TABLE - select USE_PRINTK_IN_CAR help VIA EPIA-N mainboard. Modified: trunk/coreboot-v2/src/mainboard/via/epia-n/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-n/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/mainboard/via/epia-n/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -44,9 +44,7 @@ ifdef POST_EVALUATION -MAINBOARD_OPTIONS=\ - -DCONFIG_USE_PRINTK_IN_CAR=1 \ - -DCONFIG_HAVE_HIGH_TABLES=1 +MAINBOARD_OPTIONS= $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ Added: trunk/coreboot-v2/src/mainboard/via/pc2500e/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/via/pc2500e/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/pc2500e/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,45 @@ +config BOARD_VIA_PC2500E + bool "PC2500E" + select ARCH_X86 + select CPU_VIA_C7 + select NORTHBRIDGE_VIA_CN700 + select SOUTHBRIDGE_VIA_VT8237R + select SUPERIO_ITE_IT8716F + select HAVE_PIRQ_TABLE + help + VIA PC2500E mainboard. + +config MAINBOARD_DIR + string + default via/pc2500e + depends on BOARD_VIA_PC2500E + +#config DCACHE_RAM_BASE +# hex +# default 0xffef0000 +# depends on BOARD_VIA_PC2500E +# +#config DCACHE_RAM_SIZE +# hex +# default 0x8000 +# depends on BOARD_VIA_PC2500E + +config MAINBOARD_PART_NUMBER + string + default "PC2500E" + depends on BOARD_VIA_PC2500E + +config VIDEO_MB + int + default 32 + depends on BOARD_VIA_PC2500E + +config RAMBASE + hex + default 0x4000 + depends on BOARD_VIA_PC2500E + +config IRQ_SLOT_COUNT + int + default 10 + depends on BOARD_VIA_PC2500E Added: trunk/coreboot-v2/src/mainboard/via/pc2500e/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/via/pc2500e/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/pc2500e/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,63 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 VIA Technologies, Inc. +## (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +initobj-y += crt0.o +obj-y += mainboard.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o + +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc +crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc +crt0-y += auto.inc +crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS= + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/northbridge/amd/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/northbridge/amd/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -1,8 +1,5 @@ source src/northbridge/amd/amdk8/Kconfig source src/northbridge/amd/gx2/Kconfig - -#source src/northbridge/amd/amdfam10/Kconfig -#source src/northbridge/amd/amdht/Kconfig -#source src/northbridge/amd/amdmct/Kconfig +source src/northbridge/amd/amdfam10/Kconfig #source src/northbridge/amd/gx1/Kconfig #source src/northbridge/amd/lx/Kconfig Modified: trunk/coreboot-v2/src/northbridge/amd/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/northbridge/amd/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -1,7 +1,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) += amdfam10 -subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDHT) += amdht subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8 -subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDMCT) += amdmct subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX1) += gx1 subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx Added: trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,34 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2009 coresystems GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config NORTHBRIDGE_AMD_AMDFAM10 + bool + default n + +config AGP_APERTURE_SIZE + hex + default 0x4000000 + depends on NORTHBRIDGE_AMD_AMDFAM10 + +config HAVE_HIGH_TABLES + bool + default y + depends on NORTHBRIDGE_AMD_AMDFAM10 + +source src/northbridge/amd/amdfam10/root_complex/Kconfig Added: trunk/coreboot-v2/src/northbridge/amd/amdfam10/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,12 @@ +driver-y += northbridge.o +driver-y += misc_control.o + +obj-$(CONFIG_HAVE_ACPI_TABLES) += amdfam10_acpi.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += ssdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += sspr1.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += sspr2.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += sspr3.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += sspr4.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += sspr5.o + +obj-y += get_pci1234.o Added: trunk/coreboot-v2/src/northbridge/amd/amdfam10/root_complex/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/root_complex/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/root_complex/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,4 @@ +config NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX + bool + default n + Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -24,10 +24,12 @@ config AGP_APERTURE_SIZE hex default 0x4000000 + depends on NORTHBRIDGE_AMD_AMDK8 config HAVE_HIGH_TABLES bool default y + depends on NORTHBRIDGE_AMD_AMDK8 config HYPERTRANSPORT_PLUGIN_SUPPORT bool Modified: trunk/coreboot-v2/src/northbridge/intel/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/northbridge/intel/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -1,10 +1,10 @@ -#source src/northbridge/intel/e7501/Kconfig -#source src/northbridge/intel/e7520/Kconfig -#source src/northbridge/intel/e7525/Kconfig -#source src/northbridge/intel/i3100/Kconfig +source src/northbridge/intel/e7501/Kconfig +source src/northbridge/intel/e7520/Kconfig +source src/northbridge/intel/e7525/Kconfig +source src/northbridge/intel/i3100/Kconfig source src/northbridge/intel/i440bx/Kconfig source src/northbridge/intel/i82810/Kconfig -#source src/northbridge/intel/i82830/Kconfig -#source src/northbridge/intel/i855gme/Kconfig -#source src/northbridge/intel/i855pm/Kconfig +source src/northbridge/intel/i82830/Kconfig +source src/northbridge/intel/i855gme/Kconfig +source src/northbridge/intel/i855pm/Kconfig source src/northbridge/intel/i945/Kconfig Modified: trunk/coreboot-v2/src/northbridge/intel/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/northbridge/intel/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -1,10 +1,10 @@ -#subdirs-y += e7501 -#subdirs-y += e7520 -#subdirs-y += e7525 -#subdirs-y += i3100 -subdirs-y += i440bx -subdirs-y += i82810 -#subdirs-y += i82830 -#subdirs-y += i855gme -#subdirs-y += i855pm -subdirs-y += i945 +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7501) += e7501 +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7520) += e7520 +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7525) += e7525 +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I3100) += i3100 +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I440BX) += i440bx +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82810) += i82810 +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82830) += i82830 +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855GME) += i855gme +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855PM) += i855pm +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945) += i945 Added: trunk/coreboot-v2/src/northbridge/intel/e7501/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7501/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/e7501/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,8 @@ +config NORTHBRIDGE_INTEL_E7501 + bool + default n + +config HAVE_HIGH_TABLES + bool + default y + depends on NORTHBRIDGE_INTEL_E7501 Added: trunk/coreboot-v2/src/northbridge/intel/e7501/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7501/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/e7501/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1 @@ +obj-y += northbridge.o Added: trunk/coreboot-v2/src/northbridge/intel/e7520/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7520/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/e7520/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,8 @@ +config NORTHBRIDGE_INTEL_E7520 + bool + default n + +config HAVE_HIGH_TABLES + bool + default y + depends on NORTHBRIDGE_INTEL_E7520 Added: trunk/coreboot-v2/src/northbridge/intel/e7520/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7520/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/e7520/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,5 @@ +driver-y += northbridge.o +driver-y += pciexp_porta.o +driver-y += pciexp_porta1.o +driver-y += pciexp_portb.o +driver-y += pciexp_portc.o Added: trunk/coreboot-v2/src/northbridge/intel/e7525/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7525/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/e7525/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,8 @@ +config NORTHBRIDGE_INTEL_E7525 + bool + default n + +config HAVE_HIGH_TABLES + bool + default y + depends on NORTHBRIDGE_INTEL_E7525 Added: trunk/coreboot-v2/src/northbridge/intel/e7525/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7525/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/e7525/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,5 @@ +driver-y += northbridge.o +driver-y += pciexp_porta.o +driver-y += pciexp_porta1.o +driver-y += pciexp_portb.o +driver-y += pciexp_portc.o Added: trunk/coreboot-v2/src/northbridge/intel/i3100/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i3100/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i3100/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,8 @@ +config NORTHBRIDGE_INTEL_I3100 + bool + default n + +config HAVE_HIGH_TABLES + bool + default y + depends on NORTHBRIDGE_INTEL_I3100 Added: trunk/coreboot-v2/src/northbridge/intel/i3100/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i3100/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i3100/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +driver-y += northbridge.o +driver-y += pciexp_porta.o +driver-y += pciexp_porta_ep80579.o Modified: trunk/coreboot-v2/src/northbridge/intel/i440bx/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i440bx/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/northbridge/intel/i440bx/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -22,3 +22,7 @@ bool default n +config HAVE_HIGH_TABLES + bool + default y + Modified: trunk/coreboot-v2/src/northbridge/intel/i440bx/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i440bx/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/northbridge/intel/i440bx/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-$(CONFIG_NORTHBRIDGE_INTEL_I440BX) += northbridge.o +driver-y += northbridge.o Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -21,3 +21,9 @@ config NORTHBRIDGE_INTEL_I82810 bool default n + +config HAVE_HIGH_TABLES + bool + default y + depends on NORTHBRIDGE_INTEL_I82810 + Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-$(CONFIG_NORTHBRIDGE_INTEL_I82810) += northbridge.o +driver-y += northbridge.o Added: trunk/coreboot-v2/src/northbridge/intel/i82830/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82830/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i82830/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,8 @@ +config NORTHBRIDGE_INTEL_I82830 + bool + default n + +config HAVE_HIGH_TABLES + bool + default y + depends on NORTHBRIDGE_INTEL_I82830 Added: trunk/coreboot-v2/src/northbridge/intel/i82830/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82830/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i82830/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,2 @@ +driver-y += northbridge.o +driver-y += vga.o Added: trunk/coreboot-v2/src/northbridge/intel/i855gme/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i855gme/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i855gme/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,8 @@ +config NORTHBRIDGE_INTEL_I855GME + bool + default n + +config HAVE_HIGH_TABLES + bool + default y + depends on NORTHBRIDGE_INTEL_I855GME Added: trunk/coreboot-v2/src/northbridge/intel/i855gme/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i855gme/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i855gme/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1 @@ +obj-y += northbridge.o Added: trunk/coreboot-v2/src/northbridge/intel/i855pm/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i855pm/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i855pm/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,8 @@ +config NORTHBRIDGE_INTEL_I855PM + bool + default n + +config HAVE_HIGH_TABLES + bool + default y + depends on NORTHBRIDGE_INTEL_I855PM Added: trunk/coreboot-v2/src/northbridge/intel/i855pm/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i855pm/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i855pm/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1 @@ +obj-y += northbridge.o Modified: trunk/coreboot-v2/src/northbridge/intel/i945/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/northbridge/intel/i945/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -20,3 +20,9 @@ config NORTHBRIDGE_INTEL_I945 bool default n + +config HAVE_HIGH_TABLES + bool + default y + depends on NORTHBRIDGE_INTEL_I945 + Modified: trunk/coreboot-v2/src/northbridge/intel/i945/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/northbridge/intel/i945/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -17,8 +17,6 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -driver-$(CONFIG_NORTHBRIDGE_INTEL_I945) += northbridge.o -driver-$(CONFIG_NORTHBRIDGE_INTEL_I945) += gma.o -ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) - obj-$(CONFIG_NORTHBRIDGE_INTEL_I945) += acpi.o -endif +driver-y += northbridge.o +driver-y += gma.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi.o Modified: trunk/coreboot-v2/src/northbridge/via/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/via/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/northbridge/via/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -1,6 +1,6 @@ -#source src/northbridge/via/cn700/Kconfig +source src/northbridge/via/cn700/Kconfig source src/northbridge/via/cx700/Kconfig source src/northbridge/via/cn400/Kconfig -#source src/northbridge/via/vt8601/Kconfig -#source src/northbridge/via/vt8623/Kconfig -#source src/northbridge/via/vx800/Kconfig +source src/northbridge/via/vt8601/Kconfig +source src/northbridge/via/vt8623/Kconfig +source src/northbridge/via/vx800/Kconfig Modified: trunk/coreboot-v2/src/northbridge/via/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/via/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/northbridge/via/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -1,7 +1,7 @@ -#subdirs-y += vt8601 -#subdirs-y += vt8623 -#subdirs-y += cn700 +subdirs-$(CONFIG_NORTHBRIDGE_VIA_VT8601) += vt8601 +subdirs-$(CONFIG_NORTHBRIDGE_VIA_VT8623) += vt8623 +subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN700) += cn700 subdirs-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700 subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN400) += cn400 -#subdirs-y += vx800 +subdirs-$(CONFIG_NORTHBRIDGE_VIA_VX800) += vx800 Added: trunk/coreboot-v2/src/northbridge/via/cn700/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cn700/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/via/cn700/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,13 @@ +config NORTHBRIDGE_VIA_CN700 + bool + default n + +config FALLBACK_SIZE + int + default 0 + depends on NORTHBRIDGE_VIA_CN700 + +config HAVE_HIGH_TABLES + bool + default y + depends on NORTHBRIDGE_VIA_CN700 Added: trunk/coreboot-v2/src/northbridge/via/cn700/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cn700/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/via/cn700/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +obj-y += vgabios.o + +driver-y += northbridge.o +driver-y += agp.o +driver-y += vga.o + Added: trunk/coreboot-v2/src/northbridge/via/vt8601/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8601/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/via/vt8601/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,13 @@ +config NORTHBRIDGE_VIA_VT8601 + bool + default n + +config FALLBACK_SIZE + int + default 0 + depends on NORTHBRIDGE_VIA_VT8601 + +config HAVE_HIGH_TABLES + bool + default y + depends on NORTHBRIDGE_VIA_VT8601 Added: trunk/coreboot-v2/src/northbridge/via/vt8601/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8601/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/via/vt8601/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += northbridge.o + Added: trunk/coreboot-v2/src/northbridge/via/vt8623/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8623/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/via/vt8623/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,13 @@ +config NORTHBRIDGE_VIA_VT8623 + bool + default n + +config FALLBACK_SIZE + int + default 0 + depends on NORTHBRIDGE_VIA_VT8623 + +config HAVE_HIGH_TABLES + bool + default y + depends on NORTHBRIDGE_VIA_VT8623 Added: trunk/coreboot-v2/src/northbridge/via/vt8623/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8623/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/via/vt8623/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += northbridge.o + Added: trunk/coreboot-v2/src/northbridge/via/vx800/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vx800/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/via/vx800/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,8 @@ +config NORTHBRIDGE_VIA_VX800 + bool + default n + +config FALLBACK_SIZE + int + default 0 + depends on NORTHBRIDGE_VIA_VX800 Added: trunk/coreboot-v2/src/northbridge/via/vx800/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vx800/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/via/vx800/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,27 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +obj-y += vgabios.o + +driver-y += northbridge.o +driver-y += vga.o +driver-y += vx800_lpc.o +driver-y += vx800_ide.o + Modified: trunk/coreboot-v2/src/southbridge/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/southbridge/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -1,8 +1,8 @@ source src/southbridge/amd/Kconfig -#source src/southbridge/broadcom/Kconfig +source src/southbridge/broadcom/Kconfig source src/southbridge/intel/Kconfig source src/southbridge/nvidia/Kconfig -#source src/southbridge/ricoh/Kconfig -#source src/southbridge/sis/Kconfig +source src/southbridge/ricoh/Kconfig +source src/southbridge/sis/Kconfig source src/southbridge/via/Kconfig -#source src/southbridge/winbond/Kconfig +source src/southbridge/winbond/Kconfig Modified: trunk/coreboot-v2/src/southbridge/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/southbridge/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -1,8 +1,8 @@ subdirs-y += amd -#subdirs-y += broadcom +subdirs-y += broadcom subdirs-y += intel subdirs-y += nvidia -#subdirs-y += ricoh -#subdirs-y += sis +subdirs-y += ricoh +subdirs-y += sis subdirs-y += via -#subdirs-y += winbond +subdirs-y += winbond Modified: trunk/coreboot-v2/src/southbridge/amd/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/southbridge/amd/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -2,9 +2,9 @@ source src/southbridge/amd/amd8131/Kconfig source src/southbridge/amd/cs5536/Kconfig #source src/southbridge/amd/amd8131-disable/Kconfig -#source src/southbridge/amd/amd8132/Kconfig -#source src/southbridge/amd/amd8151/Kconfig -#source src/southbridge/amd/cs5530/Kconfig -#source src/southbridge/amd/cs5535/Kconfig +source src/southbridge/amd/amd8132/Kconfig +source src/southbridge/amd/amd8151/Kconfig +source src/southbridge/amd/cs5530/Kconfig +source src/southbridge/amd/cs5535/Kconfig source src/southbridge/amd/rs690/Kconfig source src/southbridge/amd/sb600/Kconfig Added: trunk/coreboot-v2/src/southbridge/amd/amd8132/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8132/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/amd/amd8132/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_AMD_AMD8132 + bool + default n Added: trunk/coreboot-v2/src/southbridge/amd/amd8132/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8132/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/amd/amd8132/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1 @@ +driver-y += amd8132_bridge.o Added: trunk/coreboot-v2/src/southbridge/amd/amd8151/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8151/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/amd/amd8151/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_AMD_AMD8151 + bool + default n Added: trunk/coreboot-v2/src/southbridge/amd/amd8151/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8151/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/amd/amd8151/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1 @@ +driver-y += amd8151_agp3.o Added: trunk/coreboot-v2/src/southbridge/amd/cs5530/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5530/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/amd/cs5530/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_AMD_CS5530 + bool + default n Added: trunk/coreboot-v2/src/southbridge/amd/cs5530/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5530/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/amd/cs5530/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,25 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += cs5530.o +driver-y += cs5530_isa.o +driver-y += cs5530_ide.o +driver-y += cs5530_vga.o +driver-y += cs5530_pirq.o Added: trunk/coreboot-v2/src/southbridge/amd/cs5535/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5535/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/amd/cs5535/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_AMD_CS5535 + bool + default n Added: trunk/coreboot-v2/src/southbridge/amd/cs5535/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5535/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/amd/cs5535/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +driver-y += cs5535.o +#driver-y += cs5535_pci.o +#driver-y += cs5535_ide.o Modified: trunk/coreboot-v2/src/southbridge/broadcom/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/southbridge/broadcom/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -1,4 +1,3 @@ -subdirs-y += bcm21000 -subdirs-y += bcm5780 -subdirs-y += bcm5785 - +subdirs-$(CONFIG_SOUTHBRIDGE_BROADCOM_BCM21000) += bcm21000 +subdirs-$(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5780) += bcm5780 +subdirs-$(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5785) += bcm5785 Added: trunk/coreboot-v2/src/southbridge/broadcom/bcm21000/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/bcm21000/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/broadcom/bcm21000/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_BROADCOM_BCM21000 + bool + default n Added: trunk/coreboot-v2/src/southbridge/broadcom/bcm21000/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/bcm21000/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/broadcom/bcm21000/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1 @@ +driver-y += bcm21000_pcie.o Added: trunk/coreboot-v2/src/southbridge/broadcom/bcm5780/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/bcm5780/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/broadcom/bcm5780/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_BROADCOM_BCM5780 + bool + default n Added: trunk/coreboot-v2/src/southbridge/broadcom/bcm5780/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/bcm5780/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/broadcom/bcm5780/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +driver-y += bcm5780_nic.o +driver-y += bcm5780_pcix.o +driver-y += bcm5780_pcie.o Added: trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_BROADCOM_BCM5785 + bool + default n Added: trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,7 @@ +driver-y += bcm5785.o +driver-y += bcm5785_usb.o +driver-y += bcm5785_lpc.o +driver-y += bcm5785_sb_pci_main.o +driver-y += bcm5785_ide.o +driver-y += bcm5785_sata.o +obj-y += bcm5785_reset.o Modified: trunk/coreboot-v2/src/southbridge/intel/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/southbridge/intel/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -1,10 +1,10 @@ -#source src/southbridge/intel/esb6300/Kconfig -#source src/southbridge/intel/i3100/Kconfig +source src/southbridge/intel/esb6300/Kconfig +source src/southbridge/intel/i3100/Kconfig source src/southbridge/intel/i82371eb/Kconfig -#source src/southbridge/intel/i82801ca/Kconfig -#source src/southbridge/intel/i82801dbm/Kconfig -#source src/southbridge/intel/i82801er/Kconfig +source src/southbridge/intel/i82801ca/Kconfig +source src/southbridge/intel/i82801dbm/Kconfig +source src/southbridge/intel/i82801er/Kconfig source src/southbridge/intel/i82801gx/Kconfig source src/southbridge/intel/i82801xx/Kconfig -#source src/southbridge/intel/i82870/Kconfig -#source src/southbridge/intel/pxhd/Kconfig +source src/southbridge/intel/i82870/Kconfig +source src/southbridge/intel/pxhd/Kconfig Modified: trunk/coreboot-v2/src/southbridge/intel/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/southbridge/intel/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -1,11 +1,11 @@ -#subdirs-y += esb6300 -#subdirs-y += i3100 -subdirs-y += i82371eb -#subdirs-y += i82801ca -#subdirs-y += i82801dbm -#subdirs-y += i82801er -subdirs-y += i82801gx -subdirs-y += i82801xx -#subdirs-y += i82870 -#subdirs-y += pxhd +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_ESB6300) += esb6300 +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I3100) += i3100 +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801CA) += i82801ca +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801DBM) += i82801dbm +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801ER) += i82801er +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82870) += i82870 +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_PXHD) += pxhd Added: trunk/coreboot-v2/src/southbridge/intel/esb6300/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/esb6300/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/esb6300/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_INTEL_ESB6300 + bool + default n Added: trunk/coreboot-v2/src/southbridge/intel/esb6300/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/esb6300/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/esb6300/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,11 @@ +driver-y += esb6300.o +driver-y += esb6300_uhci.o +driver-y += esb6300_lpc.o +driver-y += esb6300_ide.o +driver-y += esb6300_sata.o +driver-y += esb6300_ehci.o +driver-y += esb6300_smbus.o +driver-y += esb6300_pci.o +driver-y += esb6300_pic.o +driver-y += esb6300_bridge1c.o +driver-y += esb6300_ac97.o Added: trunk/coreboot-v2/src/southbridge/intel/i3100/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_INTEL_I3100 + bool + default n Added: trunk/coreboot-v2/src/southbridge/intel/i3100/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,9 @@ +driver-y += i3100.o +driver-y += i3100_uhci.o +driver-y += i3100_lpc.o +driver-y += i3100_sata.o +driver-y += i3100_ehci.o +driver-y += i3100_smbus.o +driver-y += i3100_pci.o +obj-y += i3100_reset.o +obj-y += i3100_pciexp_portb.o Modified: trunk/coreboot-v2/src/southbridge/intel/i82371eb/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82371eb/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/southbridge/intel/i82371eb/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -18,11 +18,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_isa.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_ide.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_usb.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_smbus.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_reset.o +driver-y += i82371eb.o +driver-y += i82371eb_isa.o +driver-y += i82371eb_ide.o +driver-y += i82371eb_usb.o +driver-y += i82371eb_smbus.o +driver-y += i82371eb_reset.o -#initobj-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_early_rom.o +#initobj-y += i82371eb_early_rom.o Added: trunk/coreboot-v2/src/southbridge/intel/i82801ca/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801ca/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801ca/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_INTEL_I82801CA + bool + default n Added: trunk/coreboot-v2/src/southbridge/intel/i82801ca/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801ca/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801ca/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,10 @@ +driver-y += i82801ca.o +driver-y += i82801ca_usb.o +driver-y += i82801ca_lpc.o + +driver-$(CONFIG_IDE) += i82801ca_ide.o + +driver-y += i82801ca_ac97.o +#driver-y += i82801ca_nic.o +driver-y += i82801ca_pci.o +obj-y += i82801ca_reset.o Added: trunk/coreboot-v2/src/southbridge/intel/i82801dbm/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801dbm/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801dbm/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_INTEL_I82801DBM + bool + default n Added: trunk/coreboot-v2/src/southbridge/intel/i82801dbm/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801dbm/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801dbm/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,9 @@ +driver-y += i82801dbm.o +driver-y += i82801dbm_usb.o +driver-y += i82801dbm_lpc.o +driver-y += i82801dbm_ide.o +driver-y += i82801dbm_usb2.o +driver-y += i82801dbm_ac97.o +#driver-y += i82801dbm_nic.o +#driver-y += i82801dbm_pci.o +obj-y += i82801dbm_reset.o Added: trunk/coreboot-v2/src/southbridge/intel/i82801er/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801er/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801er/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_INTEL_I82801ER + bool + default n Added: trunk/coreboot-v2/src/southbridge/intel/i82801er/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801er/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801er/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,11 @@ +driver-y += i82801er.o +driver-y += i82801er_uhci.o +driver-y += i82801er_lpc.o +driver-y += i82801er_ide.o +driver-y += i82801er_sata.o +driver-y += i82801er_ehci.o +driver-y += i82801er_smbus.o +driver-y += i82801er_pci.o +driver-y += i82801er_ac97.o +obj-y += i82801er_watchdog.o +obj-y += i82801er_reset.o Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -17,24 +17,21 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_ac97.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_azalia.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_ide.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_lpc.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_nic.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_pci.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_pcie.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_sata.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_smbus.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_usb.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_usb_ehci.o +driver-y += i82801gx.o +driver-y += i82801gx_ac97.o +driver-y += i82801gx_azalia.o +driver-y += i82801gx_ide.o +driver-y += i82801gx_lpc.o +driver-y += i82801gx_nic.o +driver-y += i82801gx_pci.o +driver-y += i82801gx_pcie.o +driver-y += i82801gx_sata.o +driver-y += i82801gx_smbus.o +driver-y += i82801gx_usb.o +driver-y += i82801gx_usb_ehci.o -object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_reset.o -object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_watchdog.o +object-y += i82801gx_reset.o +object-y += i82801gx_watchdog.o -# arg. How does the linux kconfig handle compound conditionals? -ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) - object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_smi.o - smmobj-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_smihandler.o -endif +object-$(CONFIG_HAVE_SMI_HANDLER) += i82801gx_smi.o +smmobj-$(CONFIG_HAVE_SMI_HANDLER) += i82801gx_smihandler.o Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -18,19 +18,19 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_ac97.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_ide.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_lpc.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_nic.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_pci.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_sata.o -# driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_smbus.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_usb.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_usb_ehci.o +driver-y += i82801xx.o +driver-y += i82801xx_ac97.o +driver-y += i82801xx_ide.o +driver-y += i82801xx_lpc.o +driver-y += i82801xx_nic.o +driver-y += i82801xx_pci.o +driver-y += i82801xx_sata.o +# driver-y += i82801xx_smbus.o +driver-y += i82801xx_usb.o +driver-y += i82801xx_usb_ehci.o -object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_reset.o -object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_watchdog.o +object-y += i82801xx_reset.o +object-y += i82801xx_watchdog.o # TODO: What about cmos_failover.c? Added: trunk/coreboot-v2/src/southbridge/intel/i82870/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82870/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82870/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_INTEL_I82870 + bool + default n Added: trunk/coreboot-v2/src/southbridge/intel/i82870/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82870/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82870/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +driver-y += p64h2_ioapic.o +driver-y += p64h2_pcibridge.o +#driver-y += p64h2_pci_parity.o Added: trunk/coreboot-v2/src/southbridge/intel/pxhd/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/pxhd/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/pxhd/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_INTEL_PXHD + bool + default n Added: trunk/coreboot-v2/src/southbridge/intel/pxhd/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/pxhd/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/pxhd/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1 @@ +driver-y += pxhd_bridge.o Modified: trunk/coreboot-v2/src/southbridge/ricoh/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/ricoh/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/southbridge/ricoh/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -1 +1 @@ -subdirs-y += rl5c476 +subdirs-$(CONFIG_SOUTHBRIDGE_RICOH_RL5C476) += rl5c476 Added: trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_RICOH_RL5C476 + bool + default n + Added: trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1 @@ +driver-y += rl5c476.o Modified: trunk/coreboot-v2/src/southbridge/sis/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/sis/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/southbridge/sis/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -1,2 +1,2 @@ -subdirs-y += sis966 +subdirs-$(CONFIG_SOUTHBRIDGE_SIS_SIS966) += sis966 Added: trunk/coreboot-v2/src/southbridge/sis/sis966/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/sis/sis966/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/sis/sis966/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_SIS_SIS966 + bool + default n Added: trunk/coreboot-v2/src/southbridge/sis/sis966/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/sis/sis966/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/sis/sis966/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,11 @@ +driver-y += sis761.o +driver-y += sis966.o +driver-y += sis966_lpc.o +driver-y += sis966_ide.o +driver-y += sis966_usb.o +driver-y += sis966_usb2.o +driver-y += sis966_nic.o +driver-y += sis966_sata.o +driver-y += sis966_pcie.o +driver-y += sis966_aza.o +obj-y += sis966_reset.o Modified: trunk/coreboot-v2/src/southbridge/via/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/via/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/southbridge/via/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -1,5 +1,4 @@ -#source src/southbridge/via/k8t890/Kconfig -#source src/southbridge/via/vt8231/Kconfig -#source src/southbridge/via/vt8235/Kconfig +source src/southbridge/via/k8t890/Kconfig +source src/southbridge/via/vt8231/Kconfig +source src/southbridge/via/vt8235/Kconfig source src/southbridge/via/vt8237r/Kconfig -#source src/southbridge/via/vt82c686/Kconfig Modified: trunk/coreboot-v2/src/southbridge/via/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/via/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/southbridge/via/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -1,5 +1,4 @@ -#subdirs-y += k8t890 -#subdirs-y += vt8231 -#subdirs-y += vt8235 +subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T890) += k8t890 +subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8231) += vt8231 +subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8235) += vt8235 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8237R) += vt8237r -#subdirs-y += vt82c686 Added: trunk/coreboot-v2/src/southbridge/via/k8t890/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/via/k8t890/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/via/k8t890/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,4 @@ +config SOUTHBRIDGE_VIA_K8T890 + bool + default n + Added: trunk/coreboot-v2/src/southbridge/via/k8t890/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/via/k8t890/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/via/k8t890/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,9 @@ +driver-y += k8t890_ctrl.o +driver-y += k8t890_dram.o +driver-y += k8t890_bridge.o +driver-y += k8t890_host.o +driver-y += k8t890_host_ctrl.o +driver-y += k8t890_pcie.o +driver-y += k8t890_traf_ctrl.o +driver-y += k8t890_error.o +driver-y += k8m890_chrome.o Added: trunk/coreboot-v2/src/southbridge/via/vt8231/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8231/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/via/vt8231/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_VIA_VT8231 + bool + default n + Added: trunk/coreboot-v2/src/southbridge/via/vt8231/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8231/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/via/vt8231/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,25 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007, 2009 Rudolf Marek <r.marek(a)assembler.cz> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License v2 as published by +## the Free Software Foundation. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += vt8231.o +driver-y += vt8231_lpc.o +driver-y += vt8231_acpi.o +driver-y += vt8231_ide.o +driver-y += vt8231_nic.o +#driver-y += vt8231_usb.o Added: trunk/coreboot-v2/src/southbridge/via/vt8235/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8235/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/via/vt8235/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_VIA_VT8235 + bool + default n + Added: trunk/coreboot-v2/src/southbridge/via/vt8235/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8235/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/via/vt8235/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007, 2009 Rudolf Marek <r.marek(a)assembler.cz> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License v2 as published by +## the Free Software Foundation. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += vt8235.o +driver-y += vt8235_ide.o +driver-y += vt8235_lpc.o +driver-y += vt8235_nic.o +driver-y += vt8235_usb.o Modified: trunk/coreboot-v2/src/southbridge/winbond/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/winbond/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) +++ trunk/coreboot-v2/src/southbridge/winbond/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -1 +1 @@ -subdirs-y += w83c553 +subdirs-$(CONFIG_SOUTHBRIDGE_WINBOND_W83C553) += w83c553 Added: trunk/coreboot-v2/src/southbridge/winbond/w83c553/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/winbond/w83c553/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/winbond/w83c553/Kconfig 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_WINBOND_W83C553 + bool + default n Added: trunk/coreboot-v2/src/southbridge/winbond/w83c553/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/winbond/w83c553/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/winbond/w83c553/Makefile.inc 2009-09-25 18:43:02 UTC (rev 4673) @@ -0,0 +1,2 @@ +driver-y += w83c553f.o +driver-y += w83c553f_ide.o

1 0

build service results for r4672
by coreboot information 25 Sep '09

25 Sep '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4672 to the coreboot repository. This caused the following changes: Change Log: Rename CONFIG_SERIAL_CONSOLE to match newconfig. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4672&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4672&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4672&device=briq&vendor=to… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[PATCH] Serial console driver
by Myles Watson 25 Sep '09

25 Sep '09

This patch changes CONFIG_SERIAL_CONSOLE to CONFIG_CONSOLE_SERIAL8250 to match newconfig. That makes it so that the #ifdefs in code still work. I think we should avoid changing names until the conversion is complete. The other way to do it is to change all the occurrences in all the board's Options.lb files and in the code. I get serial either way... Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 2

[v2] r4672 - trunk/coreboot-v2/src/console
by svn＠coreboot.org 25 Sep '09

25 Sep '09

Author: myles Date: 2009-09-25 19:24:08 +0200 (Fri, 25 Sep 2009) New Revision: 4672 Modified: trunk/coreboot-v2/src/console/Kconfig trunk/coreboot-v2/src/console/Makefile.inc Log: Rename CONFIG_SERIAL_CONSOLE to match newconfig. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/console/Kconfig =================================================================== --- trunk/coreboot-v2/src/console/Kconfig 2009-09-24 16:56:08 UTC (rev 4671) +++ trunk/coreboot-v2/src/console/Kconfig 2009-09-25 17:24:08 UTC (rev 4672) @@ -1,6 +1,7 @@ menu "Console options" -config SERIAL_CONSOLE +config CONSOLE_SERIAL8250 + #TODO Rename to SERIAL_CONSOLE once Kconfig transition is complete. bool "See output on the serial port console" default y @@ -10,13 +11,13 @@ config TTYS0_BASE hex "I/O base for the serial port" - depends on SERIAL_CONSOLE + depends on CONSOLE_SERIAL8250 default 0x3f8 config SERIAL_SET_SPEED bool "Override the serial console BAUD rate" default y - depends on SERIAL_CONSOLE + depends on CONSOLE_SERIAL8250 config TTYS0_BAUD int "Serial console BAUD rate" Modified: trunk/coreboot-v2/src/console/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/console/Makefile.inc 2009-09-24 16:56:08 UTC (rev 4671) +++ trunk/coreboot-v2/src/console/Makefile.inc 2009-09-25 17:24:08 UTC (rev 4672) @@ -6,7 +6,7 @@ initobj-y += vtxprintf.o initobj-y += vsprintf.o -driver-$(CONFIG_SERIAL_CONSOLE) += uart8250_console.o +driver-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.o driver-$(CONFIG_USBDEBUG_DIRECT) += usbdebug_direct_console.o driver-$(CONFIG_CONSOLE_VGA) += vga_console.o driver-$(CONFIG_CONSOLE_BTEXT) += btext_console.o

1 0

it's now called "microEFI" by the way
by ron minnich 25 Sep '09

25 Sep '09

uEFI now means micro-EFI. Not to be confused with UEFI, the "Universal" EFI. What's in a letter :-) So I wonder how much of EFI is stripped out to make it micro? Of course, even if I knew, the agreements might make it impossible for me to say. ron

1 0

EHCI Debug port support?
by TigerLiu＠viatech.com.cn 25 Sep '09

25 Sep '09

Hi: I reviewed the source code of coreboot-v2-4671. I found the EHCI debug port source code at " src\lib" && "src\console" dirs. So, that means: I plugged a USB-2-Serial device into the usb port on the target platform, then, I used a serial line connected to the host's COM port, then, I could see the debug messages output from the target platform? Best wishes,

2 1

[flashrom] [PATCH] SST SST49LF003A/B should be marked as TEST_OK_PR
by Peter Lemenkov 25 Sep '09

25 Sep '09

Hello All! I reported earlier, that I successfully extracted BIOS image from SST49LF003A/B, but cannot verify it yet. Nowadays, using wonderful bios_extract utility, I can provide confirmation, that everything was extracted correctly. Here is the simple patch. Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- Here are logs of extraction of BIOS from chip, and extraction of various BLOBs from BIOS image: [petro@Workplace tmp]$ sudo ~/work/flashrom/flashrom -r bios.bin flashrom v0.9.0-runknown No coreboot table found. Found chipset "Intel ICH6/ICH6R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF003A/B" (384 KB, FWH) at physical address 0xfffa0000. === This flash part has status UNTESTED for operations: READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard you tested. Thanks for your help! === Reading flash... done. [petro@Workplace tmp]$ ~/work/bios_extract/bios_extract bios.bin Using file "bios.bin" (384kB) Found Award BIOS. 0x00000 ( 79260 bytes) -> 8i9me.BIN (131072 bytes) 0x1359E ( 40539 bytes) -> awardext.rom ( 57600 bytes) 0x1D3FA ( 5375 bytes) -> ACPITBL.BIN ( 14956 bytes) 0x1E8FA ( 681 bytes) -> AwardBmp.bmp ( 5772 bytes) 0x1EBA4 ( 19354 bytes) -> awardeyt.rom ( 28336 bytes) 0x2373F ( 8997 bytes) -> _EN_CODE.BIN ( 22064 bytes) 0x25A65 ( 28551 bytes) -> GSDALE.VGA ( 65536 bytes) 0x2C9ED ( 747 bytes) -> GSDALE.VBT ( 1632 bytes) 0x2CCD9 ( 30268 bytes) -> RTGBROM.LOM ( 49152 bytes) 0x34316 ( 32167 bytes) -> rtk_pxe.211 ( 53248 bytes) 0x3C0BE ( 2774 bytes) -> PPMINIT.ROM ( 6365 bytes) 0x3CB95 ( 12899 bytes) -> FINER.BIN ( 28102 bytes) 0x3FDF9 ( 6020 bytes) -> SBF.BIN ( 7974 bytes) [petro@Workplace tmp]$ -- With best regards!

2 1

inteltool patch (third version)
by Maciej Pijanka 25 Sep '09

25 Sep '09

Hello fixed another one mistake, g'night -- Maciej Pijanka, PLD-Linux Developer, Reg Linux user #133161 POE/Perl user

1 0

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coreboot September 2009