coreboot August 2009

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[v2] r4575 - trunk/coreboot-v2/src/mainboard
by svn＠coreboot.org 25 Aug '09

25 Aug '09

Author: myles Date: 2009-08-25 16:41:38 +0200 (Tue, 25 Aug 2009) New Revision: 4575 Modified: trunk/coreboot-v2/src/mainboard/Kconfig Log: Add vendor strings in mainboard/Kconfig. Trivial. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/Kconfig 2009-08-25 14:22:58 UTC (rev 4574) +++ trunk/coreboot-v2/src/mainboard/Kconfig 2009-08-25 14:41:38 UTC (rev 4575) @@ -97,24 +97,224 @@ config MAINBOARD_VENDOR string + default "A-Trend" + depends on VENDOR_ATREND + +config MAINBOARD_VENDOR + string + default "Abit" + depends on VENDOR_ABIT + +config MAINBOARD_VENDOR + string + default "Advantech" + depends on VENDOR_ADVANTECH + +config MAINBOARD_VENDOR + string + default "agami" + depends on VENDOR_AGAMI + +config MAINBOARD_VENDOR + string + default "AMD" + depends on VENDOR_AMD + +config MAINBOARD_VENDOR + string + default "Arima" + depends on VENDOR_ARIMA + +config MAINBOARD_VENDOR + string + default "Artec Group" + depends on VENDOR_ARTEC + +config MAINBOARD_VENDOR + string + default "ASI" + depends on VENDOR_ASI + +config MAINBOARD_VENDOR + string + default "ASUS" + depends on VENDOR_ASUS + +config MAINBOARD_VENDOR + string + default "AXUS" + depends on VENDOR_AXUS + +config MAINBOARD_VENDOR + string + default "AZZA" + depends on VENDOR_AZZA + +config MAINBOARD_VENDOR + string + default "BCOM" + depends on VENDOR_BCOM + +config MAINBOARD_VENDOR + string + default "Biostar" + depends on VENDOR_BIOSTAR + +config MAINBOARD_VENDOR + string + default "Broadcom" + depends on VENDOR_BROADCOM + +config MAINBOARD_VENDOR + string + default "Compaq" + depends on VENDOR_COMPAQ + +config MAINBOARD_VENDOR + string + default "Dell" + depends on VENDOR_DELL + +config MAINBOARD_VENDOR + string + default "DIGITAL-LOGIC" + depends on VENDOR_DIGITALLOGIC + +config MAINBOARD_VENDOR + string + default "EagleLion" + depends on VENDOR_EAGLELION + +config MAINBOARD_VENDOR + string + default "Embedded Planet" + depends on VENDOR_EMBEDDEDPLANET + +config MAINBOARD_VENDOR + string default "Emulation" depends on VENDOR_EMULATION config MAINBOARD_VENDOR string + default "GIGABYTE" + depends on VENDOR_GIGABYTE + +config MAINBOARD_VENDOR + string + default "HP" + depends on VENDOR_HP + +config MAINBOARD_VENDOR + string + default "IBM" + depends on VENDOR_IBM + +config MAINBOARD_VENDOR + string + default "IEI" + depends on VENDOR_IEI + +config MAINBOARD_VENDOR + string + default "Intel" + depends on VENDOR_INTEL + +config MAINBOARD_VENDOR + string + default "IWILL" + depends on VENDOR_IWILL + +config MAINBOARD_VENDOR + string + default "Jetway" + depends on VENDOR_JETWAY + +config MAINBOARD_VENDOR + string default "Kontron" depends on VENDOR_KONTRON config MAINBOARD_VENDOR string - default "VIA" - depends on VENDOR_VIA + default "Lippert" + depends on VENDOR_LIPPERT config MAINBOARD_VENDOR string - default "AMD" - depends on VENDOR_AMD + default "Motorola" + depends on VENDOR_MOTOROLA +config MAINBOARD_VENDOR + string + default "MSI" + depends on VENDOR_MSI + +config MAINBOARD_VENDOR + string + default "NEC" + depends on VENDOR_NEC + +config MAINBOARD_VENDOR + string + default "Newisys" + depends on VENDOR_NEWISYS + +config MAINBOARD_VENDOR + string + default "NVIDIA" + depends on VENDOR_NVIDIA + +config MAINBOARD_VENDOR + string + default "OLPC" + depends on VENDOR_OLPC + +config MAINBOARD_VENDOR + string + default "PC Engines" + depends on VENDOR_PCENGINES + +config MAINBOARD_VENDOR + string + default "RCA" + depends on VENDOR_RCA + +config MAINBOARD_VENDOR + string + default "Sun" + depends on VENDOR_SUNW + +config MAINBOARD_VENDOR + string + default "Supermicro" + depends on VENDOR_SUPERMICRO + +config MAINBOARD_VENDOR + string + default "Technexion" + depends on VENDOR_TECHNEXION + +config MAINBOARD_VENDOR + string + default "Thomson" + depends on VENDOR_THOMSON + +config MAINBOARD_VENDOR + string + default "Total Impact" + depends on VENDOR_TOTALIMPACT + +config MAINBOARD_VENDOR + string + default "Tyan" + depends on VENDOR_TYAN + +config MAINBOARD_VENDOR + string + default "VIA" + depends on VENDOR_VIA + config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex default 0x1019

1 0

[v2] r4574 - in trunk/coreboot-v2/src/cpu/amd: . model_fxx socket_940 socket_AM2 socket_F
by svn＠coreboot.org 25 Aug '09

25 Aug '09

Author: myles Date: 2009-08-25 16:22:58 +0200 (Tue, 25 Aug 2009) New Revision: 4574 Added: trunk/coreboot-v2/src/cpu/amd/socket_940/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_940/Makefile.inc Modified: trunk/coreboot-v2/src/cpu/amd/Kconfig trunk/coreboot-v2/src/cpu/amd/Makefile.inc trunk/coreboot-v2/src/cpu/amd/model_fxx/Makefile.inc trunk/coreboot-v2/src/cpu/amd/socket_AM2/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_AM2/Makefile.inc trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_F/Makefile.inc Log: Add support for AMD Socket 940. Move common files to model_fxx. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/cpu/amd/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/Kconfig 2009-08-25 13:53:14 UTC (rev 4573) +++ trunk/coreboot-v2/src/cpu/amd/Kconfig 2009-08-25 14:22:58 UTC (rev 4574) @@ -1,6 +1,6 @@ #source src/cpu/amd/socket_754/Kconfig #source src/cpu/amd/socket_939/Kconfig -#source src/cpu/amd/socket_940/Kconfig +source src/cpu/amd/socket_940/Kconfig source src/cpu/amd/socket_AM2/Kconfig #source src/cpu/amd/socket_AM2r2/Kconfig source src/cpu/amd/socket_F/Kconfig Modified: trunk/coreboot-v2/src/cpu/amd/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/Makefile.inc 2009-08-25 13:53:14 UTC (rev 4573) +++ trunk/coreboot-v2/src/cpu/amd/Makefile.inc 2009-08-25 14:22:58 UTC (rev 4574) @@ -1,2 +1,3 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_F) += socket_F +subdirs-$(CONFIG_CPU_AMD_SOCKET_940) += socket_940 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2) += socket_AM2 Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/Makefile.inc 2009-08-25 13:53:14 UTC (rev 4573) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/Makefile.inc 2009-08-25 14:22:58 UTC (rev 4574) @@ -4,3 +4,16 @@ obj-y += model_fxx_update_microcode.o obj-y += processor_name.o obj-y += powernow_acpi.o +subdirs-y += ../dualcore +subdirs-y += ../mtrr +subdirs-y += ../microcode +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/fpu +subdirs-y += ../../x86/mmx +subdirs-y += ../../x86/sse +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/pae +subdirs-y += ../../x86/smm Copied: trunk/coreboot-v2/src/cpu/amd/socket_940/Kconfig (from rev 4558, trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig) =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_940/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/socket_940/Kconfig 2009-08-25 14:22:58 UTC (rev 4574) @@ -0,0 +1,14 @@ +config CPU_AMD_SOCKET_940 + bool + default false + +config K8_REV_F_SUPPORT + bool + default n + depends on CPU_AMD_SOCKET_940 + +#Opteron K8 1G HT Support +config K8_HT_FREQ_1G_SUPPORT + hex + default 1 + depends on CPU_AMD_SOCKET_940 Property changes on: trunk/coreboot-v2/src/cpu/amd/socket_940/Kconfig ___________________________________________________________________ Added: svn:mergeinfo + Copied: trunk/coreboot-v2/src/cpu/amd/socket_940/Makefile.inc (from rev 4564, trunk/coreboot-v2/src/cpu/amd/socket_F/Makefile.inc) =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_940/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/socket_940/Makefile.inc 2009-08-25 14:22:58 UTC (rev 4574) @@ -0,0 +1,2 @@ +obj-y += socket_940.o +subdirs-y += ../model_fxx Property changes on: trunk/coreboot-v2/src/cpu/amd/socket_940/Makefile.inc ___________________________________________________________________ Added: svn:mergeinfo + Modified: trunk/coreboot-v2/src/cpu/amd/socket_AM2/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_AM2/Kconfig 2009-08-25 13:53:14 UTC (rev 4573) +++ trunk/coreboot-v2/src/cpu/amd/socket_AM2/Kconfig 2009-08-25 14:22:58 UTC (rev 4574) @@ -8,8 +8,8 @@ depends on CPU_AMD_SOCKET_AM2 config K8_REV_F_SUPPORT - hex - default 1 + bool + default y depends on CPU_AMD_SOCKET_AM2 # Opteron K8 1G HT support Modified: trunk/coreboot-v2/src/cpu/amd/socket_AM2/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_AM2/Makefile.inc 2009-08-25 13:53:14 UTC (rev 4573) +++ trunk/coreboot-v2/src/cpu/amd/socket_AM2/Makefile.inc 2009-08-25 14:22:58 UTC (rev 4574) @@ -1,15 +1,2 @@ obj-y += socket_AM2.o subdirs-y += ../model_fxx -subdirs-y += ../dualcore -subdirs-y += ../mtrr -subdirs-y += ../microcode -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/fpu -subdirs-y += ../../x86/mmx -subdirs-y += ../../x86/sse -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/pae -subdirs-y += ../../x86/smm Modified: trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig 2009-08-25 13:53:14 UTC (rev 4573) +++ trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig 2009-08-25 14:22:58 UTC (rev 4574) @@ -8,8 +8,8 @@ depends on CPU_AMD_SOCKET_F config K8_REV_F_SUPPORT - hex - default 1 + bool + default y depends on CPU_AMD_SOCKET_F # Opteron K8 1G HT support Modified: trunk/coreboot-v2/src/cpu/amd/socket_F/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_F/Makefile.inc 2009-08-25 13:53:14 UTC (rev 4573) +++ trunk/coreboot-v2/src/cpu/amd/socket_F/Makefile.inc 2009-08-25 14:22:58 UTC (rev 4574) @@ -1,14 +1,2 @@ obj-y += socket_F.o subdirs-y += ../model_fxx -subdirs-y += ../dualcore -subdirs-y += ../mtrr -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/fpu -subdirs-y += ../../x86/mmx -subdirs-y += ../../x86/sse -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/pae -subdirs-y += ../../x86/smm

1 0

[PATCH] kconfig support for ASUS P2B-F
by Uwe Hermann 25 Aug '09

25 Aug '09

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

3 4

[v2] r4573 - in trunk/coreboot-v2: . src/arch/i386
by svn＠coreboot.org 25 Aug '09

25 Aug '09

Author: oxygene Date: 2009-08-25 15:53:14 +0200 (Tue, 25 Aug 2009) New Revision: 4573 Modified: trunk/coreboot-v2/Makefile trunk/coreboot-v2/src/arch/i386/Makefile.inc Log: Properly check for the LZMA compression variable, and fix a print message for the VGA ROM that would print a useless NULL string. Signed-off by: Cristi Magherusan <cristi.magherusan(a)net.utcluj.ro> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/coreboot-v2/Makefile =================================================================== --- trunk/coreboot-v2/Makefile 2009-08-25 12:25:36 UTC (rev 4572) +++ trunk/coreboot-v2/Makefile 2009-08-25 13:53:14 UTC (rev 4573) @@ -232,7 +232,7 @@ CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CBFS_COMPRESS_FLAG:= -ifeq "$(CONFIG_COMPRESSED_PAYLOAD_LZMA)" "1" +ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZMA),y) CBFS_COMPRESS_FLAG:=l endif Modified: trunk/coreboot-v2/src/arch/i386/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/arch/i386/Makefile.inc 2009-08-25 12:25:36 UTC (rev 4572) +++ trunk/coreboot-v2/src/arch/i386/Makefile.inc 2009-08-25 13:53:14 UTC (rev 4573) @@ -27,7 +27,7 @@ $(Q) printf " PAYLOAD $(CONFIG_FALLBACK_PAYLOAD_FILE) $(COMPRESSFLAG)\n" $(Q)$(CBFSTOOL) ./build/coreboot.rom add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) fallback/payload $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_VGA_BIOS),y) - $(Q) printf " VGABIOS $(CONFIG_FALLBACK_VGA_BIOS_FILE) $(CONFIG_FALLBACK_VGA_BIOS_ID) $(COMPRESSFLAG)\n" + $(Q) printf " VGABIOS $(CONFIG_FALLBACK_VGA_BIOS_FILE) $(CONFIG_FALLBACK_VGA_BIOS_ID)\n" $(Q) $(CBFSTOOL) ./build/coreboot.rom add $(CONFIG_FALLBACK_VGA_BIOS_FILE) "pci$(CONFIG_FALLBACK_VGA_BIOS_ID).rom" optionrom endif $(Q) printf " CBFSPRINT ./build/coreboot.rom\n\n"

1 0

[v2] r4572 - in trunk/coreboot-v2/src: cpu/intel cpu/intel/slot_2 mainboard/asus mainboard/asus/p2b-f northbridge/intel northbridge/intel/i440bx
by svn＠coreboot.org 25 Aug '09

25 Aug '09

Author: uwe Date: 2009-08-25 14:25:36 +0200 (Tue, 25 Aug 2009) New Revision: 4572 Added: trunk/coreboot-v2/src/cpu/intel/slot_2/Kconfig trunk/coreboot-v2/src/cpu/intel/slot_2/Makefile.inc trunk/coreboot-v2/src/mainboard/asus/p2b-f/Kconfig trunk/coreboot-v2/src/mainboard/asus/p2b-f/Makefile.inc trunk/coreboot-v2/src/northbridge/intel/i440bx/Kconfig trunk/coreboot-v2/src/northbridge/intel/i440bx/Makefile.inc Modified: trunk/coreboot-v2/src/cpu/intel/Kconfig trunk/coreboot-v2/src/cpu/intel/Makefile.inc trunk/coreboot-v2/src/mainboard/asus/Kconfig trunk/coreboot-v2/src/northbridge/intel/Kconfig trunk/coreboot-v2/src/northbridge/intel/Makefile.inc Log: Add kconfig support for ASUS P2B-F. Only build-tested so far, not tested on hardware. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/cpu/intel/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/Kconfig 2009-08-25 12:19:28 UTC (rev 4571) +++ trunk/coreboot-v2/src/cpu/intel/Kconfig 2009-08-25 12:25:36 UTC (rev 4572) @@ -1,4 +1,5 @@ source src/cpu/intel/model_6ex/Kconfig source src/cpu/intel/model_6fx/Kconfig source src/cpu/intel/socket_mFCPGA478/Kconfig -source src/cpu/intel/socket_PGA370/Kconfig \ No newline at end of file +source src/cpu/intel/socket_PGA370/Kconfig +source src/cpu/intel/slot_2/Kconfig Modified: trunk/coreboot-v2/src/cpu/intel/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/Makefile.inc 2009-08-25 12:19:28 UTC (rev 4571) +++ trunk/coreboot-v2/src/cpu/intel/Makefile.inc 2009-08-25 12:25:36 UTC (rev 4572) @@ -5,6 +5,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478 subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370 +subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2 #socket_mPGA478 #socket_mPGA479M Added: trunk/coreboot-v2/src/cpu/intel/slot_2/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/slot_2/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/slot_2/Kconfig 2009-08-25 12:25:36 UTC (rev 4572) @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config CPU_INTEL_SLOT_2 + bool + default n + Added: trunk/coreboot-v2/src/cpu/intel/slot_2/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/slot_2/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/slot_2/Makefile.inc 2009-08-25 12:25:36 UTC (rev 4572) @@ -0,0 +1,32 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +obj-y += slot_2.o +subdirs-y += ../model_6xx +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/fpu +subdirs-y += ../../x86/mmx +subdirs-y += ../../x86/sse +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode + Modified: trunk/coreboot-v2/src/mainboard/asus/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/Kconfig 2009-08-25 12:19:28 UTC (rev 4571) +++ trunk/coreboot-v2/src/mainboard/asus/Kconfig 2009-08-25 12:25:36 UTC (rev 4572) @@ -1 +1,28 @@ -# +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_ASUS + +source "src/mainboard/asus/p2b-f/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/asus/p2b-f/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-f/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/Kconfig 2009-08-25 12:25:36 UTC (rev 4572) @@ -0,0 +1,59 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_ASUS_P2B_F + bool "P2B-F" + select ARCH_X86 + select CPU_INTEL_SLOT_2 + select NORTHBRIDGE_INTEL_I440BX + select SOUTHBRIDGE_INTEL_I82371EB + select SUPERIO_WINBOND_W83977TF + select HAVE_PIRQ_TABLE + select UDELAY_IO + select PCI_ROM_RUN + select CONSOLE_VGA + help + ASUS P2B-F mainboard. + +config MAINBOARD_DIR + string + default asus/p2b-f + depends on BOARD_ASUS_P2B_F + +config MAINBOARD_VENDOR + string + default "ASUS" + depends on BOARD_ASUS_P2B_F + +config MAINBOARD_PART_NUMBER + string + default "P2B-F" + depends on BOARD_ASUS_P2B_F + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_ASUS_P2B_F + +config IRQ_SLOT_COUNT + int + default 7 + depends on BOARD_ASUS_P2B_F + Added: trunk/coreboot-v2/src/mainboard/asus/p2b-f/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-f/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/Makefile.inc 2009-08-25 12:25:36 UTC (rev 4572) @@ -0,0 +1,54 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +initobj-y += crt0.o +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/cpu_reset.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += failover.inc +crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc +crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc +crt0-y += auto.inc +crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +driver-y += mainboard.o + +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c + $(obj)/romcc -mcpu=p2 -O2 --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c + $(obj)/romcc -mcpu=p2 -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + +endif + Modified: trunk/coreboot-v2/src/northbridge/intel/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/Kconfig 2009-08-25 12:19:28 UTC (rev 4571) +++ trunk/coreboot-v2/src/northbridge/intel/Kconfig 2009-08-25 12:25:36 UTC (rev 4572) @@ -2,7 +2,7 @@ #source src/northbridge/intel/e7520/Kconfig #source src/northbridge/intel/e7525/Kconfig #source src/northbridge/intel/i3100/Kconfig -#source src/northbridge/intel/i440bx/Kconfig +source src/northbridge/intel/i440bx/Kconfig source src/northbridge/intel/i82810/Kconfig #source src/northbridge/intel/i82830/Kconfig #source src/northbridge/intel/i855gme/Kconfig Modified: trunk/coreboot-v2/src/northbridge/intel/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/Makefile.inc 2009-08-25 12:19:28 UTC (rev 4571) +++ trunk/coreboot-v2/src/northbridge/intel/Makefile.inc 2009-08-25 12:25:36 UTC (rev 4572) @@ -2,7 +2,7 @@ #subdirs-y += e7520 #subdirs-y += e7525 #subdirs-y += i3100 -#subdirs-y += i440bx +subdirs-y += i440bx subdirs-y += i82810 #subdirs-y += i82830 #subdirs-y += i855gme Added: trunk/coreboot-v2/src/northbridge/intel/i440bx/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i440bx/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i440bx/Kconfig 2009-08-25 12:25:36 UTC (rev 4572) @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config NORTHBRIDGE_INTEL_I440BX + bool + default n + Added: trunk/coreboot-v2/src/northbridge/intel/i440bx/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i440bx/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i440bx/Makefile.inc 2009-08-25 12:25:36 UTC (rev 4572) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-$(CONFIG_NORTHBRIDGE_INTEL_I440BX) += northbridge.o +

1 0

[PATCH] Fix copy-paste error in src/cpu/x86/Kconfig (XIP_*)
by Uwe Hermann 25 Aug '09

25 Aug '09

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

[v2] r4571 - trunk/coreboot-v2/src/cpu/x86
by svn＠coreboot.org 25 Aug '09

25 Aug '09

Author: uwe Date: 2009-08-25 14:19:28 +0200 (Tue, 25 Aug 2009) New Revision: 4571 Modified: trunk/coreboot-v2/src/cpu/x86/Kconfig Log: Fix copy-paste error in src/cpu/x86/Kconfig. That file defines XIP_ROM_BASE twice, but the latter definition should be XIP_ROM_SIZE (not *_BASE). These exact two definitions are listed in src/Kconfig already, though, so maybe one of the two locations should remove them? Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/cpu/x86/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/x86/Kconfig 2009-08-25 12:18:05 UTC (rev 4570) +++ trunk/coreboot-v2/src/cpu/x86/Kconfig 2009-08-25 12:19:28 UTC (rev 4571) @@ -6,6 +6,6 @@ hex default 0xfffe0000 -config XIP_ROM_BASE +config XIP_ROM_SIZE hex default 0x2000

1 0

[PATCH] Only build option_table.o if CONFIG_HAVE_OPTION_TABLE is 'y'
by Uwe Hermann 25 Aug '09

25 Aug '09

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

[v2] r4570 - trunk/coreboot-v2/src/arch/i386
by svn＠coreboot.org 25 Aug '09

25 Aug '09

Author: uwe Date: 2009-08-25 14:18:05 +0200 (Tue, 25 Aug 2009) New Revision: 4570 Modified: trunk/coreboot-v2/src/arch/i386/Makefile.inc Log: Only build option_table.o if CONFIG_HAVE_OPTION_TABLE is 'y'. Not all boards have an option table (cmos.layout). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/arch/i386/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/arch/i386/Makefile.inc 2009-08-25 04:12:55 UTC (rev 4569) +++ trunk/coreboot-v2/src/arch/i386/Makefile.inc 2009-08-25 12:18:05 UTC (rev 4570) @@ -5,7 +5,7 @@ subdirs-y += lib subdirs-y += smp -obj-y += ../../option_table.o +obj-$(CONFIG_HAVE_OPTION_TABLE) += ../../option_table.o ifdef POST_EVALUATION BOOTBLOCK_SIZE=65536

1 0

Re: [coreboot] vga not working
by Arnaud Maye 25 Aug '09

25 Aug '09

As an additional information, I've seen that : 1) coreboot was running at 0x4000. I've changed Options.lb in mainboard\intel\truxton : -- default CONFIG_RAMBASE=0x00004000 ++ default CONFIG_RAMBASE=0x00100000 This did not compile so I've had to add : ++ uses CONFIG_LB_MEM_TOPK ++ default CONFG_LB_MEM_TOPK = 2 * 1024 * 1024 This did not change anything to the VGA problem, I think I will keep this that way, what you guys are thinking about this? 2) My auto.c patch is not consistent as this is called prior the enable_resource function in fact. The function enable_resource is using logical or operations. In this case I still gets some unwanted bits obviously. Actually yesterday I was very tired I guess. The value 0xb means 0b1011 : 2PERRE = 1, 2SERRE = 1 and VGAEN = 1. I am not sure 2PERRE or 2SERRE would be any relevant around my problem. But the legacy BIOS do not set these to 1, this is a fact. Actually what is the best way to get pciexp_porta.c to be included and replace the default PCI functions in src\devices ? As an additional question: 1) Can these memory holes be cached or not. I guess these ranges should not correspond to a cacheable RAM section. Does coreboot cache the complete 0x0 to CONFIG_LB_MEM_TOPK area. The chipset configuration provide the complete memory range as coherent memory. Thank you Arnaud Arnaud Maye wrote: > Myles Watson wrote: >>> The ep80579 has two x4 lanes peripherals (00:02.0 and 00:03.0) both of >>> >> You mean the i3100 here, right? >> >> > Yeah the EP80579 is a SOC ( System on chip ). It includes a IA32 core, > a North Bridge and a > South Bridge all on the same chip. In this respect talking about i3100 > is not very correct I believe. > It is clear they have a i3100 core there inside. it is just not named > in fact. The ep80579 has an > IMCH and a IICH. > > The northbridge and southbridge are connected by a NSI ( North-South > Interface ). This is in > fact a custom transparent PCIe implementation. So finally most of the > devices are on bus 0. > >>> them having a register 0x3E. If you set >>> ISAEN on 00:02.00 you have to set ISAEN on 00:03.00 as well. This is a >>> requirement provided by Intel in fact. >>> It makes sense as the address decoding is different as soon ISAEN is >>> set. All th bridges should be set correctly. >>> >>> These two peripherals can be coupled together providing x8 lanes. >>> >>> Note that ISAEN is not set by the legacy BIOS, and the VGA output is >>> working flawlessly. So in fact I just want >>> to write 0x8 instead 0xb in register 0x3E. But this I can already do, >>> just not at the correct place. >>> >> So where have you tried? File and function? >> >> It looks like if that's the bit you want to set you need to have your >> own >> enable_resources function in pciexp_porta.c. Right now you're using the >> default. >> >> > In auto.c ( mainboard\intel\truxton ) I've created a enable_vga() > function which only > pci_write_config(dev, 0x3e, 8). > > This function is called at the end of auto.c's main() after the > ram_fill/ram_verify. > > I agree, I need my own enable_resources function. This is the patch > I've tried to do. I've attached > the patch. In fact it is not called because I did not include it. I > did expect this file to be > correctly included as it is part of the initial port. > > As you can see I have added a printk in pcie_init and I do not see > that on the log. > >>> With the GFX card connected to SLOT0, the PCIe is operating in coupled >>> mode and actually configured as x8. >>> This is because the current coreboot port does not set PEACAPA.SIMP >>> to 1 >>> in both bridge. As soon both 00:02.0 >>> and 00:03.0 get PEACAPA.SIMP is set to 1, the two port are configured >>> in x4. We can see that in >>> PEALNKCAP.MLW. Checking legacy BIOS settings confirm PEACAPA.SIMP >>> should >>> be 1 in both PCIe >>> ports. >>> >> So this should probably be done even earlier. That's not something >> that is >> fixed, right? Or do you want it coupled (or not) depending on what card >> gets plugged in? >> >> > Actually for a very generic port we should come up with some config > options. About the truxton board, > We have an architecture like the following : > > PCIe PEA0 (4x) -> SLOT0 > PCIe PEA1 (4x) -> PCIe SWITCH -> SLOT1 (1x), SLOT2 (1x), SLOT3 (1x), > SLOT4 (1x) > > For a truxton BSP we should not have both ports coupled as a (8x), > Just imagine if you decide to have > a GFX card on slot 0 and a ethernet card on SLOT2, this is not going > to go very well. > > I think having some CONFIG option for this would be great. And I think > this should indeed happen > in pcie_init(). > > Actually, there a are a few other things like that which are not > important to describe so far I believe. > Verifying all the registers value takes time. lspci legacy vs coreboot > shows a lot of differences and > in this respect I am checking them one by one using the datasheet. So > it is likely some other things > will pop up. >>> I guess the only thing left is that coreboot does not allocate a hole >>> for the VGA, two holes are required I guess, >>> MEM and IO. how can I check if a hole is actually reserved or not? >>> >> Look through the last resource tree in the boot log. It should be >> there. >> >> You can always add them in read_resources. >> > > I have attached my last log. I believe we have the correct hole : > > PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 > flags e0004200 index 3 > PCI_DOMAIN: 0000 resource base c0000 size 1ff40000 align 0 gran 0 > limit 0 flags e0004200 index 4 > > We do not have anything between 0xa0000 and 0xc0000. These areas are > in fact VGAA, MDA and > VGAB. > > Anything else I should verify? > > Thank you, > > Arnaud * *

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coreboot August 2009