coreboot August 2009

coreboot@coreboot.org

61 participants
356 discussions

[v2] r4594 - in trunk/coreboot-v2: src/config src/include util/x86emu/include/x86emu util/x86emu/x86emu
by svn＠coreboot.org 27 Aug '09

27 Aug '09

Author: stepan Date: 2009-08-27 13:34:09 +0200 (Thu, 27 Aug 2009) New Revision: 4594 Removed: trunk/coreboot-v2/src/include/x86emu/ Modified: trunk/coreboot-v2/src/config/Config.lb trunk/coreboot-v2/util/x86emu/include/x86emu/x86emu.h trunk/coreboot-v2/util/x86emu/x86emu/Config.lb Log: coreboot was still using an old set (obsolete since yabel) of x86emu includes instead of the versions in util/x86emu. Clean up this mess. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/config/Config.lb =================================================================== --- trunk/coreboot-v2/src/config/Config.lb 2009-08-27 11:23:06 UTC (rev 4593) +++ trunk/coreboot-v2/src/config/Config.lb 2009-08-27 11:34:09 UTC (rev 4594) @@ -10,7 +10,7 @@ makedefine GCC_INC_DIR := $(shell LC_ALL=C $(GCC) -print-search-dirs | sed -ne "s/install: $.*$/\1include/gp") makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(CONFIG_ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS) -makedefine CFLAGS := $(CONFIG_CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer +makedefine CFLAGS = $(CONFIG_CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer if CONFIG_ASSEMBLER_DEBUG makedefine DEBUG_CFLAGS := -g -dA -fverbose-asm Modified: trunk/coreboot-v2/util/x86emu/include/x86emu/x86emu.h =================================================================== --- trunk/coreboot-v2/util/x86emu/include/x86emu/x86emu.h 2009-08-27 11:23:06 UTC (rev 4593) +++ trunk/coreboot-v2/util/x86emu/include/x86emu/x86emu.h 2009-08-27 11:34:09 UTC (rev 4594) @@ -42,10 +42,11 @@ #ifndef __X86EMU_X86EMU_H #define __X86EMU_X86EMU_H -/* FIXME: undefine printk for the moment */ -#if 1 /* Coreboot needs to map prinkf to printk. */ -#include <console.h> -#define printk(x...) printk(BIOS_DEBUG, x) +/* FIXME: redefine printk for the moment */ +#ifdef COREBOOT_V2 +#include <console/console.h> +#undef printk +#define printk(x...) do_printk(BIOS_DEBUG, x) #else #define printk printf #endif @@ -165,7 +166,7 @@ #ifdef CONFIG_DEBUG #define HALT_SYS() \ - printk("halt_sys: file %s, line %d\n", __FILE__, __LINE__); \ + printk("halt_sys: in %s\n", __func__); \ X86EMU_halt_sys(); #else #define HALT_SYS() X86EMU_halt_sys() Modified: trunk/coreboot-v2/util/x86emu/x86emu/Config.lb =================================================================== --- trunk/coreboot-v2/util/x86emu/x86emu/Config.lb 2009-08-27 11:23:06 UTC (rev 4593) +++ trunk/coreboot-v2/util/x86emu/x86emu/Config.lb 2009-08-27 11:34:09 UTC (rev 4594) @@ -1,3 +1,5 @@ +makedefine CPPFLAGS += -I$(TOP)/util/x86emu/include + object debug.o object decode.o object fpu.o

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[v2] r4593 - trunk/coreboot-v2/src/arch/i386/boot
by svn＠coreboot.org 27 Aug '09

27 Aug '09

Author: stepan Date: 2009-08-27 13:23:06 +0200 (Thu, 27 Aug 2009) New Revision: 4593 Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.h Log: Make all those locally used functions static instead of exporting them. (triv) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2009-08-27 07:42:45 UTC (rev 4592) +++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2009-08-27 11:23:06 UTC (rev 4593) @@ -1,5 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003-2004 Eric Biederman + * Copyright (C) 2005-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + #include <console/console.h> #include <ip_checksum.h> +#include <boot/tables.h> #include <boot/coreboot_tables.h> #include "coreboot_table.h" #include <string.h> @@ -7,7 +30,7 @@ #include <device/device.h> #include <stdlib.h> -struct lb_header *lb_table_init(unsigned long addr) +static struct lb_header *lb_table_init(unsigned long addr) { struct lb_header *header; @@ -28,27 +51,27 @@ return header; } -struct lb_record *lb_first_record(struct lb_header *header) +static struct lb_record *lb_first_record(struct lb_header *header) { struct lb_record *rec; rec = (void *)(((char *)header) + sizeof(*header)); return rec; } -struct lb_record *lb_last_record(struct lb_header *header) +static struct lb_record *lb_last_record(struct lb_header *header) { struct lb_record *rec; rec = (void *)(((char *)header) + sizeof(*header) + header->table_bytes); return rec; } -struct lb_record *lb_next_record(struct lb_record *rec) +static struct lb_record *lb_next_record(struct lb_record *rec) { rec = (void *)(((char *)rec) + rec->size); return rec; } -struct lb_record *lb_new_record(struct lb_header *header) +static struct lb_record *lb_new_record(struct lb_header *header) { struct lb_record *rec; rec = lb_last_record(header); @@ -63,7 +86,7 @@ } -struct lb_memory *lb_memory(struct lb_header *header) +static struct lb_memory *lb_memory(struct lb_header *header) { struct lb_record *rec; struct lb_memory *mem; @@ -74,7 +97,7 @@ return mem; } -struct lb_serial *lb_serial(struct lb_header *header) +static struct lb_serial *lb_serial(struct lb_header *header) { #if defined(CONFIG_TTYS0_BASE) struct lb_record *rec; @@ -91,7 +114,7 @@ #endif } -void add_console(struct lb_header *header, u16 consoletype) +static void add_console(struct lb_header *header, u16 consoletype) { struct lb_console *console; @@ -101,7 +124,7 @@ console->type = consoletype; } -void lb_console(struct lb_header *header) +static void lb_console(struct lb_header *header) { #ifdef CONFIG_CONSOLE_SERIAL8250 add_console(header, LB_TAG_CONSOLE_SERIAL8250); @@ -147,7 +170,7 @@ return mainboard; } -struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) +static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) { struct lb_record *rec; struct cmos_checksum *cmos_checksum; @@ -165,7 +188,7 @@ return cmos_checksum; } -void lb_strings(struct lb_header *header) +static void lb_strings(struct lb_header *header) { static const struct { uint32_t tag; @@ -195,7 +218,7 @@ } -struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header) +static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header) { struct lb_record *rec; struct lb_forward *forward; Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.h 2009-08-27 07:42:45 UTC (rev 4592) +++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.h 2009-08-27 11:23:06 UTC (rev 4593) @@ -8,12 +8,6 @@ unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end); -struct lb_header *lb_table_init(unsigned long addr); -struct lb_record *lb_first_record(struct lb_header *header); -struct lb_record *lb_last_record(struct lb_header *header); -struct lb_record *lb_next_record(struct lb_record *rec); -struct lb_record *lb_new_record(struct lb_header *header); -struct lb_memory *lb_memory(struct lb_header *header); void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size); struct lb_mainboard *lb_mainboard(struct lb_header *header);

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Seabios/Coreboot USB Keyboard support
by Arnaud Maye 27 Aug '09

27 Aug '09

Hello Gents, Just wanted to know if the the development moved since December 2008 around this. To proceed with something as simple as installing windows from CD one need to react about "Press any key to boot from cdrom". Thank you! Arnaud

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[v2] r4592 - in trunk/coreboot-v2/targets/via: epia-m700 pc2500e
by svn＠coreboot.org 27 Aug '09

27 Aug '09

Author: oxygene Date: 2009-08-27 09:42:45 +0200 (Thu, 27 Aug 2009) New Revision: 4592 Modified: trunk/coreboot-v2/targets/via/epia-m700/Config-abuild.lb trunk/coreboot-v2/targets/via/pc2500e/Config-abuild.lb Log: Rename "image" image to "fallback", so CBFS can find it. Thanks to Carl-Daniel for finding this. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/coreboot-v2/targets/via/epia-m700/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/via/epia-m700/Config-abuild.lb 2009-08-27 04:30:47 UTC (rev 4591) +++ trunk/coreboot-v2/targets/via/epia-m700/Config-abuild.lb 2009-08-27 07:42:45 UTC (rev 4592) @@ -28,9 +28,9 @@ __COMPRESSION__ __LOGLEVEL__ -romimage "image" +romimage "fallback" option COREBOOT_EXTRA_VERSION = "-epia-m700" payload __PAYLOAD__ end -buildrom ./coreboot.rom CONFIG_ROM_SIZE "image" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" Modified: trunk/coreboot-v2/targets/via/pc2500e/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/via/pc2500e/Config-abuild.lb 2009-08-27 04:30:47 UTC (rev 4591) +++ trunk/coreboot-v2/targets/via/pc2500e/Config-abuild.lb 2009-08-27 07:42:45 UTC (rev 4592) @@ -30,11 +30,11 @@ option CONFIG_ROM_SIZE = 512 * 1024 -romimage "image" +romimage "fallback" option CONFIG_USE_FALLBACK_IMAGE = 1 option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom CONFIG_ROM_SIZE "image" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

1 0

[PATCH] Fix SB600 SATA BAR printing
by Carl-Daniel Hailfinger 27 Aug '09

27 Aug '09

The new resource allocator made a bug in SB600 SATA BAR printing very visible (the SB600 code printed that two BARs had the same address). Mask the correct number of bits. Tested on Asus M2A-VM (AMD DBM690T target). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/sb600/sb600_sata.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/sb600/sb600_sata.c (Revision 4589) +++ LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/sb600/sb600_sata.c (Arbeitskopie) @@ -86,10 +86,10 @@ /* get base addresss */ sata_bar5 = (u8 *) (pci_read_config32(dev, 0x24) & ~0x3FF); sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; - sata_bar1 = pci_read_config16(dev, 0x14) & ~0x7; + sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3; sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7; - sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x7; - sata_bar4 = pci_read_config16(dev, 0x20) & ~0x7; + sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3; + sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf; printk_spew("sata_bar0=%x\n", sata_bar0); /* 3030 */ printk_spew("sata_bar1=%x\n", sata_bar1); /* 3070 */ -- http://www.hailfinger.org/

2 2

[v2] r4591 - trunk/coreboot-v2/src/southbridge/amd/sb600
by svn＠coreboot.org 27 Aug '09

27 Aug '09

Author: hailfinger Date: 2009-08-27 06:30:47 +0200 (Thu, 27 Aug 2009) New Revision: 4591 Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sata.c Log: The new resource allocator helped me find a bug in SB600 diagnostics. The SB600 SATA code printed that two BARs had the same address because it didn't mask the correct number of bits in the BAR. Functionality was not affected, but the debug output was incorrect. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sata.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sata.c 2009-08-27 02:47:35 UTC (rev 4590) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sata.c 2009-08-27 04:30:47 UTC (rev 4591) @@ -86,10 +86,10 @@ /* get base addresss */ sata_bar5 = (u8 *) (pci_read_config32(dev, 0x24) & ~0x3FF); sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; - sata_bar1 = pci_read_config16(dev, 0x14) & ~0x7; + sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3; sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7; - sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x7; - sata_bar4 = pci_read_config16(dev, 0x20) & ~0x7; + sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3; + sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf; printk_spew("sata_bar0=%x\n", sata_bar0); /* 3030 */ printk_spew("sata_bar1=%x\n", sata_bar1); /* 3070 */

1 0

AMD DBM690T and Pistachio work with CBFS
by Carl-Daniel Hailfinger 27 Aug '09

27 Aug '09

A binary search and some log reading revealed the exact issue with CBFS on AMD DBM690T and AMD Pistachio. The fallback image was called failover and due to that the CBFS code was unable to find the file fallback/coreboot_ram and jumped into the void. Thanks to Stefan for the fix (committed in r4589 and r4590). The underlying bug is CBFS code jumping to (void *)-1 when a file does not exist. Log follows: [...] CBFS: Could not find file fallback/coreboot_ram Jumping to image. INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- Issuing SOFT_RESET... Regards, Carl-Daniel -- http://www.hailfinger.org/

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[v2] r4590 - trunk/coreboot-v2/targets/amd/pistachio
by svn＠coreboot.org 27 Aug '09

27 Aug '09

Author: hailfinger Date: 2009-08-27 04:47:35 +0200 (Thu, 27 Aug 2009) New Revision: 4590 Modified: trunk/coreboot-v2/targets/amd/pistachio/Config-abuild.lb Log: amd/pistachio: fallback image must be called fallback. Thanks to Stefan for providing the original fix for amd/dbm690t Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/targets/amd/pistachio/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/amd/pistachio/Config-abuild.lb 2009-08-27 01:47:41 UTC (rev 4589) +++ trunk/coreboot-v2/targets/amd/pistachio/Config-abuild.lb 2009-08-27 02:47:35 UTC (rev 4590) @@ -19,12 +19,12 @@ payload __PAYLOAD__ end -romimage "failover" +romimage "fallback" option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_ROM_IMAGE_SIZE=0x20000 option CONFIG_XIP_ROM_SIZE=0x20000 - option COREBOOT_EXTRA_VERSION=".0-failover" + option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

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[v2] r4589 - trunk/coreboot-v2/targets/amd/dbm690t
by svn＠coreboot.org 27 Aug '09

27 Aug '09

Author: stepan Date: 2009-08-27 03:47:41 +0200 (Thu, 27 Aug 2009) New Revision: 4589 Modified: trunk/coreboot-v2/targets/amd/dbm690t/Config-abuild.lb Log: fallback image must be called fallback. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/targets/amd/dbm690t/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/amd/dbm690t/Config-abuild.lb 2009-08-26 18:14:30 UTC (rev 4588) +++ trunk/coreboot-v2/targets/amd/dbm690t/Config-abuild.lb 2009-08-27 01:47:41 UTC (rev 4589) @@ -19,12 +19,12 @@ payload __PAYLOAD__ end -romimage "failover" +romimage "fallback" option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_ROM_IMAGE_SIZE=0x20000 option CONFIG_XIP_ROM_SIZE=0x20000 - option COREBOOT_EXTRA_VERSION=".0-failover" + option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

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[v2] r4588 - in trunk/coreboot-v2/src: drivers/i2c/adm1026 northbridge/amd/amdfam10 northbridge/ibm/cpc710 southbridge/amd/sb600
by svn＠coreboot.org 26 Aug '09

26 Aug '09

Author: oxygene Date: 2009-08-26 20:14:30 +0200 (Wed, 26 Aug 2009) New Revision: 4588 Modified: trunk/coreboot-v2/src/drivers/i2c/adm1026/adm1026.c trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_acpi.c trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_pci.c trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_pci.h trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c Log: Remove a couple of CONFIG_ prefixes that shouldn't have happened. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/drivers/i2c/adm1026/adm1026.c =================================================================== --- trunk/coreboot-v2/src/drivers/i2c/adm1026/adm1026.c 2009-08-26 17:10:00 UTC (rev 4587) +++ trunk/coreboot-v2/src/drivers/i2c/adm1026/adm1026.c 2009-08-26 18:14:30 UTC (rev 4588) @@ -17,7 +17,7 @@ #define CFG1_THERM_HOT 0x10 #define CFT1_DAC_AFC 0x20 #define CFG1_PWM_AFC 0x40 -#define CFG1CONFIG_RESET 0x80 +#define CFG1_RESET 0x80 #define ADM1026_REG_CONFIG2 0x01 #define ADM1026_REG_CONFIG3 0x07 @@ -40,7 +40,7 @@ int result; result = smbus_read_byte(dev, ADM1026_REG_CONFIG1); - result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1CONFIG_RESET); + result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1_RESET); result = smbus_write_byte(dev, ADM1026_REG_CONFIG1, result); result = smbus_read_byte(dev, ADM1026_REG_CONFIG1); Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_acpi.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_acpi.c 2009-08-26 17:10:00 UTC (rev 4587) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_acpi.c 2009-08-26 18:14:30 UTC (rev 4588) @@ -190,7 +190,7 @@ u8 *CBST; u8 *CBBX; u8 *CBS2; - u8 *CONFIG_CBB2; + u8 *CBB2; int i; @@ -208,7 +208,7 @@ HCDN = ssdt+0x57a; //+5 will be next HCDN CBBX = ssdt+0x61f; // CBST = ssdt+0x626; - CONFIG_CBB2 = ssdt+0x62d; // + CBB2 = ssdt+0x62d; // CBS2 = ssdt+0x634; for(i=0;i<HC_NUMS;i++) { @@ -260,10 +260,10 @@ if((CONFIG_CBB == 0xff) && (sysconf.nodes>32)) { *CBS2 = 0x0f; - *CONFIG_CBB2 = (u8)(CONFIG_CBB-1); + *CBB2 = (u8)(CONFIG_CBB-1); } else { *CBS2 = 0x00; - *CONFIG_CBB2 = 0x00; + *CBB2 = 0x00; } } Modified: trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_pci.c =================================================================== --- trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_pci.c 2009-08-26 17:10:00 UTC (rev 4587) +++ trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_pci.c 2009-08-26 18:14:30 UTC (rev 4588) @@ -45,7 +45,7 @@ setCPC710_PCI32(CPC710_PCIL0_MSIZE, CPC710_PCI32_MEM_SIZE); setCPC710_PCI32(CPC710_PCIL0_IOSIZE, CPC710_PCI32_IO_SIZE); setCPC710_PCI32(CPC710_PCIL0_SMBAR, CPC710_PCI32_MEM_BASE); - setCPC710_PCI32(CPC710_PCIL0_SIBAR, CPC710_PCI32CONFIG_IO_BASE); + setCPC710_PCI32(CPC710_PCIL0_SIBAR, CPC710_PCI32_IO_BASE); setCPC710_PCI32(CPC710_PCIL0_CTLRW, 0x00000000); setCPC710_PCI32(CPC710_PCIL0_PSSIZE, 0x00000080); setCPC710_PCI32(CPC710_PCIL0_BARPS, 0x00000000); @@ -94,7 +94,7 @@ setCPC710_PCI64(CPC710_PCIL0_MSIZE, CPC710_PCI64_MEM_SIZE); setCPC710_PCI64(CPC710_PCIL0_IOSIZE, CPC710_PCI64_IO_SIZE); setCPC710_PCI64(CPC710_PCIL0_SMBAR, CPC710_PCI64_MEM_BASE); - setCPC710_PCI64(CPC710_PCIL0_SIBAR, CPC710_PCI64CONFIG_IO_BASE); + setCPC710_PCI64(CPC710_PCIL0_SIBAR, CPC710_PCI64_IO_BASE); setCPC710_PCI64(CPC710_PCIL0_CTLRW, 0x02000000); setCPC710_PCI64(CPC710_PCIL0_PSSIZE, 0x00000080); Modified: trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_pci.h =================================================================== --- trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_pci.h 2009-08-26 17:10:00 UTC (rev 4587) +++ trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_pci.h 2009-08-26 18:14:30 UTC (rev 4588) @@ -28,13 +28,13 @@ #define CPC710_PCI32_MEM_SIZE 0xf8000000 #define CPC710_PCI32_MEM_BASE 0xc0000000 #define CPC710_PCI32_IO_SIZE 0xf8000000 -#define CPC710_PCI32CONFIG_IO_BASE 0x80000000 +#define CPC710_PCI32_IO_BASE 0x80000000 //#define CPC710_PCI64_CONFIG 0xff400000 //#define CPC710_PCI64_MEM_SIZE 0xf8000000 //#define CPC710_PCI64_MEM_BASE 0xc8000000 //#define CPC710_PCI64_IO_SIZE 0xf8000000 -//#define CPC710_PCI64CONFIG_IO_BASE 0x88000000 +//#define CPC710_PCI64_IO_BASE 0x88000000 #define CPC710_PCIL0_PSEA 0xf6110 #define CPC710_PCIL0_PCIDG 0xf6120 Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c 2009-08-26 17:10:00 UTC (rev 4587) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c 2009-08-26 18:14:30 UTC (rev 4588) @@ -430,7 +430,7 @@ /*CIM set this register; but I didn't find its description in RPR. On DBM690T platform, I didn't find different between set and skip this register. - But on Filbert platform, the CONFIG_DEBUG message from serial port on Peanut board can't be displayed + But on Filbert platform, the DEBUG message from serial port on Peanut board can't be displayed after the bit0 of this register is set. pci_write_config8(dev, 0x04, 0x21); */

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coreboot August 2009