coreboot July 2009

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75 participants
304 discussions

Re: [coreboot] IOAPIC Initialisation - How much do you have to do ??
by Rudolf Marek 27 Jul '09

27 Jul '09

Harrison, Jon (SELEX GALILEO, UK) napsal(a): > Sooo. I've added MPtables and masked IRQ0 from boot but still get > > APIC error on CPU0: 40(40) Hi, seems like I'm bit online ;) Check if bit 7 on 48h 7 APIC FSB Fixed at Low DW It changes how the APIC is delivered. Also if external bus is used, you will need to check the pin multiplexer/multifunction is setup correctly. > Is there a kernel command line option that will turn on more verbose > APIC output ? Yes but not help apic=debug maybe Rudolf

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cbfstool issues?
by Cristi Magherusan 26 Jul '09

26 Jul '09

Hello, I'm trying to get qemu in good shape with latest coreboot-v2 revisions, but I'm facing an issue with cbfstool. It seems the "l" parameter (LZMA compression) doesn't work anymore. I need it for using LZMA-compressed LAB images in AVATT. Is there anything that I can do about it? Thanks, Cristi -- Ing. Cristi Măgherușan, System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247

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[Fwd: Re: lots of compilation failures in abuild on x86-64]
by Cristi Magherusan 26 Jul '09

26 Jul '09

-------- Forwarded Message -------- From: Ivan Barrera A. <info(a)Ivn.cl> To: Cristi Magherusan <Cristi.Magherusan(a)net.utcluj.ro> Subject: Re: [coreboot] lots of compilation failures in abuild on x86-64 Date: Sun, 26 Jul 2009 23:14:29 -0400 >>> The fix is pretty simple, but I have no idea if it's acceptable: >>> Use gcc-multilib, and add -lgcc to the LDFLAGS for all the broken >>> targets. >>> >>> I will provide soon a log with all the broken boards. >> Hi.. >> Which distro of linux are you using ? >> I work only with x86_64, and never had any issues... Perhaps some bad >> env settings ? > Hello, > > Yeah, my bad! > > I'm using 64bit Ubuntu 9.04, and I hadn't installed gcc-multilib when I > started building. > I installed it while compilation was ongoing but most of the remaining > targets still failed to build and I tried to find a solution. The weird > thing is that some compiled fine even before installing gcc-multilib. > > After I saw your message I restarted the build it all went fine. It must > have been something in gcc's, no idea. > > Thanks for your feedback! :) No problem. And i just saw that i answered to your email directly instead of the list... so add the follow up for all to know :D Thanks for sharing > Cristi > -- Ing. Cristi Măgherușan, System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247

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lots of compilation failures in abuild on x86-64
by Cristi Magherusan 26 Jul '09

26 Jul '09

Hello, I tried to run abuild on my x86-64 box and I got compilation errors like the following, for almost all the targets: Compiling image on 1 cpu .. FAILED after 17s! Log excerpt: (.text+0x101db): undefined reference to `__divdi3' The fix is pretty simple, but I have no idea if it's acceptable: Use gcc-multilib, and add -lgcc to the LDFLAGS for all the broken targets. I will provide soon a log with all the broken boards. Regards, Cristi -- Ing. Cristi Măgherușan, System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247

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i945: raminit.c
by Urbez Santana Roma 26 Jul '09

26 Jul '09

in file: coreboot-v2/src/northbridge/intel/i945/raminit.c in the function: static int sdram_capabilities_dual_channel(void) { u32 reg32; reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4); reg32 >>= 24; reg32 &= 1; return (!reg32); } The pci_read_config8 must be pci_read_config32 to read the bit 56 of CAPID0? . Another question. If the chipset FSB supports 667MHz and chipset only supports DDR2-533 if one DDR2 667MHz or 800Mhz are connected, then FSB can one set FSB to maximum 667?

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[v2] r4468 - trunk/coreboot-v2/util/cbfstool
by svn＠coreboot.org 26 Jul '09

26 Jul '09

Author: stepan Date: 2009-07-26 17:11:53 +0200 (Sun, 26 Jul 2009) New Revision: 4468 Modified: trunk/coreboot-v2/util/cbfstool/add.c Log: drop dead nested assignment (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/util/cbfstool/add.c =================================================================== --- trunk/coreboot-v2/util/cbfstool/add.c 2009-07-26 15:05:40 UTC (rev 4467) +++ trunk/coreboot-v2/util/cbfstool/add.c 2009-07-26 15:11:53 UTC (rev 4468) @@ -254,14 +254,12 @@ return -1; } - int component_type; - /* There are two ways to specify the type - a string or a number */ if (isdigit(*(argv[2]))) type = strtoul(argv[2], 0, 0); else { - switch( component_type = select_component_type(argv[2])) { + switch(select_component_type(argv[2])) { case 0: type = CBFS_COMPONENT_STAGE; break;

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[v2] r4467 - trunk/coreboot-v2/src/console
by svn＠coreboot.org 26 Jul '09

26 Jul '09

Author: stepan Date: 2009-07-26 17:05:40 +0200 (Sun, 26 Jul 2009) New Revision: 4467 Modified: trunk/coreboot-v2/src/console/vsprintf.c Log: trivial typo in a comment Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/console/vsprintf.c =================================================================== --- trunk/coreboot-v2/src/console/vsprintf.c 2009-07-23 22:03:14 UTC (rev 4466) +++ trunk/coreboot-v2/src/console/vsprintf.c 2009-07-26 15:05:40 UTC (rev 4467) @@ -17,7 +17,7 @@ { char *str_buf; - /* this function is only used by vsprint. + /* this function is only used by vsprintf. To keep str_buf local (for reentrancy and to avoid .bss use, nest it */ void str_tx_byte(unsigned char byte)

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fam10/h8dmr: extreme slowness in CBFS memset / memcpy
by Ward Vandewege 24 Jul '09

24 Jul '09

Hi all, I'm working on a fam10 tree for supermicro h8dmr. I'm using CBFS. It boots, but I'm struggling with some extreme slowness during boot. In particular, the memset function in src/lib/memset.c takes *minutes* to clear 1.2MB of ram. A little further CBFS does a memcpy which takes another 20 or 30 seconds: Stage: load fallback/coreboot_ram @ 2097152/1245184 bytes, enter @ 200000 ....LOOOOOONG pause.... Stage: after memset on-stack variables at 00ffbec8 and 00ffbed4 cbfs_decompress: algo: 0 cbfs_decompress: uncompressed ....another lengthy pause.... cbfs_decompress: memcpy from 0xffbecc to 0xffbed0 for 0x2d304 bytes done Stage: done loading. The first, lengthly pause is new; it is apparently caused by something introduced between r4368 and r4440. The second pause was there already in r4368. I understand this may have something to do with MTRRs - looking at the logs it seems MTRRs are not set up until well after CBFS has dealt with coreboot_ram. This box has 32GB of ram, in case that makes a difference. Any suggestions? Thanks, Ward. -- Ward Vandewege <ward(a)gnu.org>

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Re: [coreboot] IOAPIC Initialisation - How much do you have to do ??
by Harrison, Jon (SELEX GALILEO, UK) 24 Jul '09

24 Jul '09

Sooo. I've added MPtables and masked IRQ0 from boot but still get APIC error on CPU0: 40(40) "" "" "" "" Which seems to mean "illegal vector recieved" Any suggestions on how to track down what the interrupt source is of the illegal vector ? Is there a kernel command line option that will turn on more verbose APIC output ? Thanks, Jon > ------------------------------ > > Message: 5 > Date: Fri, 24 Jul 2009 10:04:29 +0100 > From: "Harrison, Jon (SELEX GALILEO, UK)" > <jon.harrison(a)selexgalileo.com> > To: "Rudolf Marek" <r.marek(a)assembler.cz> > Cc: coreboot(a)coreboot.org > Subject: Re: [coreboot] IOAPIC Initialisation - How much do you have > to do ?? > Message-ID: > > <8E520A5E7FB8D647BFDA039F6031C1C6059D59EC(a)desmdswms201.des.grplnk.net> > Content-Type: text/plain; charset="us-ascii" > > Ahh Haa !! > > Finally, I have managed to get the IRQs through to the processor. > > Proper setup for APIC Serial Bus delivery. > > Now I get an smp_error_interrupt during kernel init, with a "received > illegal vector" status. > > I'll call this progress though. > > Guessing that either in Serial Bus mode the IRQs should be > disabled from > boot (Current VT8237R IOAPIC init emables IRQ 0 from boot, > but is in FSB > mode...) until the kernel has time to sort out IRQ vectors or there is > something else missing (perhaps in the MP tables to allow > things to get > setup properly ?) > > Jon > SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England & Wales. Company no. 02426132 ******************************************************************** This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. ********************************************************************

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Re: [coreboot] IOAPIC Initialisation - How much do you have to do ??
by Rudolf Marek 24 Jul '09

24 Jul '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, I will leave for a holiday today. Its difficult to answer that without the patch at hand. The ..TIMER: vector=0x31 apic1=0 pin1=2 apic2=-1 pin2=-1 ..MP-BIOS bug: 8254 timer not connected to IO-APIC Means that: ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) For some reason this is wrong. You have same line in the orig bios? If yes there is still smth wrong with APIC. Please check: Assigned: PCI: 00:10.4 10 * [0xfebffd00 - 0xfebffdff] mem Assigned: PCI: 00:10.5 10 * [0xfebffe00 - 0xfebffeff] mem Assigned: PCI: 00:12.0 14 * [0xfebfff00 - 0xfebfffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fec00000 size: 300 align: 8 gran: 0 done This looks like the mem resources are setup from too high overlaping the IOAPIC with some hardware. No good. Move all resource bases bellow f0000000. You will need to adjust the northbridge.c and put the PCI resource limit to the address above most likely. Others can help here. Also it seems that you created something in half: ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 6 7 *10 11 12) ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 6 7 10 *11 12) ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 6 7 10 11 *12) ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 6 7 10 *11 12), disabled. ACPI: PCI Interrupt Link [ATAI] (IRQs *20) ACPI: PCI Interrupt Link [USBI] (IRQs *21) ACPI: PCI Interrupt Link [VT8I] (IRQs *22) ACPI: PCI Interrupt Link [NICI] (IRQs *23) This means you route half of IRQs through APIC and second half through the 8259. Why not route all of them through APIC. Check M2V-MX se board _PRT methods. INTA# to IRQ16 INTB# to IRQ17 INTC# to IRQ18 INTD# to IRQ19 uhci_hcd 0000:00:10.0: Unlink after no-IRQ? Controller is probably using the wrong IRQ. <<---- Whoops !! Yes maybe but I think all USBs are routed to IRQ21 so it must be smth else. Like the resource conflict I mentioned above. If VT8237R apic is enabled (and it is) this is routed like this: IDE (Native Mode)/SATA IRQ & INTE to IRQ20 USB IRQ (all 5 functions) and INTF to IRQ21 AC'97 / MC'97 IRQ and INTG to IRQ22 LAN IRQ and INTH to IRQ23 So I would recommend to boot now with init=/bin/bash and provide cat /proc/iomem cat /proc/interrupts lspci -vvvxxx I'm going to be most likely AFK for a week so hopefully others can try to help. Most likely is the resource conflict in game. Also check if the APIC messages should be routed by extra bus or as part of FSB messages (there is some bit for that on 0xfec000smth) I think FSB routing is fine for VIA CPU too but not sure. rest looks OK to me. Please provide the WIP patch next time so one can see how you set things up. Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkpoijwACgkQ3J9wPJqZRNUqUACgqTxXlnbgyQa2jrFkwrECogh8 iKAAn2TtACws0090J7KhBbC3fSE1Nprc =eOhh -----END PGP SIGNATURE-----

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coreboot July 2009