coreboot July 2009

coreboot@coreboot.org

75 participants
304 discussions

[PATCH] Fix AMD 690 HIGH_TABLES
by Carl-Daniel Hailfinger 15 Oct '09

15 Oct '09

Zheng, can you please test this with HIGH_TABLES enabled (and a new FILO)? A full log would be appreciated. Thanks. This hopefully will fix AMD 690 HIGH_TABLES or at least give me an insight into why HIGH_TABLES fails. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c (Revision 4339) +++ LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c (Arbeitskopie) @@ -896,6 +896,7 @@ #if HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; +extern uint64_t uma_memory_base, uma_memory_size; #endif static void pci_domain_set_resources(device_t dev) @@ -1066,7 +1067,9 @@ } -// printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu + printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); + if ((uma_memory_base >> 10) < mmio_basek) + printk_alert("node %d: UMA memory starts below mmio_basek\n", i); /* See if I need to split the region to accomodate pci memory space */ if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { @@ -1080,7 +1083,7 @@ #if HAVE_HIGH_TABLES==1 if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = ((uma_memory_base >> 10) - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE, high_tables_base); @@ -1105,6 +1108,9 @@ sizek -= (4*1024*1024 - mmio_basek); } } + + printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); + /* If sizek == 0, it was split at mmio_basek without a hole. * Don't create an empty ram_resource. */ @@ -1116,7 +1122,7 @@ i, mmio_basek, basek, limitk); if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = ((uma_memory_base >> 10) - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; } #endif -- http://www.hailfinger.org/ Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c (Revision 4339) +++ LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c (Arbeitskopie) @@ -896,6 +896,7 @@ #if HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; +extern uint64_t uma_memory_base, uma_memory_size; #endif static void pci_domain_set_resources(device_t dev) @@ -1066,7 +1067,9 @@ } -// printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu + printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); + if ((uma_memory_base >> 10) < mmio_basek) + printk_alert("node %d: UMA memory starts below mmio_basek\n", i); /* See if I need to split the region to accomodate pci memory space */ if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { @@ -1080,7 +1083,7 @@ #if HAVE_HIGH_TABLES==1 if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = ((uma_memory_base >> 10) - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE, high_tables_base); @@ -1105,6 +1108,9 @@ sizek -= (4*1024*1024 - mmio_basek); } } + + printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); + /* If sizek == 0, it was split at mmio_basek without a hole. * Don't create an empty ram_resource. */ @@ -1116,7 +1122,7 @@ i, mmio_basek, basek, limitk); if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = ((uma_memory_base >> 10) - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; } #endif

3 6

flashrom on MCP73
by Fabrício Ceolin 08 Oct '09

08 Oct '09

Hi guys, We are trying to make flashrom work on http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=858&… Chipset MCP73 / SIP chipset Macronix MX25L8005. We made modifications using a enable_flash_mcp55 function, but does't work. ./flashrom -V -c MX25L8005 -r -f rom Calibrating delay loop... 627M loops per second, 100 myus = 199 us. OK. No coreboot table found. Found chipset "NVIDIA MCP73", enabling flash write... OK. Probing for Macronix MX25L8005, 1024 KB: spi_command called, but no SPI chipset/strapping detected No EEPROM/flash device found. Force read (-f -r -c) requested, forcing chip probe success: Probing for Macronix MX25L8005, 1024 KB: Found chip "Macronix MX25L8005" (1024 KB) at physical address 0xfff00000. Force reading flash... spi_chip_read called, but no SPI chipset/strapping detected 0 done. How can I do works? Are there any hints? Thanks! -- Fabrício Ceolin

3 4

[flashrom] [PATCH] SST SST49LF003A/B should be marked as TEST_OK_PR
by Peter Lemenkov 25 Sep '09

25 Sep '09

Hello All! I reported earlier, that I successfully extracted BIOS image from SST49LF003A/B, but cannot verify it yet. Nowadays, using wonderful bios_extract utility, I can provide confirmation, that everything was extracted correctly. Here is the simple patch. Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- Here are logs of extraction of BIOS from chip, and extraction of various BLOBs from BIOS image: [petro@Workplace tmp]$ sudo ~/work/flashrom/flashrom -r bios.bin flashrom v0.9.0-runknown No coreboot table found. Found chipset "Intel ICH6/ICH6R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF003A/B" (384 KB, FWH) at physical address 0xfffa0000. === This flash part has status UNTESTED for operations: READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard you tested. Thanks for your help! === Reading flash... done. [petro@Workplace tmp]$ ~/work/bios_extract/bios_extract bios.bin Using file "bios.bin" (384kB) Found Award BIOS. 0x00000 ( 79260 bytes) -> 8i9me.BIN (131072 bytes) 0x1359E ( 40539 bytes) -> awardext.rom ( 57600 bytes) 0x1D3FA ( 5375 bytes) -> ACPITBL.BIN ( 14956 bytes) 0x1E8FA ( 681 bytes) -> AwardBmp.bmp ( 5772 bytes) 0x1EBA4 ( 19354 bytes) -> awardeyt.rom ( 28336 bytes) 0x2373F ( 8997 bytes) -> _EN_CODE.BIN ( 22064 bytes) 0x25A65 ( 28551 bytes) -> GSDALE.VGA ( 65536 bytes) 0x2C9ED ( 747 bytes) -> GSDALE.VBT ( 1632 bytes) 0x2CCD9 ( 30268 bytes) -> RTGBROM.LOM ( 49152 bytes) 0x34316 ( 32167 bytes) -> rtk_pxe.211 ( 53248 bytes) 0x3C0BE ( 2774 bytes) -> PPMINIT.ROM ( 6365 bytes) 0x3CB95 ( 12899 bytes) -> FINER.BIN ( 28102 bytes) 0x3FDF9 ( 6020 bytes) -> SBF.BIN ( 7974 bytes) [petro@Workplace tmp]$ -- With best regards!

2 1

#121: flashrom runtime error
by coreboot 29 Aug '09

29 Aug '09

#121: flashrom runtime error ---------------------------------+------------------------------------------ Reporter: lymanrb@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ I got such errors when running flashrom. {{{ Calibrating delay loop... OK. Can't mmap memory using /dev/mem: Invalid argument }}} My env {{{ Linux xxx 2.6.28-ARCH #1 SMP PREEMPT Sun Jan 18 19:41:52 UTC 2009 x86_64 Intel(R) Core(TM)2 Duo CPU T7250 @ 2.00GHz GenuineIntel GNU/Linux core/pciutils 3.0.3-1 [installed] (base) PCI bus configuration space access library and tools core/zlib 1.2.3.3-3 [installed] (base) A compression/decompression Library $ ./flashrom -R flashrom r3869 }}} -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/121> coreboot <http://www.coreboot.org/>

5 10

[patch] [AMD Fam10] Fix confused RB-C2 and DA-C2
by Bao, Zheng 24 Aug '09

24 Aug '09

This patch is about the DA-C2 and RB-C2. Chip with install processor Revision ID of 0x100F62 is DA-C2, instead of RB-C2 which was incorrectly defined in raminit_amdmct.c. RB-C2's ID is 0x100F42. The Erratas applied to them are almost the same. Issues: 1. I really dont know what their nicknames are (Shanghai C2 or something). 2. About the mc_patch_01000086.h, I dont know if it is allowed to be released. If you really need it, please contact AMD Inc to see if it is public. 3. I haven't made coreboot go thoroughly on this RB-C2. This patch is just half tested. I am not confident it is 100% correct. Zheng Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/cpu/amd/model_10xxx/update_microcode.c =================================================================== --- src/cpu/amd/model_10xxx/update_microcode.c (revision 4426) +++ src/cpu/amd/model_10xxx/update_microcode.c (working copy) @@ -44,6 +44,7 @@ * 00100F2Ah (DR-BA) 1020h 01000096h * 00100F22h (DR-B2) 1022h 01000095h * 00100F23h (DR-B3) 1022h 01000095h + * 00100F42h (RB-C2) 1041h 01000086h * 00100F62h (DA-C2) 1062h 0100009Fh */ @@ -67,6 +68,7 @@ 0x100f2A, 0x1020, 0x100f22, 0x1022, 0x100f23, 0x1022, + 0x100f42, 0x1041, 0x100f62, 0x1062, }; Index: src/cpu/amd/model_10xxx/defaults.h =================================================================== --- src/cpu/amd/model_10xxx/defaults.h (revision 4426) +++ src/cpu/amd/model_10xxx/defaults.h (working copy) @@ -290,7 +290,7 @@ /* errata 346 - Fam10 C2 * System software should set F3x188[22] to 1b. */ - { 3, 0x188, AMD_RB_C2, AMD_PTYPE_ALL, + { 3, 0x188, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, 0x00400000, 0x00400000 }, /* L3 Control Register */ @@ -317,82 +317,82 @@ /* Errata 344 - Fam10 C2 * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */ - { 0x60, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x60, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x61, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x61, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x62, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x62, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x63, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x63, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x64, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x64, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x65, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x65, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x66, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x66, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x67, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x67, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x68, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x68, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x70, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x70, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x71, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x71, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x72, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x72, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x73, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x73, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x74, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x74, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x75, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x75, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x76, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x76, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x77, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x77, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x78, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x78, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, /* Errata 354 - Fam10 C2 * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */ - { 0x40, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x40, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x41, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x41, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x42, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x42, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x43, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x43, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x44, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x44, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x45, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x45, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x46, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x46, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x47, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x47, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x48, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x48, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x50, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x50, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x51, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x51, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x52, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x52, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x53, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x53, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x54, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x54, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x55, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x55, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x56, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x56, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x57, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x57, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x58, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x58, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, /* Errata 327 - Fam10 C2 @@ -400,15 +400,15 @@ * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and * Link Phy Impedance Register[RttIndex] * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */ - { 0xC0, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0xC0, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x40040000, 0xe01F0000 }, - { 0xD0, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0xD0, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x40040000, 0xe01F0000 }, - { 0x520A, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x520A, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */ - { 0x530A, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x530A, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */ { 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, Index: src/northbridge/amd/amdmct/wrappers/mcti_d.c =================================================================== --- src/northbridge/amd/amdmct/wrappers/mcti_d.c (revision 4426) +++ src/northbridge/amd/amdmct/wrappers/mcti_d.c (working copy) @@ -394,7 +394,7 @@ void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { - if (pDCTstatA->LogicalCPUID & AMD_RB_C2) { + if (pDCTstatA->LogicalCPUID & (AMD_RB_C2 | AMD_DA_C2)) { vErrata350(pMCTstat, pDCTstatA); } } Index: src/northbridge/amd/amdmct/amddefs.h =================================================================== --- src/northbridge/amd/amdmct/amddefs.h (revision 4426) +++ src/northbridge/amd/amdmct/amddefs.h (working copy) @@ -41,6 +41,7 @@ #define AMD_DR_BA 0x00400000 /* Barcelona BA */ #define AMD_DR_B3 0x00800000 /* Barcelona B3 */ #define AMD_RB_C2 0x01000000 /* Shanghai C2 */ +#define AMD_DA_C2 0x02000000 /* XXXX C2 */ /* * Groups - Create as many as you wish, from the above public values Index: src/northbridge/amd/amdfam10/raminit_amdmct.c =================================================================== --- src/northbridge/amd/amdfam10/raminit_amdmct.c (revision 4426) +++ src/northbridge/amd/amdfam10/raminit_amdmct.c (working copy) @@ -149,9 +149,12 @@ case 0x10023: ret = AMD_DR_B3; break; - case 0x10062: + case 0x10042: ret = AMD_RB_C2; break; + case 0x10062: + ret = AMD_DA_C2; + break; default: /* FIXME: mabe we should die() here. */ print_err("FIXME! CPU Version unknown or not supported! \n"); <<amd_fam10_RBC2_DAC2_fix.patch>>

4 14

Re: [coreboot] vga not working
by Kevin O'Connor 20 Aug '09

20 Aug '09

On Sun, Jul 26, 2009 at 01:00:52PM +0200, Arnaud Maye wrote: > I've been on IRC for a GFX output issue on Friday. Actually the > output is always black or full of non sense square on the screen. I > have tried two graphic cards and in this respect it is fair to point > the issue outside of the vgarom. [...] > Scan for VGA option rom > Attempting to init PCI bdf 07:00.0 (dev/ven 42110de) > Searching CBFS for data file pci10de,0421.rom > Found CBFS file fallback/payload > Found CBFS file fallback/coreboot_ram > Found CBFS file pci10de,0421.rom > Copying data 58368@0xffe17a98 to 196608@0x000c0000 > Checking rom 0x000c0000 (sig aa55 size 114) > Running option rom at c000:0003 How did you obtain the vgabios? Is this a vga adapter built-in to the motherboard, or one on an external card? For vga adapters on external cards, one should not add the vgabios to CBFS - SeaBIOS can extract the vgabios directly from the card. -Kevin

4 27

Problem jumping to Boot Loader
by Jeffrey C. Jacobs 07 Aug '09

07 Aug '09

Hello again, Now that I've got my BIOS booting properly AFAICT, I am running into a problem when I jump to my Boot Loader. I get to the adjusted_boot_notes line, and then my Boot Loader is started, but it gets a memory map error that I don't understand and fails to load my menu.lst. This Boot Loader (FILO ver 0.5) works with an older version of CoreBoot (specifically a version from when it was called LinuxBIOS) but in my current build does not seem to work. You can see my full boot sequence at http://coreboot.pastebin.com/f4ebea109 -- the relevant lines start at line 1006: FILO version 0.5 (me(a)mymachine.com) Wed Jul 15 13:14:58 EDT 2009 Can't get memory map from firmware. Using hardcoded default. Press <Enter> for default menu.lst (hda1:/filo/menu.lst), or <Esc> for prompt... 2 1 timed out menu: hda1:/filo/menu.lst Detected floating bus No drive detected on IDE channel 0 A proper boot should look like this: FILO version 0.5 (me(a)mymachine.com) Sun Oct 19 14:32:35 EDT 2008 Press <Enter> for default menu.lst (hda1:/filo/menu.lst), or <Esc> for prompt... 2 1 timed out menu: hda1:/filo/menu.lst hda: LBA48 40GB: IC25N040ATMR04-0 hdb: ATAPI: MATSHITACD-RW CW-8124 Mounted ext2fs Has anyone experienced this before? Any ideas how to get FILO to recognize the mounted hardware? I'm guessing it's something I missed in my CoreBoot modifications since it clearly works in the older version. Thanks in advance, Jeffrey.

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Re: [coreboot] ASUS KFN4D16 - K8 FAM10
by thomas ward 06 Aug '09

06 Aug '09

Thanks Myles! Your reply is very helpfull to me (especailly the part about using v2 - I was unsure which of v2 or v3 was appropriate) and very clear. I will follow the "destructions" (probably not till August becasue busy in June and holiday most of July) and once I have blown up the board will post the results to this list. regards, Tom. --- On Wed, 17/6/09, Myles Watson <mylesgw(a)gmail.com> wrote: > From: Myles Watson <mylesgw(a)gmail.com> > Subject: Re: [coreboot] ASUS KFN4D16 - K8 FAM10 > To: "Thomas Ward" <tomwardathome(a)yahoo.co.uk> > Cc: "coreboot(a)coreboot.org" <coreboot(a)coreboot.org> > Date: Wednesday, 17 June, 2009, 5:13 PM > > > On Tue, Jun 16, 2009 at 3:36 AM, > Thomas Ward <tomwardathome(a)yahoo.co.uk> > wrote: > > Hello, > > I realise your list is very technical and this is probably > a daft set of question so please forgive me if it is > cluttering up your list but I couldn't find a more > appropriate place to ask,.. > > ... so here goes. > > > > My questions are about running coreboot on an ASUS KFN4-D16 > with an NVIDIA CK804 chipset and a SST SST49LF080A (BIOS?) > chip 33-4C-NHE 0631138-B > > I have 2 cpus one is a 65nm dual core opteron 2210, the > second CPU is a quad core 45nm "Shanghai" opteron > 2376 - this CPU isn't supported by the ASUS BIOS. > > My aim is to get the board to boot with the quad core CPU, > I would be happy if it boots with support for all the RAM > and at least one of the ethernet ports, I can live without > PCI, SATA, USB etc.They should all work. > > > > My plan is to use a BIOS saviour and buy a second > SST49LF080A chip and then > > > > 1. flash coreboot for K8 (?) with flashrom to verify that > coreboot works on this board > > 2. flash coreboot for fam10 (?) with flashrom > > > > does this sound like a good plan?Yes. > > > I have a couple of other questions > > E. what sort of BIOS chip / bios saviour kit should I use > with this board?RD1 > > > > output from flashrom, superiotool and lspci appended > below, > > > > many thanks for any help and good luck with your project, > > > > Tom Ward > > > > root@shed:/home/tom/coreboot/flashrom# ./flashrom > > flashrom v0.9.0-r555 > > No coreboot table found. > > Found chipset "NVIDIA CK804", enabling flash > write... OK. > > Calibrating delay loop... OK. > > Found chip "SST SST49LF080A" (1024 KB) at > physical address 0xfff00000.Hopefully this > chip is socketed. > > > superiotool r3695 > > Found Winbond W83627THF/THG (id=0x82, rev=0x84) at > 0x2eThis SuperIO is supported. > > > 00:00.0 Memory controller: nVidia Corporation CK804 Memory > Controller (rev a4) > > This board is very similar to the > tyan/s2892. > > If I were you, my first step would be to get the BIOS > savior (or just use the pushpin method) > > http://www.coreboot.org/Developer_Manual > > > Once you can recover from a bad flash, > > check out the latest coreboot-v2 > mkdir src/mainboard/asus/kfn4-d16 > svn cp src/mainboard/tyan/s2892/* > src/mainboard/asus/kfn4-d16/ > mkdir targets/asus/kfn4-d16 > > svn cp targets/tyan/s2892/Config.lb targets/asus/kfn4-d16/ > > edit src/mainboard/asus/kfn4-d16/Config.lb > > Enable devices that are in your lspci, disable any that > don't show up. Don't worry about cards that you > plug in, they'll be found automatically. > > Change the SuperIO from chip superio/winbond/w83627hf to > superio/winbond/w83627thf and change any settings there that > you need to. > Change socket_940 to socket_F > > (When you're ready to switch to fam10) > Change amdk8 to amdfam10 everywhere (may need some other > small fixups) > > > edit targets/asus/kfn4-d16/Config.lb > Change s2892 to kfn4-d16 > make sure ROM_SIZE matches the chip you're using. > > > > cd targets > > ./buildtarget asus/kfn4-d16 > > make a payload (Maybe seabios) > cp your_payload targets/asus/kfn4-d16/kfn4-d16/payload.elf > > make -C asus/kfn4-d16/kfn4-d16 > > Last step is to send your patches to the list with a > Signed-off-by: <your-email> line. > > > Thanks, > Myles > > > -----Inline Attachment Follows----- > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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[PATCH] cld before call
by Robert Millan 01 Aug '09

01 Aug '09

Hi, The Multiboot spec is a bit too permissive about this, as it doesn't specify the state of direction flag when payload is called. Some payloads (we found this in ReactOS FreeLDR) assume it is cleared, and fail otherwise. We adjusted GRUB to be sure it's always cleared. I think coreboot should do the same. Here's a patch for v3. -- Robert Millan The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and how) you may access your data; but nobody's threatening your freedom: we still allow you to remove your data and not access it at all."

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Re: [coreboot] [LinuxBIOS] ASUS M2N-E (Non-SLI) Motherboard
by Asbjørn Sloth Tønnesen 01 Aug '09

01 Aug '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, In reply to: http://www.coreboot.org/pipermail/coreboot/2007-May/021716.html On Fri, May 25, 2007 at 09:40:47PM -0200, Uwe Hermann wrote: > On Tue, May 22, 2007 at 06:57:07PM -0500, Jonathan King wrote: >> Yes I am willing and able to help in any way needed! Me too, for a long time I have wanted a MB that I could run coreboot on, so I might just as well enable this one to run coreboot. That way I can also run it without an election heater ( > 8MiB GPU). Since it's being used as a home server. > Please post some more information about the mainboard: > > - lspci -n > - lspci -vv > - lspci -tv > - lspnp -v > - cat /proc/cpuinfo - dmesg - dmidecode - sensors-detect http://asbjorn.it/pub/coreboot/m2n-e/mbinfo/ > As far as I can see this board is very similar to the GIGABYTE > GA-M57SLI-S4, so for now we'll just modify that one. > > Please apply the attached patch (which doesn't really change very much). I have updated the patch to v2 trunk, and filled in the PCI bridge ids http://asbjorn.it/pub/coreboot/m2n-e/v2_asus_m2n_e_r4478.patch > Then build a FILO payload which is configured to display serial > debugging, and use the GRUB from your hard drive to boot the kernel. > Enable the maximum amount of debugging. > The result should be a /tmp/filo.elf file. FILO config: http://asbjorn.it/pub/coreboot/m2n-e/filo_config libpayload config: http://asbjorn.it/pub/coreboot/m2n-e/libpayload_config > Then build the linuxbios.rom image by doing > > $ cd targets > $ ./buildtarget gigabyte/m57sli > $ cd targets/gigabyte/m57sli/m57sli > $ make > > Please record all the serial output in a file and post it here... http://asbjorn.it/pub/coreboot/m2n-e/take1.txt CPU and chassis fans all stops shortly before loading the payload, leading to the hardware watchdog restarting the system after af couple of minutes. I didn't got past LILO because I only had SATA drives in the machine and SATA didn't work. What's the next step? How do I continue? How do I fix SATA? - -- Best regards Asbjørn Sloth Tønnesen -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkpzfeIACgkQSViWlxucwuqmywCfd3kV+vKk+9hmMxb1ZZA6Y25o W8kAn0HYtXiDDTCWRtNyp+s22aezW2Pz =+TAq -----END PGP SIGNATURE-----

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coreboot July 2009