coreboot April 2009

coreboot@coreboot.org

69 participants
583 discussions

SeaBIOS and CBFS
by Kevin O'Connor 12 Apr '09

12 Apr '09

Hi, The latest seabios git now supports reading option roms from the CBFS flash layout. To enable it in SeaBIOS, modify src/config.h and make sure the following are set: #define CONFIG_COREBOOT 1 #define CONFIG_OPTIONROMS_DEPLOYED 0 #define CONFIG_COREBOOT_FLASH 1 It will also be necessary to enable support in coreboot (modify Config.lb and add "option CONFIG_ROMFS=1"). The current support just takes raw files, and it does not support compression. To add a rom, use the following: ./romtool coreboot.romfs add vgabios.bin pci1013,00b8.rom 0 Where "vgabios.bin" is the rom file to add and "pci1013,00b8.rom" is the cbfs name - get the proper vendor/deviceid from lspci. Any number of roms may be added. I've tested this on qemu (with a vga rom) and on epia-cn (with vga and gpxe). -Kevin

1 0

Replacement for W39V040BPZ
by Stephan Raue 11 Apr '09

11 Apr '09

Hi all, can i replace my Winbond W39V040BPZ Chip with a 8M Chip like SST49LF080A? Stephan -- ### OpenELEC.tv ### The free and open Mediacenter Distribution 4 you http://www.openelec.tv

2 1

[PATCH] Config.lb assimilation 2/many
by Carl-Daniel Hailfinger 11 Apr '09

11 Apr '09

Unify Config.lb a bit more. Targets affected: gigabyte/ga_2761gxdk (comment fix only) gigabyte/m57sli msi/ms9282 tyan/s2891 tyan/s2892 tyan/s2895 tyan/s2912 tyan/s2912_fam10 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: coreboot-v2-cleanup-configlb/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/gigabyte/m57sli/Config.lb (revision 4095) +++ coreboot-v2-cleanup-configlb/src/mainboard/gigabyte/m57sli/Config.lb (working copy) @@ -81,15 +81,17 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o + makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c + if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -100,7 +102,7 @@ if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end Index: coreboot-v2-cleanup-configlb/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/gigabyte/ga_2761gxdk/Config.lb (revision 4095) +++ coreboot-v2-cleanup-configlb/src/mainboard/gigabyte/ga_2761gxdk/Config.lb (working copy) @@ -162,7 +162,7 @@ ldscript /southbridge/sis/sis966/id.lds ## -## ROMSTRAP table for MCP55 +## ROMSTRAP table for SiS966 ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE Index: coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912/Config.lb (revision 4095) +++ coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912/Config.lb (working copy) @@ -72,8 +72,8 @@ ## ## Build the objects we have code for in this directory. ## +driver mainboard.o -driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o @@ -86,7 +86,7 @@ if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else makerule ./cache_as_ram_auto.inc Index: coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2891/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2891/Config.lb (revision 4095) +++ coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2891/Config.lb (working copy) @@ -1,4 +1,23 @@ ## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## ## Compute the location and size of where this firmware image ## (coreboot plus bootloader) will live in the boot rom chip. ## @@ -35,15 +54,11 @@ arch i386 end - ## ## Build the objects we have code for in this directory. ## - driver mainboard.o -#dir /drivers/ati/ragexl - #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o @@ -63,15 +78,17 @@ #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb end + makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c + if CONFIG_USE_INIT - makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" + makerule ./cache_as_ram_auto.o + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else - makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" + makerule ./cache_as_ram_auto.inc + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -142,9 +159,9 @@ ## Setup RAM ## if CONFIG_USE_INIT - initobject auto.o + initobject cache_as_ram_auto.o else - mainboardinit ./auto.inc + mainboardinit ./cache_as_ram_auto.inc end ## Index: coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2892/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2892/Config.lb (revision 4095) +++ coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2892/Config.lb (working copy) @@ -1,4 +1,23 @@ ## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## ## Compute the location and size of where this firmware image ## (coreboot plus bootloader) will live in the boot rom chip. ## @@ -35,15 +54,11 @@ arch i386 end - ## ## Build the objects we have code for in this directory. ## - driver mainboard.o -#dir /drivers/ati/ragexl - #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o @@ -63,15 +78,17 @@ #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb end + makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c + if CONFIG_USE_INIT - makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" + makerule ./cache_as_ram_auto.o + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else - makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" + makerule ./cache_as_ram_auto.inc + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -142,9 +159,9 @@ ## Setup RAM ## if CONFIG_USE_INIT - initobject auto.o + initobject cache_as_ram_auto.o else - mainboardinit ./auto.inc + mainboardinit ./cache_as_ram_auto.inc end ## Index: coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2895/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2895/Config.lb (revision 4095) +++ coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2895/Config.lb (working copy) @@ -1,4 +1,23 @@ ## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## ## Compute the location and size of where this firmware image ## (coreboot plus bootloader) will live in the boot rom chip. ## @@ -51,8 +70,8 @@ ## ## Build the objects we have code for in this directory. ## +driver mainboard.o -driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o @@ -72,15 +91,17 @@ #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb end + makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c + if CONFIG_USE_INIT - makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" + makerule ./cache_as_ram_auto.o + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else - makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" + makerule ./cache_as_ram_auto.inc + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -177,9 +198,9 @@ ## Setup RAM ## if CONFIG_USE_INIT - initobject auto.o + initobject cache_as_ram_auto.o else - mainboardinit ./auto.inc + mainboardinit ./cache_as_ram_auto.inc end ## Index: coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912_fam10/Config.lb (revision 4095) +++ coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912_fam10/Config.lb (working copy) @@ -72,8 +72,8 @@ ## ## Build the objects we have code for in this directory. ## +driver mainboard.o -driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o @@ -86,7 +86,7 @@ if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else makerule ./cache_as_ram_auto.inc Index: coreboot-v2-cleanup-configlb/src/mainboard/msi/ms9282/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/msi/ms9282/Config.lb (revision 4095) +++ coreboot-v2-cleanup-configlb/src/mainboard/msi/ms9282/Config.lb (working copy) @@ -63,30 +63,29 @@ ## ## Build the objects we have code for in this directory. ## - driver mainboard.o -#dir /drivers/ati/ragexl #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o - if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o + makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c + if CONFIG_USE_INIT -makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +makerule ./cache_as_ram_auto.o + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else -makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" +makerule ./cache_as_ram_auto.inc + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -158,9 +157,9 @@ ## Setup RAM ## if CONFIG_USE_INIT -initobject auto.o +initobject cache_as_ram_auto.o else -mainboardinit ./auto.inc +mainboardinit ./cache_as_ram_auto.inc end ## -- http://www.hailfinger.org/ Index: coreboot-v2-cleanup-configlb/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/gigabyte/m57sli/Config.lb (revision 4095) +++ coreboot-v2-cleanup-configlb/src/mainboard/gigabyte/m57sli/Config.lb (working copy) @@ -81,15 +81,17 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o + makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c + if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -100,7 +102,7 @@ if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end Index: coreboot-v2-cleanup-configlb/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/gigabyte/ga_2761gxdk/Config.lb (revision 4095) +++ coreboot-v2-cleanup-configlb/src/mainboard/gigabyte/ga_2761gxdk/Config.lb (working copy) @@ -162,7 +162,7 @@ ldscript /southbridge/sis/sis966/id.lds ## -## ROMSTRAP table for MCP55 +## ROMSTRAP table for SiS966 ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE Index: coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912/Config.lb (revision 4095) +++ coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912/Config.lb (working copy) @@ -72,8 +72,8 @@ ## ## Build the objects we have code for in this directory. ## +driver mainboard.o -driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o @@ -86,7 +86,7 @@ if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else makerule ./cache_as_ram_auto.inc Index: coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2891/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2891/Config.lb (revision 4095) +++ coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2891/Config.lb (working copy) @@ -1,4 +1,23 @@ ## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## ## Compute the location and size of where this firmware image ## (coreboot plus bootloader) will live in the boot rom chip. ## @@ -35,15 +54,11 @@ arch i386 end - ## ## Build the objects we have code for in this directory. ## - driver mainboard.o -#dir /drivers/ati/ragexl - #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o @@ -63,15 +78,17 @@ #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb end + makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c + if CONFIG_USE_INIT - makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" + makerule ./cache_as_ram_auto.o + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else - makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" + makerule ./cache_as_ram_auto.inc + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -142,9 +159,9 @@ ## Setup RAM ## if CONFIG_USE_INIT - initobject auto.o + initobject cache_as_ram_auto.o else - mainboardinit ./auto.inc + mainboardinit ./cache_as_ram_auto.inc end ## Index: coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2892/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2892/Config.lb (revision 4095) +++ coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2892/Config.lb (working copy) @@ -1,4 +1,23 @@ ## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## ## Compute the location and size of where this firmware image ## (coreboot plus bootloader) will live in the boot rom chip. ## @@ -35,15 +54,11 @@ arch i386 end - ## ## Build the objects we have code for in this directory. ## - driver mainboard.o -#dir /drivers/ati/ragexl - #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o @@ -63,15 +78,17 @@ #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb end + makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c + if CONFIG_USE_INIT - makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" + makerule ./cache_as_ram_auto.o + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else - makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" + makerule ./cache_as_ram_auto.inc + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -142,9 +159,9 @@ ## Setup RAM ## if CONFIG_USE_INIT - initobject auto.o + initobject cache_as_ram_auto.o else - mainboardinit ./auto.inc + mainboardinit ./cache_as_ram_auto.inc end ## Index: coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2895/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2895/Config.lb (revision 4095) +++ coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2895/Config.lb (working copy) @@ -1,4 +1,23 @@ ## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## ## Compute the location and size of where this firmware image ## (coreboot plus bootloader) will live in the boot rom chip. ## @@ -51,8 +70,8 @@ ## ## Build the objects we have code for in this directory. ## +driver mainboard.o -driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o @@ -72,15 +91,17 @@ #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb end + makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c + if CONFIG_USE_INIT - makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" + makerule ./cache_as_ram_auto.o + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else - makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" + makerule ./cache_as_ram_auto.inc + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -177,9 +198,9 @@ ## Setup RAM ## if CONFIG_USE_INIT - initobject auto.o + initobject cache_as_ram_auto.o else - mainboardinit ./auto.inc + mainboardinit ./cache_as_ram_auto.inc end ## Index: coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912_fam10/Config.lb (revision 4095) +++ coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912_fam10/Config.lb (working copy) @@ -72,8 +72,8 @@ ## ## Build the objects we have code for in this directory. ## +driver mainboard.o -driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o @@ -86,7 +86,7 @@ if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else makerule ./cache_as_ram_auto.inc Index: coreboot-v2-cleanup-configlb/src/mainboard/msi/ms9282/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/msi/ms9282/Config.lb (revision 4095) +++ coreboot-v2-cleanup-configlb/src/mainboard/msi/ms9282/Config.lb (working copy) @@ -63,30 +63,29 @@ ## ## Build the objects we have code for in this directory. ## - driver mainboard.o -#dir /drivers/ati/ragexl #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o - if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o + makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c + if CONFIG_USE_INIT -makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +makerule ./cache_as_ram_auto.o + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else -makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" +makerule ./cache_as_ram_auto.inc + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -158,9 +157,9 @@ ## Setup RAM ## if CONFIG_USE_INIT -initobject auto.o +initobject cache_as_ram_auto.o else -mainboardinit ./auto.inc +mainboardinit ./cache_as_ram_auto.inc end ##

4 11

[PATCH] Bring S2912 and S2912_Fam10 Config.lb in line
by Carl-Daniel Hailfinger 11 Apr '09

11 Apr '09

Bring S2912 and S2912_Fam10 Config.lb in line with each other. - Use $(CACHE_AS_RAM_AUTO_C) instead of cache_as_ram_auto.c - Compile apc_auto.c with $(DISTRO_CFLAGS) - Clean up whitespace If anyone can explain the remaining differences in Config.lb which are NOT caused by the K8/Fam10 switch, I'd be glad to hear them. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912/Config.lb (revision 4093) +++ coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912/Config.lb (working copy) @@ -81,15 +81,17 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o + makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c + if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CFLAGS) $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin $(DEBUG_CFLAGS) -Wall -c -S -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -100,7 +102,7 @@ if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -259,7 +261,7 @@ device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 + io 0x60 = 0x290 irq 0x70 = 5 end end @@ -345,16 +347,16 @@ end # PCI domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 on end # mem # device pnp 0.3 off end # cpuid # device pnp 0.4 on end # smbus_regs_all # device pnp 0.5 off end # dual core msr # device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc +# device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 off end # io -# end +# end end #root_complex Index: coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912_fam10/Config.lb (revision 4093) +++ coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912_fam10/Config.lb (working copy) @@ -263,7 +263,7 @@ device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 + io 0x60 = 0x290 irq 0x70 = 5 end end @@ -330,7 +330,7 @@ device pci 4.0 on end register "rom_address" = "0xfff00000" end - end # PCI + end # PCI device pci 6.1 off end # AZA device pci 8.0 on end # NIC device pci 9.0 on end # NIC -- http://www.hailfinger.org/ Index: coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912/Config.lb (revision 4093) +++ coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912/Config.lb (working copy) @@ -81,15 +81,17 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o + makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c + if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CFLAGS) $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin $(DEBUG_CFLAGS) -Wall -c -S -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -100,7 +102,7 @@ if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -259,7 +261,7 @@ device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 + io 0x60 = 0x290 irq 0x70 = 5 end end @@ -345,16 +347,16 @@ end # PCI domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 on end # mem # device pnp 0.3 off end # cpuid # device pnp 0.4 on end # smbus_regs_all # device pnp 0.5 off end # dual core msr # device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc +# device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 off end # io -# end +# end end #root_complex Index: coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912_fam10/Config.lb (revision 4093) +++ coreboot-v2-cleanup-configlb/src/mainboard/tyan/s2912_fam10/Config.lb (working copy) @@ -263,7 +263,7 @@ device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 + io 0x60 = 0x290 irq 0x70 = 5 end end @@ -330,7 +330,7 @@ device pci 4.0 on end register "rom_address" = "0xfff00000" end - end # PCI + end # PCI device pci 6.1 off end # AZA device pci 8.0 on end # NIC device pci 9.0 on end # NIC

2 2

[v2] r4095 - in trunk/coreboot-v2/src/mainboard/tyan: s2912 s2912_fam10
by svn＠coreboot.org 11 Apr '09

11 Apr '09

Author: hailfinger Date: 2009-04-11 20:58:17 +0200 (Sat, 11 Apr 2009) New Revision: 4095 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb Log: Bring S2912 and S2912_Fam10 Config.lb in line with each other. - Use $(CACHE_AS_RAM_AUTO_C) instead of cache_as_ram_auto.c - Compile apc_auto.c with $(DISTRO_CFLAGS) - Clean up whitespace If anyone can explain the remaining differences in Config.lb which are NOT caused by the K8/Fam10 switch, I'd be glad to hear them. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb 2009-04-11 18:09:03 UTC (rev 4094) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb 2009-04-11 18:58:17 UTC (rev 4095) @@ -81,15 +81,17 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o + makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c + if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@" + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CFLAGS) $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin $(DEBUG_CFLAGS) -Wall -c -S -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -100,7 +102,7 @@ if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -259,7 +261,7 @@ device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 + io 0x60 = 0x290 irq 0x70 = 5 end end @@ -345,16 +347,16 @@ end # PCI domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 on end # mem # device pnp 0.3 off end # cpuid # device pnp 0.4 on end # smbus_regs_all # device pnp 0.5 off end # dual core msr # device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc +# device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 off end # io -# end +# end end #root_complex Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb 2009-04-11 18:09:03 UTC (rev 4094) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb 2009-04-11 18:58:17 UTC (rev 4095) @@ -263,7 +263,7 @@ device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 + io 0x60 = 0x290 irq 0x70 = 5 end end @@ -330,7 +330,7 @@ device pci 4.0 on end register "rom_address" = "0xfff00000" end - end # PCI + end # PCI device pci 6.1 off end # AZA device pci 8.0 on end # NIC device pci 9.0 on end # NIC

1 0

[patch] fix k8 raminit edge case
by Ward Vandewege 11 Apr '09

11 Apr '09

See attached. Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior Systems Administrator

2 2

[v2] r4094 - trunk/coreboot-v2/src/northbridge/amd/amdk8
by svn＠coreboot.org 11 Apr '09

11 Apr '09

Author: ward Date: 2009-04-11 20:09:03 +0200 (Sat, 11 Apr 2009) New Revision: 4094 Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c Log: This patch fixes an edge case for K8 raminit. Specifically, it brings the code in line with the K10 code. I was trying to use DDR2 800 (CL6) memory on an m57sli, but booting failed. Marc Jones found this bug (thanks!), which fixes booting with this specific memory. For the record, it was Crucial CT2KIT25664AA800. I put the machine through a few days of use. It also succesfully passed a run of http://people.redhat.com/dledford/memtest.shtml: $ ./memtest TEST_DIR: /tmp SOURCE_FILE: linux-2.6.29.1.tar.bz2 NR_PASSES: 20 MEGS_PER_COPY: 270 NR_COPIES: 45 PARALLEL: no COMPRESS_RATIO: 5 COMPRESS_FLAG: j COMPRESS_PROG: /bin/bzip2 EXTRACT: yes Creating comparison source...done. Starting test pass #1: unpacking, comparing, removing, done. Starting test pass #2: unpacking, comparing, removing, done. Starting test pass #3: unpacking, comparing, removing, done. Starting test pass #4: unpacking, comparing, removing, done. Starting test pass #5: unpacking, comparing, removing, done. Starting test pass #6: unpacking, comparing, removing, done. Starting test pass #7: unpacking, comparing, removing, done. Starting test pass #8: unpacking, comparing, removing, done. Starting test pass #9: unpacking, comparing, removing, done. Starting test pass #10: unpacking, comparing, removing, done. Starting test pass #11: unpacking, comparing, removing, done. Starting test pass #12: unpacking, comparing, removing, done. Starting test pass #13: unpacking, comparing, removing, done. Starting test pass #14: unpacking, comparing, removing, done. Starting test pass #15: unpacking, comparing, removing, done. Starting test pass #16: unpacking, comparing, removing, done. Starting test pass #17: unpacking, comparing, removing, done. Starting test pass #18: unpacking, comparing, removing, done. Starting test pass #19: unpacking, comparing, removing, done. Starting test pass #20: unpacking, comparing, removing, done. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2009-04-11 14:51:49 UTC (rev 4093) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2009-04-11 18:09:03 UTC (rev 4094) @@ -2071,7 +2071,8 @@ } if (clocks > TT_MAX) { - return 0; + printk_info("warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX); + clocks = TT_MAX; } dtl = pci_read_config32(ctrl->f2, TT_REG);

1 0

[PATCH] Kill remaining unneeded CAR/ROMCC if-blocks
by Carl-Daniel Hailfinger 11 Apr '09

11 Apr '09

Kill remaining unneeded CAR/ROMCC if-blocks. Lots of Config.lb files still have "if USE_DCACHE_RAM" sections although USE_DCACHE_RAM is always set for them. Such checks are not only pointless, they actively make the files hard to read. A full abuild run confirmed that compilation did not change with this patch applied. The patch does not change whitespace of the remaining code to ease review and svn blame. With this change, it should be possible to have two or three Config.lb variants in total (except the actual hardware config). Right now, some Config.lb have comments, some don't, some have empty lines for better readability, some don't, some have leading whitespace, some don't. This is an utter mess and unifying these files would certainly reduce the headaches I have when looking at them. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8_htx/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8_htx/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8_htx/Config.lb (working copy) @@ -129,8 +129,6 @@ end end -if USE_DCACHE_RAM - if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o @@ -148,7 +146,6 @@ end end -end if USE_FAILOVER_IMAGE else @@ -178,7 +175,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -186,7 +182,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -215,12 +210,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -229,15 +222,11 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -248,16 +237,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Index: coreboot-v2-kill-orphan-romcc/src/mainboard/broadcom/blast/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/broadcom/blast/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/broadcom/blast/Config.lb (working copy) @@ -50,8 +50,6 @@ #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -70,14 +68,12 @@ end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -85,7 +81,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -104,12 +99,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -117,12 +110,7 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -132,16 +120,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Index: coreboot-v2-kill-orphan-romcc/src/mainboard/supermicro/h8dmr/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/supermicro/h8dmr/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/supermicro/h8dmr/Config.lb (working copy) @@ -80,7 +80,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o @@ -96,8 +95,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -127,7 +124,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -135,9 +131,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -180,12 +174,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -194,29 +186,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/supermicro/h8dme/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/supermicro/h8dme/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/supermicro/h8dme/Config.lb (working copy) @@ -77,7 +77,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o @@ -93,8 +92,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -124,7 +121,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -132,9 +128,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -177,12 +171,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -191,29 +183,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/gigabyte/m57sli/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/gigabyte/m57sli/Config.lb (working copy) @@ -80,7 +80,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -96,8 +95,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -127,7 +124,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -135,9 +131,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -180,12 +174,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -194,15 +186,11 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -213,14 +201,11 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/gigabyte/ga_2761gxdk/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/gigabyte/ga_2761gxdk/Config.lb (working copy) @@ -82,7 +82,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -98,8 +97,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -129,7 +126,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -137,9 +133,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -182,12 +176,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -196,29 +188,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/digitallogic/msm800sev/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/digitallogic/msm800sev/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/digitallogic/msm800sev/Config.lb (working copy) @@ -48,7 +48,6 @@ object irq_tables.o end -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -56,10 +55,7 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -107,10 +103,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/amd/pistachio/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/amd/pistachio/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/amd/pistachio/Config.lb (working copy) @@ -83,8 +83,6 @@ #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -103,14 +101,12 @@ end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -118,7 +114,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -137,12 +132,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -150,12 +143,7 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -165,16 +153,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Index: coreboot-v2-kill-orphan-romcc/src/mainboard/amd/dbm690t/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/amd/dbm690t/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/amd/dbm690t/Config.lb (working copy) @@ -83,8 +83,6 @@ #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -103,14 +101,12 @@ end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -118,7 +114,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -137,12 +132,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -150,12 +143,7 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -165,16 +153,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Index: coreboot-v2-kill-orphan-romcc/src/mainboard/amd/serengeti_cheetah/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/amd/serengeti_cheetah/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/amd/serengeti_cheetah/Config.lb (working copy) @@ -122,8 +122,6 @@ end end -if USE_DCACHE_RAM - if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o @@ -140,7 +138,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if USE_FAILOVER_IMAGE else @@ -170,7 +167,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -178,7 +174,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -207,12 +202,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -221,15 +214,11 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -240,16 +229,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Index: coreboot-v2-kill-orphan-romcc/src/mainboard/amd/norwich/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/amd/norwich/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/amd/norwich/Config.lb (working copy) @@ -52,7 +52,6 @@ #object reset.o -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -60,9 +59,7 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -110,10 +107,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb (working copy) @@ -129,7 +129,6 @@ end end -if USE_DCACHE_RAM makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c if CONFIG_USE_INIT @@ -149,7 +148,6 @@ end end -end if USE_FAILOVER_IMAGE else @@ -179,7 +177,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -187,7 +184,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -217,12 +213,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -231,15 +225,11 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -250,16 +240,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Index: coreboot-v2-kill-orphan-romcc/src/mainboard/amd/db800/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/amd/db800/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/amd/db800/Config.lb (working copy) @@ -50,7 +50,6 @@ object irq_tables.o end -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -58,9 +57,7 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -108,10 +105,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/iei/pcisa-lx-800-r10/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/iei/pcisa-lx-800-r10/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/iei/pcisa-lx-800-r10/Config.lb (working copy) @@ -35,7 +35,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM # Compile cache_as_ram.c to auto.inc. makerule ./cache_as_ram_auto.inc # depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -44,7 +43,6 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds @@ -63,10 +61,8 @@ # mainboardinit ./failover.inc end mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end dir /pc80 config chip.h Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2912/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2912/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2912/Config.lb (working copy) @@ -81,8 +81,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -97,8 +95,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -128,7 +124,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -136,9 +131,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -181,12 +174,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -195,29 +186,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2912_fam10/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2912_fam10/Config.lb (working copy) @@ -81,7 +81,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c if CONFIG_USE_INIT @@ -98,8 +97,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -129,7 +126,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -137,9 +133,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -182,12 +176,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -196,29 +188,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/pcengines/alix1c/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/pcengines/alix1c/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/pcengines/alix1c/Config.lb (working copy) @@ -68,7 +68,6 @@ object irq_tables.o end -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -76,10 +75,7 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -127,10 +123,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/artecgroup/dbe61/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/artecgroup/dbe61/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/artecgroup/dbe61/Config.lb (working copy) @@ -47,8 +47,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o - -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -56,9 +54,7 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -106,10 +102,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/lippert/roadrunner-lx/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/lippert/roadrunner-lx/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/lippert/roadrunner-lx/Config.lb (working copy) @@ -72,7 +72,6 @@ object irq_tables.o end -if USE_DCACHE_RAM # compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c" @@ -80,9 +79,7 @@ action "perl -e 's/.rodata/.rom.data/g' -pi $@" action "perl -e 's/.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -130,10 +127,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/lippert/spacerunner-lx/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/lippert/spacerunner-lx/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/lippert/spacerunner-lx/Config.lb (working copy) @@ -70,7 +70,6 @@ object irq_tables.o end -if USE_DCACHE_RAM # compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c" @@ -78,7 +77,6 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end ## ## Build our 16 bit and 32 bit coreboot entry code @@ -127,10 +125,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms7135/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms7135/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms7135/Config.lb (working copy) @@ -90,7 +90,6 @@ object irq_tables.o end -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -104,7 +103,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end ## ## Build our 16 bit and 32 bit coreboot entry code. @@ -123,12 +121,10 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (this is where coreboot is entered). @@ -151,12 +147,6 @@ end end -if USE_DCACHE_RAM -else - ### Should this be in the northbridge code? - mainboardinit arch/i386/lib/cpu_reset.inc -end - ## ## Include an ID string (for safe flashing). ## @@ -178,14 +168,11 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end - ### ### This is the early phase of coreboot startup. ### Things are delicate and we test to see if we should @@ -193,15 +180,11 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -212,13 +195,11 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -end ## ## Include the secondary configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9185/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9185/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9185/Config.lb (working copy) @@ -77,8 +77,6 @@ object irq_tables.o end -if USE_DCACHE_RAM - if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o @@ -96,7 +94,6 @@ end end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -107,7 +104,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -115,7 +111,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -134,12 +129,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -147,9 +140,7 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end ### @@ -159,16 +150,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Index: coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms7260/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms7260/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms7260/Config.lb (working copy) @@ -54,7 +54,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -68,7 +67,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if USE_FAILOVER_IMAGE else @@ -95,14 +93,12 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -138,31 +134,23 @@ end end -if USE_DCACHE_RAM mainboardinit cpu/amd/car/cache_as_ram.inc -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end config chip.h Index: coreboot-v2-kill-orphan-romcc/src/mainboard/technexion/tim8690/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/technexion/tim8690/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/technexion/tim8690/Config.lb (working copy) @@ -83,8 +83,6 @@ #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -103,14 +101,12 @@ end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -118,7 +114,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -137,12 +132,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -150,12 +143,7 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -165,16 +153,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Index: coreboot-v2-kill-orphan-romcc/src/mainboard/nvidia/l1_2pvv/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/nvidia/l1_2pvv/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/nvidia/l1_2pvv/Config.lb (working copy) @@ -111,8 +111,6 @@ end end -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -127,8 +125,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -158,7 +154,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -166,9 +161,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -211,12 +204,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -225,29 +216,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/asus/a8v-e_se/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/asus/a8v-e_se/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/asus/a8v-e_se/Config.lb (working copy) @@ -52,7 +52,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -66,7 +65,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -77,14 +75,12 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -94,23 +90,17 @@ ldscript /cpu/x86/32bit/reset32.lds end -if USE_DCACHE_RAM mainboardinit cpu/amd/car/cache_as_ram.inc -end if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end config chip.h Index: coreboot-v2-kill-orphan-romcc/src/mainboard/asus/a8n_e/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/asus/a8n_e/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/asus/a8n_e/Config.lb (working copy) @@ -54,7 +54,6 @@ object get_bus_conf.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -68,7 +67,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -81,12 +79,10 @@ end end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/amd/car/cache_as_ram.lds end -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -104,10 +100,6 @@ ldscript /cpu/x86/32bit/reset32.lds end end -if USE_DCACHE_RAM -else - mainboardinit arch/i386/lib/cpu_reset.inc -end # Include an ID string (for safe flashing). mainboardinit southbridge/nvidia/ck804/id.inc ldscript /southbridge/nvidia/ck804/id.lds @@ -123,29 +115,21 @@ ldscript /southbridge/nvidia/ck804/romstrap.lds end end -if USE_DCACHE_RAM mainboardinit cpu/amd/car/cache_as_ram.inc -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -end config chip.h chip northbridge/amd/amdk8/root_complex # Root complex Index: coreboot-v2-kill-orphan-romcc/src/mainboard/asus/m2v-mx_se/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/asus/m2v-mx_se/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/asus/m2v-mx_se/Config.lb (working copy) @@ -55,7 +55,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -69,7 +68,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -80,14 +78,12 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -97,23 +93,17 @@ ldscript /cpu/x86/32bit/reset32.lds end -if USE_DCACHE_RAM mainboardinit cpu/amd/car/cache_as_ram.inc -end if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end config chip.h -- http://www.hailfinger.org/ Index: coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8_htx/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8_htx/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8_htx/Config.lb (working copy) @@ -129,8 +129,6 @@ end end -if USE_DCACHE_RAM - if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o @@ -148,7 +146,6 @@ end end -end if USE_FAILOVER_IMAGE else @@ -178,7 +175,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -186,7 +182,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -215,12 +210,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -229,15 +222,11 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -248,16 +237,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Index: coreboot-v2-kill-orphan-romcc/src/mainboard/broadcom/blast/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/broadcom/blast/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/broadcom/blast/Config.lb (working copy) @@ -50,8 +50,6 @@ #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -70,14 +68,12 @@ end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -85,7 +81,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -104,12 +99,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -117,12 +110,7 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -132,16 +120,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Index: coreboot-v2-kill-orphan-romcc/src/mainboard/supermicro/h8dmr/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/supermicro/h8dmr/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/supermicro/h8dmr/Config.lb (working copy) @@ -80,7 +80,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o @@ -96,8 +95,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -127,7 +124,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -135,9 +131,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -180,12 +174,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -194,29 +186,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/supermicro/h8dme/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/supermicro/h8dme/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/supermicro/h8dme/Config.lb (working copy) @@ -77,7 +77,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o @@ -93,8 +92,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -124,7 +121,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -132,9 +128,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -177,12 +171,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -191,29 +183,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/gigabyte/m57sli/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/gigabyte/m57sli/Config.lb (working copy) @@ -80,7 +80,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -96,8 +95,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -127,7 +124,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -135,9 +131,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -180,12 +174,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -194,15 +186,11 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -213,14 +201,11 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/gigabyte/ga_2761gxdk/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/gigabyte/ga_2761gxdk/Config.lb (working copy) @@ -82,7 +82,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -98,8 +97,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -129,7 +126,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -137,9 +133,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -182,12 +176,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -196,29 +188,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/digitallogic/msm800sev/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/digitallogic/msm800sev/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/digitallogic/msm800sev/Config.lb (working copy) @@ -48,7 +48,6 @@ object irq_tables.o end -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -56,10 +55,7 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -107,10 +103,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/amd/pistachio/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/amd/pistachio/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/amd/pistachio/Config.lb (working copy) @@ -83,8 +83,6 @@ #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -103,14 +101,12 @@ end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -118,7 +114,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -137,12 +132,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -150,12 +143,7 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -165,16 +153,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Index: coreboot-v2-kill-orphan-romcc/src/mainboard/amd/dbm690t/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/amd/dbm690t/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/amd/dbm690t/Config.lb (working copy) @@ -83,8 +83,6 @@ #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -103,14 +101,12 @@ end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -118,7 +114,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -137,12 +132,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -150,12 +143,7 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -165,16 +153,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Index: coreboot-v2-kill-orphan-romcc/src/mainboard/amd/serengeti_cheetah/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/amd/serengeti_cheetah/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/amd/serengeti_cheetah/Config.lb (working copy) @@ -122,8 +122,6 @@ end end -if USE_DCACHE_RAM - if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o @@ -140,7 +138,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if USE_FAILOVER_IMAGE else @@ -170,7 +167,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -178,7 +174,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -207,12 +202,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -221,15 +214,11 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -240,16 +229,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Index: coreboot-v2-kill-orphan-romcc/src/mainboard/amd/norwich/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/amd/norwich/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/amd/norwich/Config.lb (working copy) @@ -52,7 +52,6 @@ #object reset.o -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -60,9 +59,7 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -110,10 +107,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb (working copy) @@ -129,7 +129,6 @@ end end -if USE_DCACHE_RAM makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c if CONFIG_USE_INIT @@ -149,7 +148,6 @@ end end -end if USE_FAILOVER_IMAGE else @@ -179,7 +177,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -187,7 +184,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -217,12 +213,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -231,15 +225,11 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -250,16 +240,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Index: coreboot-v2-kill-orphan-romcc/src/mainboard/amd/db800/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/amd/db800/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/amd/db800/Config.lb (working copy) @@ -50,7 +50,6 @@ object irq_tables.o end -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -58,9 +57,7 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -108,10 +105,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/iei/pcisa-lx-800-r10/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/iei/pcisa-lx-800-r10/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/iei/pcisa-lx-800-r10/Config.lb (working copy) @@ -35,7 +35,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM # Compile cache_as_ram.c to auto.inc. makerule ./cache_as_ram_auto.inc # depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -44,7 +43,6 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds @@ -63,10 +61,8 @@ # mainboardinit ./failover.inc end mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end dir /pc80 config chip.h Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2912/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2912/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2912/Config.lb (working copy) @@ -81,8 +81,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -97,8 +95,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -128,7 +124,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -136,9 +131,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -181,12 +174,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -195,29 +186,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2912_fam10/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2912_fam10/Config.lb (working copy) @@ -81,7 +81,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c if CONFIG_USE_INIT @@ -98,8 +97,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -129,7 +126,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -137,9 +133,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -182,12 +176,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -196,29 +188,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/pcengines/alix1c/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/pcengines/alix1c/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/pcengines/alix1c/Config.lb (working copy) @@ -68,7 +68,6 @@ object irq_tables.o end -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -76,10 +75,7 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -127,10 +123,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/artecgroup/dbe61/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/artecgroup/dbe61/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/artecgroup/dbe61/Config.lb (working copy) @@ -47,8 +47,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o - -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -56,9 +54,7 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -106,10 +102,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/lippert/roadrunner-lx/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/lippert/roadrunner-lx/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/lippert/roadrunner-lx/Config.lb (working copy) @@ -72,7 +72,6 @@ object irq_tables.o end -if USE_DCACHE_RAM # compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c" @@ -80,9 +79,7 @@ action "perl -e 's/.rodata/.rom.data/g' -pi $@" action "perl -e 's/.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -130,10 +127,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/lippert/spacerunner-lx/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/lippert/spacerunner-lx/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/lippert/spacerunner-lx/Config.lb (working copy) @@ -70,7 +70,6 @@ object irq_tables.o end -if USE_DCACHE_RAM # compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c" @@ -78,7 +77,6 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end ## ## Build our 16 bit and 32 bit coreboot entry code @@ -127,10 +125,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms7135/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms7135/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms7135/Config.lb (working copy) @@ -90,7 +90,6 @@ object irq_tables.o end -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -104,7 +103,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end ## ## Build our 16 bit and 32 bit coreboot entry code. @@ -123,12 +121,10 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (this is where coreboot is entered). @@ -151,12 +147,6 @@ end end -if USE_DCACHE_RAM -else - ### Should this be in the northbridge code? - mainboardinit arch/i386/lib/cpu_reset.inc -end - ## ## Include an ID string (for safe flashing). ## @@ -178,14 +168,11 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end - ### ### This is the early phase of coreboot startup. ### Things are delicate and we test to see if we should @@ -193,15 +180,11 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -212,13 +195,11 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -end ## ## Include the secondary configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9185/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9185/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9185/Config.lb (working copy) @@ -77,8 +77,6 @@ object irq_tables.o end -if USE_DCACHE_RAM - if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o @@ -96,7 +94,6 @@ end end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -107,7 +104,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -115,7 +111,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -134,12 +129,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -147,9 +140,7 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end ### @@ -159,16 +150,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Index: coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms7260/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms7260/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms7260/Config.lb (working copy) @@ -54,7 +54,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -68,7 +67,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if USE_FAILOVER_IMAGE else @@ -95,14 +93,12 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -138,31 +134,23 @@ end end -if USE_DCACHE_RAM mainboardinit cpu/amd/car/cache_as_ram.inc -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end config chip.h Index: coreboot-v2-kill-orphan-romcc/src/mainboard/technexion/tim8690/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/technexion/tim8690/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/technexion/tim8690/Config.lb (working copy) @@ -83,8 +83,6 @@ #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -103,14 +101,12 @@ end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -118,7 +114,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -137,12 +132,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -150,12 +143,7 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -165,16 +153,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Index: coreboot-v2-kill-orphan-romcc/src/mainboard/nvidia/l1_2pvv/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/nvidia/l1_2pvv/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/nvidia/l1_2pvv/Config.lb (working copy) @@ -111,8 +111,6 @@ end end -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -127,8 +125,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -158,7 +154,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -166,9 +161,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -211,12 +204,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -225,29 +216,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files Index: coreboot-v2-kill-orphan-romcc/src/mainboard/asus/a8v-e_se/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/asus/a8v-e_se/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/asus/a8v-e_se/Config.lb (working copy) @@ -52,7 +52,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -66,7 +65,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -77,14 +75,12 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -94,23 +90,17 @@ ldscript /cpu/x86/32bit/reset32.lds end -if USE_DCACHE_RAM mainboardinit cpu/amd/car/cache_as_ram.inc -end if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end config chip.h Index: coreboot-v2-kill-orphan-romcc/src/mainboard/asus/a8n_e/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/asus/a8n_e/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/asus/a8n_e/Config.lb (working copy) @@ -54,7 +54,6 @@ object get_bus_conf.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -68,7 +67,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -81,12 +79,10 @@ end end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/amd/car/cache_as_ram.lds end -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -104,10 +100,6 @@ ldscript /cpu/x86/32bit/reset32.lds end end -if USE_DCACHE_RAM -else - mainboardinit arch/i386/lib/cpu_reset.inc -end # Include an ID string (for safe flashing). mainboardinit southbridge/nvidia/ck804/id.inc ldscript /southbridge/nvidia/ck804/id.lds @@ -123,29 +115,21 @@ ldscript /southbridge/nvidia/ck804/romstrap.lds end end -if USE_DCACHE_RAM mainboardinit cpu/amd/car/cache_as_ram.inc -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -end config chip.h chip northbridge/amd/amdk8/root_complex # Root complex Index: coreboot-v2-kill-orphan-romcc/src/mainboard/asus/m2v-mx_se/Config.lb =================================================================== --- coreboot-v2-kill-orphan-romcc/src/mainboard/asus/m2v-mx_se/Config.lb (revision 4091) +++ coreboot-v2-kill-orphan-romcc/src/mainboard/asus/m2v-mx_se/Config.lb (working copy) @@ -55,7 +55,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -69,7 +68,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -80,14 +78,12 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -97,23 +93,17 @@ ldscript /cpu/x86/32bit/reset32.lds end -if USE_DCACHE_RAM mainboardinit cpu/amd/car/cache_as_ram.inc -end if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end config chip.h

2 2

[v2] r4093 - in trunk/coreboot-v2/src/mainboard: amd/db800 amd/dbm690t amd/norwich amd/pistachio amd/serengeti_cheetah amd/serengeti_cheetah_fam10 artecgroup/dbe61 asus/a8n_e asus/a8v-e_se asus/m2v-mx_se broadcom/blast digitallogic/msm800sev gigabyte/ga_2761gxdk gigabyte/m57sli iei/pcisa-lx-800-r10 iwill/dk8_htx lippert/roadrunner-lx lippert/spacerunner-lx msi/ms7135 msi/ms7260 msi/ms9185 nvidia/l1_2pvv pcengines/alix1c supermicro/h8dme supermicro/h8dmr technexion/tim8690 tyan/s2912 tyan/s2912_fa
by svn＠coreboot.org 11 Apr '09

11 Apr '09

Author: hailfinger Date: 2009-04-11 16:51:49 +0200 (Sat, 11 Apr 2009) New Revision: 4093 Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb trunk/coreboot-v2/src/mainboard/technexion/tim8690/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb Log: Kill remaining unneeded CAR/ROMCC if-blocks. Lots of Config.lb files still have "if USE_DCACHE_RAM" sections although USE_DCACHE_RAM is always set for them. Such checks are not only pointless, they actively make the files hard to read. A full abuild run confirmed that compilation did not change with this patch applied. The patch does not change whitespace of the remaining code to ease review and svn blame. With this change, it should be possible to have two or three Config.lb variants in total (except the actual hardware config). Right now, some Config.lb have comments, some don't, some have empty lines for better readability, some don't, some have leading whitespace, some don't. This is an utter mess and unifying these files would certainly reduce the headaches I have when looking at them. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -50,7 +50,6 @@ object irq_tables.o end -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -58,9 +57,7 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -108,10 +105,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -83,8 +83,6 @@ #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -103,14 +101,12 @@ end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -118,7 +114,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -137,12 +132,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -150,12 +143,7 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -165,16 +153,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Modified: trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -52,7 +52,6 @@ #object reset.o -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -60,9 +59,7 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -110,10 +107,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -83,8 +83,6 @@ #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -103,14 +101,12 @@ end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -118,7 +114,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -137,12 +132,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -150,12 +143,7 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -165,16 +153,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -122,8 +122,6 @@ end end -if USE_DCACHE_RAM - if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o @@ -140,7 +138,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if USE_FAILOVER_IMAGE else @@ -170,7 +167,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -178,7 +174,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -207,12 +202,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -221,15 +214,11 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -240,16 +229,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -129,7 +129,6 @@ end end -if USE_DCACHE_RAM makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c if CONFIG_USE_INIT @@ -149,7 +148,6 @@ end end -end if USE_FAILOVER_IMAGE else @@ -179,7 +177,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -187,7 +184,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -217,12 +213,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -231,15 +225,11 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -250,16 +240,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -47,8 +47,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o - -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -56,9 +54,7 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -106,10 +102,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -54,7 +54,6 @@ object get_bus_conf.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -68,7 +67,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -81,12 +79,10 @@ end end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/amd/car/cache_as_ram.lds end -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -104,10 +100,6 @@ ldscript /cpu/x86/32bit/reset32.lds end end -if USE_DCACHE_RAM -else - mainboardinit arch/i386/lib/cpu_reset.inc -end # Include an ID string (for safe flashing). mainboardinit southbridge/nvidia/ck804/id.inc ldscript /southbridge/nvidia/ck804/id.lds @@ -123,29 +115,21 @@ ldscript /southbridge/nvidia/ck804/romstrap.lds end end -if USE_DCACHE_RAM mainboardinit cpu/amd/car/cache_as_ram.inc -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -end config chip.h chip northbridge/amd/amdk8/root_complex # Root complex Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -52,7 +52,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -66,7 +65,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -77,14 +75,12 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -94,23 +90,17 @@ ldscript /cpu/x86/32bit/reset32.lds end -if USE_DCACHE_RAM mainboardinit cpu/amd/car/cache_as_ram.inc -end if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end config chip.h Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -55,7 +55,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -69,7 +68,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -80,14 +78,12 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -97,23 +93,17 @@ ldscript /cpu/x86/32bit/reset32.lds end -if USE_DCACHE_RAM mainboardinit cpu/amd/car/cache_as_ram.inc -end if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end config chip.h Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -50,8 +50,6 @@ #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -70,14 +68,12 @@ end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -85,7 +81,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -104,12 +99,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -117,12 +110,7 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -132,16 +120,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -48,7 +48,6 @@ object irq_tables.o end -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -56,10 +55,7 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -107,10 +103,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -82,7 +82,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -98,8 +97,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -129,7 +126,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -137,9 +133,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -182,12 +176,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -196,29 +188,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -80,7 +80,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -96,8 +95,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -127,7 +124,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -135,9 +131,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -180,12 +174,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -194,15 +186,11 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -213,14 +201,11 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files Modified: trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -35,7 +35,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM # Compile cache_as_ram.c to auto.inc. makerule ./cache_as_ram_auto.inc # depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -44,7 +43,6 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds @@ -63,10 +61,8 @@ # mainboardinit ./failover.inc end mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end dir /pc80 config chip.h Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -129,8 +129,6 @@ end end -if USE_DCACHE_RAM - if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o @@ -148,7 +146,6 @@ end end -end if USE_FAILOVER_IMAGE else @@ -178,7 +175,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -186,7 +182,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -215,12 +210,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -229,15 +222,11 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -248,16 +237,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -72,7 +72,6 @@ object irq_tables.o end -if USE_DCACHE_RAM # compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c" @@ -80,9 +79,7 @@ action "perl -e 's/.rodata/.rom.data/g' -pi $@" action "perl -e 's/.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -130,10 +127,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary configuration files Modified: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -70,7 +70,6 @@ object irq_tables.o end -if USE_DCACHE_RAM # compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c" @@ -78,7 +77,6 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end ## ## Build our 16 bit and 32 bit coreboot entry code @@ -127,10 +125,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary configuration files Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -90,7 +90,6 @@ object irq_tables.o end -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -104,7 +103,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end ## ## Build our 16 bit and 32 bit coreboot entry code. @@ -123,12 +121,10 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (this is where coreboot is entered). @@ -151,12 +147,6 @@ end end -if USE_DCACHE_RAM -else - ### Should this be in the northbridge code? - mainboardinit arch/i386/lib/cpu_reset.inc -end - ## ## Include an ID string (for safe flashing). ## @@ -178,14 +168,11 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end - ### ### This is the early phase of coreboot startup. ### Things are delicate and we test to see if we should @@ -193,15 +180,11 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -212,13 +195,11 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -end ## ## Include the secondary configuration files Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -54,7 +54,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -68,7 +67,6 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if USE_FAILOVER_IMAGE else @@ -95,14 +93,12 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -138,31 +134,23 @@ end end -if USE_DCACHE_RAM mainboardinit cpu/amd/car/cache_as_ram.inc -end if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end -if USE_DCACHE_RAM if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end config chip.h Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -77,8 +77,6 @@ object irq_tables.o end -if USE_DCACHE_RAM - if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o @@ -96,7 +94,6 @@ end end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -107,7 +104,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -115,7 +111,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -134,12 +129,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -147,9 +140,7 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end ### @@ -159,16 +150,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -111,8 +111,6 @@ end end -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -127,8 +125,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -158,7 +154,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -166,9 +161,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -211,12 +204,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -225,29 +216,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files Modified: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -68,7 +68,6 @@ object irq_tables.o end -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -76,10 +75,7 @@ action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - - ## ## Build our 16 bit and 32 bit coreboot entry code ## @@ -127,10 +123,8 @@ ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -77,7 +77,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o @@ -93,8 +92,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -124,7 +121,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -132,9 +128,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -177,12 +171,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -191,29 +183,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -end ## ## Include the secondary Configuration files Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -80,7 +80,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o @@ -96,8 +95,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -127,7 +124,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -135,9 +131,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -180,12 +174,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -194,29 +186,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -end ## ## Include the secondary Configuration files Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -83,8 +83,6 @@ #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -103,14 +101,12 @@ end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -118,7 +114,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -137,12 +132,10 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -150,12 +143,7 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -165,16 +153,12 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -81,8 +81,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -97,8 +95,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -128,7 +124,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -136,9 +131,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -181,12 +174,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -195,29 +186,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb 2009-04-11 13:59:00 UTC (rev 4092) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb 2009-04-11 14:51:49 UTC (rev 4093) @@ -81,7 +81,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c if CONFIG_USE_INIT @@ -98,8 +97,6 @@ end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -129,7 +126,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -137,9 +133,7 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) ## @@ -182,12 +176,10 @@ end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -196,29 +188,22 @@ ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files

1 0

Coreboot spanish chapter?
by Manuel Cornejo 11 Apr '09

11 Apr '09

3 2

← Newer
1
...
39
40
41
42
43
44
45
...
59
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot April 2009