coreboot April 2009

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[PATCH] Add ACPI generic resume support
by Rudolf Marek 13 Apr '09

13 Apr '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, Following patch implements ACPI resume support for coreboot. The hardware main hook will come in separate patch perhaps. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkngvEEACgkQ3J9wPJqZRNWQJgCeLV/QW++cZ+O4Jm/gX/F3O8TA b2gAn2WDZjRLy9FsmuqRaXHgDjfhE4MT =BbSl -----END PGP SIGNATURE-----

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[v2] r4101 - in trunk/coreboot-v2/src/arch/i386: boot include/arch
by svn＠coreboot.org 13 Apr '09

13 Apr '09

Author: ruik Date: 2009-04-13 20:07:02 +0200 (Mon, 13 Apr 2009) New Revision: 4101 Added: trunk/coreboot-v2/src/arch/i386/boot/wakeup.S Modified: trunk/coreboot-v2/src/arch/i386/boot/Config.lb trunk/coreboot-v2/src/arch/i386/boot/acpi.c trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h Log: Following patch implements ACPI resume support for coreboot. The hardware main hook will come in separate patch perhaps. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/arch/i386/boot/Config.lb =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/Config.lb 2009-04-13 18:00:09 UTC (rev 4100) +++ trunk/coreboot-v2/src/arch/i386/boot/Config.lb 2009-04-13 18:07:02 UTC (rev 4101) @@ -14,4 +14,7 @@ if HAVE_ACPI_TABLES object acpi.o object acpigen.o +if HAVE_ACPI_RESUME +object wakeup.S end +end Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2009-04-13 18:00:09 UTC (rev 4100) +++ trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2009-04-13 18:07:02 UTC (rev 4101) @@ -27,6 +27,11 @@ #include <arch/acpigen.h> #include <device/pci.h> +#if HAVE_ACPI_RESUME == 1 +/* this is to be filled by SB code - startup value what was found */ +u8 acpi_slp_type; +#endif + u8 acpi_checksum(u8 *table, u32 length) { u8 ret=0; @@ -323,12 +328,12 @@ header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } - void acpi_create_facs(acpi_facs_t *facs) { + memset( (void *)facs,0, sizeof(acpi_facs_t)); - memcpy(facs->signature,"FACS",4); + memcpy(facs->signature, FACS_NAME, 4); facs->length = sizeof(acpi_facs_t); facs->hardware_signature = 0; facs->firmware_waking_vector = 0; @@ -365,11 +370,114 @@ { memcpy(rsdp->signature, RSDP_SIG, 8); memcpy(rsdp->oem_id, OEM_ID, 6); - rsdp->length = sizeof(acpi_rsdp_t); rsdp->rsdt_address = (u32)rsdt; + rsdp->revision = 2; rsdp->checksum = acpi_checksum((void *)rsdp, 20); rsdp->ext_checksum = acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t)); } +#if HAVE_ACPI_RESUME == 1 +int acpi_get_sleep_type(void) +{ + return acpi_slp_type; +} + +int acpi_is_wakeup(void) +{ + return (acpi_slp_type == 3); +} + +static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp) +{ + if (strncmp((char *)rsdp, RSDP_SIG, sizeof(RSDP_SIG) - 1) != 0) + return NULL; + + printk_debug("Looking on %p for valid checksum\n", rsdp); + + if (acpi_checksum((void *)rsdp, 20) != 0) + return NULL; + printk_debug("Checksum 1 passed\n"); + + if ((rsdp->revision > 1) && (acpi_checksum((void *)rsdp, + rsdp->length) != 0)) + return NULL; + + printk_debug("Checksum 2 passed all OK\n"); + + return rsdp; +} + +static acpi_rsdp_t *rsdp; + +void *acpi_get_wakeup_rsdp(void) +{ + return rsdp; +} + +void *acpi_find_wakeup_vector(void) +{ + char *p, *end; + + acpi_rsdt_t *rsdt; + acpi_facs_t *facs; + acpi_fadt_t *fadt; + void *wake_vec; + int i; + + rsdp = NULL; + + if (!acpi_is_wakeup()) + return NULL; + + printk_debug("Trying to find the wakeup vector ...\n"); + + /* find RSDP */ + for (p = (char *) 0xe0000; p < (char *) 0xfffff; p+=16) { + if ((rsdp = valid_rsdp((acpi_rsdp_t *) p))) + break; + } + + if (rsdp == NULL) + return NULL; + + printk_debug("RSDP found at %p\n", rsdp); + rsdt = (acpi_rsdt_t *) rsdp->rsdt_address; + + end = (char *) rsdt + rsdt->header.length; + printk_debug("RSDT found at %p ends at %p\n", rsdt, end); + + for (i = 0; ((char *) &rsdt->entry[i]) < end; i++) { + fadt = (acpi_fadt_t *) rsdt->entry[i]; + if (strncmp((char *)fadt, FADT_NAME, sizeof(FADT_NAME) - 1) == 0) + break; + fadt = NULL; + } + + if (fadt == NULL) + return NULL; + + printk_debug("FADT found at %p\n", fadt); + facs = fadt->firmware_ctrl; + + if (facs == NULL) + return NULL; + + printk_debug("FACS found at %p\n", facs); + wake_vec = (void *) facs->firmware_waking_vector; + printk_debug("OS waking vector is %p\n", wake_vec); + return wake_vec; +} + +extern char *lowmem_backup; +extern char *lowmem_backup_ptr; +extern int lowmem_backup_size; + +void acpi_jump_to_wakeup(void *vector) +{ + /* just restore the SMP trampoline and continue with wakeup on assembly level */ + memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size); + acpi_jmp_to_realm_wakeup((u32) vector); +} +#endif Added: trunk/coreboot-v2/src/arch/i386/boot/wakeup.S =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/wakeup.S (rev 0) +++ trunk/coreboot-v2/src/arch/i386/boot/wakeup.S 2009-04-13 18:07:02 UTC (rev 4101) @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + .text + .code32 + .globl acpi_jmp_to_realm_wakeup + /* This function does the PM -> RM switch, but + it can run >1MB even in real mode */ + +acpi_jmp_to_realm_wakeup: + mov 0x4(%esp), %eax + /* last 4 bits of linear addr are taken as offset */ + andw $0x0f, %ax + movw %ax, (jmp_off) + mov 0x4(%esp), %eax + /* the rest is taken as segment */ + shr $4, %eax + movw %ax, (jmp_seg) + lgdt gdtaddr_wakeup + movl $0x008,%eax + mov %eax,%ds + movl %eax,%es + movl %eax,%ss + movl %eax,%fs + movl %eax,%gs + ljmp $0x0010,$reload_cs + .code16gcc +reload_cs: + /* switch off PE */ + movl %cr0, %eax + andb $0xfe,%al + movl %eax, %cr0 + movw $0x0, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs + /* far jump to OS waking vector. The linear addr is changed to SEG and OFFSET + check ACPI specs or above code for details */ + .byte 0xea +jmp_off: + .word 0 +jmp_seg: + .word 0 + +.code32 +gdt_wakeup_limit = gdt_wakeup_end - gdt_wakeup - 1 /* compute the table limit */ + gdtaddr_wakeup: + .word gdt_wakeup_limit /* the table limit */ + .long gdt_wakeup /* we know the offset */ + + .data + + /* This is the gdt for GCC part of coreboot. + * It is different from the gdt in ROMCC/ASM part of coreboot + * which is defined in entry32.inc */ +gdt_wakeup: + /* selgdt 0, unused */ + .word 0x0000, 0x0000 /* dummy */ + .byte 0x00, 0x00, 0x00, 0x00 + + /* selgdt 8, flat data segment 16bit */ + .word 0x0000, 0x0000 /* dummy */ + .byte 0x00, 0x93, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ + + /* selgdt 0x10, flat code segment 16bit */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ + +gdt_wakeup_end: + + .previous +.code32 Modified: trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h 2009-04-13 18:00:09 UTC (rev 4100) +++ trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h 2009-04-13 18:07:02 UTC (rev 4101) @@ -16,6 +16,9 @@ #if HAVE_ACPI_TABLES==1 #include <stdint.h> + +/* 0 = S0, 1 = S1 ...*/ +extern u8 acpi_slp_type; #define RSDP_SIG "RSD PTR " /* RSDT Pointer signature */ #define RSDP_NAME "RSDP" @@ -27,6 +30,8 @@ #define SRAT_NAME "SRAT" #define SLIT_NAME "SLIT" #define SSDT_NAME "SSDT" +#define FACS_NAME "FACS" +#define FADT_NAME "FACP" #define RSDT_TABLE "RSDT " #define HPET_TABLE "AMD64 " @@ -328,6 +333,10 @@ void acpi_write_rsdt(acpi_rsdt_t *rsdt); void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt); +void *acpi_find_wakeup_vector(void); +void *acpi_get_wakeup_rsdp(void); +extern void acpi_jmp_to_realm_wakeup(u32 linear_addr); +void acpi_jump_to_wakeup(void *wakeup_addr); unsigned long acpi_add_ssdt_pstates(acpi_rsdt_t *rsdt, unsigned long current);

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[PATCH] VT8237/K8M890 resume support
by Rudolf Marek 13 Apr '09

13 Apr '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, Following patch adds support for resume on VT8237 based motherboards. The NB part of this patch adds support for resume well NVRAM. In which DQS values are stored. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkng3NkACgkQ3J9wPJqZRNUabACgt7bHzQIx+VA157v4TyfSi5G/ GW4An3Yna5/7wqC4HhCxMrjNP2V7Rszd =wsnP -----END PGP SIGNATURE-----

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[v2] r4100 - in trunk/coreboot-v2/src/southbridge/via: k8t890 vt8237r
by svn＠coreboot.org 13 Apr '09

13 Apr '09

Author: ruik Date: 2009-04-13 20:00:09 +0200 (Mon, 13 Apr 2009) New Revision: 4100 Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890.h trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_early_car.c trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_host_ctrl.c trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c Log: Following patch adds support for resume on VT8237 based motherboards. The NB part of this patch adds support for resume well NVRAM. In which DQS values are stored. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890.h =================================================================== --- trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890.h 2009-04-13 17:57:44 UTC (rev 4099) +++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890.h 2009-04-13 18:00:09 UTC (rev 4100) @@ -29,6 +29,9 @@ */ #define K8T890_APIC_BASE 0xfecc0000 +/* The 256 bytes of NVRAM for S3 storage, 256B aligned */ +#define K8T890_NVRAM_IO_BASE 0xf00 + #define K8T890_MMCONFIG_MBAR 0x61 #define K8T890_MULTIPLE_FN_EN 0x4f @@ -36,6 +39,7 @@ #define K8M890_FBSIZEMB 64 #include <device/device.h> + extern void writeback(struct device *dev, u16 where, u8 what); extern void dump_south(device_t dev); Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_early_car.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_early_car.c 2009-04-13 17:57:44 UTC (rev 4099) +++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_early_car.c 2009-04-13 18:00:09 UTC (rev 4100) @@ -23,7 +23,16 @@ */ #include <stdlib.h> +//include "k8t890.h" +#warning hack the right header here +/* The 256 bytes of NVRAM for S3 storage, 256B aligned */ +#define K8T890_NVRAM_IO_BASE 0xf00 +#define K8T890_MULTIPLE_FN_EN 0x4f +/* we provide S3 NVRAM to system */ +#define S3_NVRAM_EARLY 1 + + /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */ static ldtreg[3] = {0x86, 0xa6, 0xc6}; @@ -33,10 +42,22 @@ u8 k8t890_early_setup_ht(void) { - u8 awidth, afreq, cldtfreq; + u8 awidth, afreq, cldtfreq, reg; u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width; u16 vldtcaps; + /* hack, enable NVRAM in chipset */ + pci_write_config8(PCI_DEV(0, 0x0, 0), K8T890_MULTIPLE_FN_EN, 0x01); + + /* + * NVRAM I/O base at K8T890_NVRAM_IO_BASE + */ + + pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa2, (K8T890_NVRAM_IO_BASE >> 8)); + reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1); + reg |= 0x1; + pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg); + /* check if connected non coherent, initcomplete (find the SB on K8 side) */ if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0x98)) { ldtnr = 0; @@ -90,3 +111,44 @@ return 1; } + +int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { + + printk_debug("Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); + switch (size) { + case 1: + outb((dword & 0xff), K8T890_NVRAM_IO_BASE+nvram_pos); + nvram_pos +=1; + break; + case 2: + outw((dword & 0xffff), K8T890_NVRAM_IO_BASE+nvram_pos); + nvram_pos +=2; + break; + default: + outl(dword, K8T890_NVRAM_IO_BASE+nvram_pos); + nvram_pos +=4; + break; + } + return nvram_pos; +} + +int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { + switch (size) { + case 1: + *old_dword &= ~0xff; + *old_dword |= inb(K8T890_NVRAM_IO_BASE+nvram_pos); + nvram_pos +=1; + break; + case 2: + *old_dword &= ~0xffff; + *old_dword |= inw(K8T890_NVRAM_IO_BASE+nvram_pos); + nvram_pos +=2; + break; + default: + *old_dword = inl(K8T890_NVRAM_IO_BASE+nvram_pos); + nvram_pos +=4; + break; + } + printk_debug("Loading %x of size %d to nvram pos:%d\n", * old_dword, size, nvram_pos-size); + return nvram_pos; +} Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_host_ctrl.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_host_ctrl.c 2009-04-13 17:57:44 UTC (rev 4099) +++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_host_ctrl.c 2009-04-13 18:00:09 UTC (rev 4100) @@ -37,14 +37,14 @@ */ pci_write_config8(dev, 0xa0, 0x13); - /* Disable NVRAM and enable non-posted PCI writes. */ - pci_write_config8(dev, 0xa1, 0x8e); - /* - * NVRAM I/O base 0xe00-0xeff, but it is disabled. + * NVRAM I/O base at K8T890_NVRAM_IO_BASE * Some bits are set and reserved. */ - pci_write_config8(dev, 0xa2, 0x0e); + pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8)); + + /* enable NB NVRAM and enable non-posted PCI writes. */ + pci_write_config8(dev, 0xa1, 0x8f); /* Arbitration control, some bits are reserved. */ pci_write_config8(dev, 0xa5, 0x3c); @@ -95,14 +95,15 @@ */ pci_write_config8(dev, 0xa0, 0x13); - /* Disable NVRAM and enable non-posted PCI writes. */ - pci_write_config8(dev, 0xa1, 0x8e); - /* - * NVRAM I/O base 0xe00-0xeff, but it is disabled. + * NVRAM I/O base at K8T890_NVRAM_IO_BASE */ - pci_write_config8(dev, 0xa2, 0x0e); + pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8)); + + /* Enable NVRAM and enable non-posted PCI writes. */ + pci_write_config8(dev, 0xa1, 0x8f); + /* Arbitration control */ pci_write_config8(dev, 0xa5, 0x3c); Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c 2009-04-13 17:57:44 UTC (rev 4099) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c 2009-04-13 18:00:09 UTC (rev 4100) @@ -294,6 +294,37 @@ pci_write_config8(dev, 0x41, 0x7f); } +#define ACPI_IS_WAKEUP_EARLY 1 + +int acpi_is_wakeup_early(void) { + device_t dev; + u16 tmp; + + print_debug("IN TEST WAKEUP\n"); + + /* Power management controller */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + if (dev == PCI_DEV_INVALID) { + /* Power management controller */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); + if (dev == PCI_DEV_INVALID) + die("Power management controller not found\r\n"); + } + + /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ + pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); + + /* Enable ACPI accessm RTC signal gated with PSON. */ + pci_write_config8(dev, 0x81, 0x84); + + tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); + + print_debug_hex8(tmp); + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; +} + #if defined(__GNUC__) void vt8237_early_spi_init(void) { Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2009-04-13 17:57:44 UTC (rev 4099) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2009-04-13 18:00:09 UTC (rev 4100) @@ -149,8 +149,13 @@ * Set up the power management capabilities directly into ACPI mode. * This avoids having to handle any System Management Interrupts (SMIs). */ + +extern u8 acpi_slp_type; + + static void setup_pm(device_t dev) { + u16 tmp; /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -171,10 +176,10 @@ /* * 7 = SMBus clock from RTC 32.768KHz - * 5 = Internal PLL reset from susp - * 2 = GPO2 is GPIO + * 5 = Internal PLL reset from susp disabled + * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa4); + pci_write_config8(dev, 0x94, 0xa0); /* * 7 = stp to sust delay 1msec @@ -219,7 +224,17 @@ outb(0x0, VT8237R_ACPI_IO_BASE + 0x42); /* SCI is generated for RTC/pwrBtn/slpBtn. */ - outw(0x001, VT8237R_ACPI_IO_BASE + 0x04); + tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); + acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; + printk_debug("SLP_TYP type was %x %x\n", tmp, acpi_slp_type); + /* clear sleep */ + tmp &= ~(7 << 10); + tmp |= 1; + outw(tmp, VT8237R_ACPI_IO_BASE + 0x04); + + + + } static void vt8237r_init(struct device *dev)

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[PATCH] ACPI general support for resume
by Rudolf Marek 13 Apr '09

13 Apr '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, Following patch adds necessary hooks and as well the compile time checks for ACPI suspend/resume. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkng3GgACgkQ3J9wPJqZRNWBcgCePS7W4uc1KUdPVkjLCBcKVQoz zjkAnjcNBHU2kiEtgDPJ4JT9aV1iweQx =a8Y2 -----END PGP SIGNATURE-----

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[v2] r4099 - in trunk/coreboot-v2/src: boot config cpu/amd/car cpu/x86/lapic
by svn＠coreboot.org 13 Apr '09

13 Apr '09

Author: ruik Date: 2009-04-13 19:57:44 +0200 (Mon, 13 Apr 2009) New Revision: 4099 Modified: trunk/coreboot-v2/src/boot/hardwaremain.c trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c Log: Following patch adds necessary hooks and as well the compile time checks for ACPI suspend/resume. The memory cleared now is just the coreboot memory not the low memory. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/boot/hardwaremain.c =================================================================== --- trunk/coreboot-v2/src/boot/hardwaremain.c 2009-04-13 16:21:16 UTC (rev 4098) +++ trunk/coreboot-v2/src/boot/hardwaremain.c 2009-04-13 17:57:44 UTC (rev 4099) @@ -37,6 +37,7 @@ #include <part/init_timer.h> #include <boot/elf.h> #include <romfs.h> +#include <arch/acpi.h> /** * @brief Main function of the DRAM part of coreboot. @@ -47,9 +48,11 @@ * Device Enumeration: * In the dev_enumerate() phase, */ + void hardwaremain(int boot_complete) { struct lb_memory *lb_mem; + void *wake_vec; post_code(0x80); @@ -84,11 +87,27 @@ dev_initialize(); post_code(0x89); +#if HAVE_ACPI_RESUME == 1 + +#if MEM_TRAIN_SEQ != 0 + #error "So far it works on AMD and MEM_TRAIN_SEQ == 0" +#endif + +#if _RAMBASE < 0x1F00000 + #error "For ACPI RESUME you need to have _RAMBASE at least 31MB" + #error "Chipset support (S3_NVRAM_EARLY and ACPI_IS_WAKEUP_EARLY functions and memory ctrl)" + #error "And coreboot memory reserved in mainboard.c" +#endif + /* if we happen to be resuming find wakeup vector and jump to OS */ + wake_vec = acpi_find_wakeup_vector(); + if (wake_vec) + acpi_jump_to_wakeup(wake_vec); +#endif + /* Now that we have collected all of our information * write our configuration tables. */ lb_mem = write_tables(); - #if CONFIG_ROMFS == 1 # if USE_FALLBACK_IMAGE == 1 void (*pl)(void) = romfs_load_payload(lb_mem, "fallback/payload"); Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-04-13 16:21:16 UTC (rev 4098) +++ trunk/coreboot-v2/src/config/Options.lb 2009-04-13 17:57:44 UTC (rev 4099) @@ -927,6 +927,12 @@ comment "Define to build ACPI tables" end +define HAVE_ACPI_RESUME + default 0 + export always + comment "Define to build ACPI with resume support" +end + define ACPI_SSDTX_NUM default 0 export always Modified: trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c 2009-04-13 16:21:16 UTC (rev 4098) +++ trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c 2009-04-13 17:57:44 UTC (rev 4099) @@ -6,8 +6,7 @@ // gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram // will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already // so noline clear_init_ram - clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE)); - + clear_memory( _RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - _RAMBASE - DCACHE_RAM_SIZE); } /* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/ Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-04-13 16:21:16 UTC (rev 4098) +++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-04-13 17:57:44 UTC (rev 4099) @@ -31,6 +31,12 @@ } #endif +#if HAVE_ACPI_RESUME == 1 +char *lowmem_backup; +char *lowmem_backup_ptr; +int lowmem_backup_size; +#endif + static void copy_secondary_start_to_1m_below(void) { #if _RAMBASE >= 0x100000 @@ -45,6 +51,17 @@ start_eip = get_valid_start_eip((unsigned long)_secondary_start); code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start; +#if HAVE_ACPI_RESUME == 1 + /* need to save it for RAM resume */ + lowmem_backup_size = code_size; + lowmem_backup = malloc(code_size); + lowmem_backup_ptr = (unsigned char *)start_eip; + + if (lowmem_backup == NULL) + die("Out of backup memory\n"); + + memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size); +#endif /* copy the _secondary_start to the ram below 1M*/ memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);

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Just FYI: if you are under 18, you are out of GSOC; make sure your birthday is in there correctly!
by ron minnich 13 Apr '09

13 Apr '09

We just got the notice from Google. There are a lot of applicants under 18 --> automatic disqualification. Student applicants, please verify your personal information. Thanks ron

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build service results for r4098
by coreboot information 13 Apr '09

13 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "hailfinger" checked in revision 4098 to the coreboot repository. This caused the following changes: Change Log: Fix the following errors: In file included from src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c:93: src/northbridge/amd/amdk8/raminit.c: In function ‘sdram_set_spd_registers’: src/northbridge/amd/amdk8/raminit.c:2123: error: implicit declaration of function ‘activate_spd_rom’ In file included from src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c:101: src/cpu/amd/model_fxx/init_cpus.c: In function ‘init_cpus’: src/cpu/amd/model_fxx/init_cpus.c:319: error: implicit declaration of function ‘soft_reset’ In file included from src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c:98: src/northbridge/amd/amdk8/raminit_f.c: In function ‘sdram_set_spd_registers’: src/northbridge/amd/amdk8/raminit_f.c:2848: error: implicit declaration of function ‘activate_spd_rom’ Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of amd:serengeti_cheetah is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4098&device=serengeti_chee… Compilation of asus:a8v-e_se has been fixed Compilation of asus:m2v-mx_se has been fixed Compilation of digitallogic:msm800sev is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4098&device=msm800sev&vend… Compilation of pcengines:alix1c is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4098&device=alix1c&vendor=… Compilation of supermicro:h8dme is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4098&device=h8dme&vendor=s… Compilation of supermicro:h8dmr is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4098&device=h8dmr&vendor=s… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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Remaining implicit declaration errors
by Carl-Daniel Hailfinger 13 Apr '09

13 Apr '09

My gcc call unification patch breaks 7 targets because those targets don't use CFLAGS and thus are not affected by -Werror-implicit-function-declaration. In file included from src/mainboard/amd/serengeti_cheetah/apc_auto.c:65: src/cpu/amd/dualcore/dualcore.c: In function ‘start_other_cores’: src/cpu/amd/dualcore/dualcore.c:64: error: implicit declaration of function ‘get_nodes’ In file included from src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c:93: src/northbridge/amd/amdk8/raminit.c: In function ‘sdram_set_spd_registers’: src/northbridge/amd/amdk8/raminit.c:2123: error: implicit declaration of function ‘activate_spd_rom’ In file included from src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c:101: src/cpu/amd/model_fxx/init_cpus.c: In function ‘init_cpus’: src/cpu/amd/model_fxx/init_cpus.c:319: error: implicit declaration of function ‘soft_reset’ In file included from src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c:98: src/northbridge/amd/amdk8/raminit_f.c: In function ‘sdram_set_spd_registers’: src/northbridge/amd/amdk8/raminit_f.c:2848: error: implicit declaration of function ‘activate_spd_rom’ src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c: In function ‘cache_as_ram_main’: src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c:117: error: implicit declaration of function ‘done_cache_as_ram_main’ src/mainboard/pcengines/alix1c/cache_as_ram_auto.c: In function ‘cache_as_ram_main’: src/mainboard/pcengines/alix1c/cache_as_ram_auto.c:209: error: implicit declaration of function ‘done_cache_as_ram_main’ In file included from src/mainboard/supermicro/h8dme/apc_auto.c:85: src/cpu/amd/dualcore/dualcore.c: In function ‘start_other_cores’: src/cpu/amd/dualcore/dualcore.c:64: error: implicit declaration of function ‘get_nodes’ In file included from src/mainboard/supermicro/h8dmr/apc_auto.c:85: src/cpu/amd/dualcore/dualcore.c: In function ‘start_other_cores’: src/cpu/amd/dualcore/dualcore.c:64: error: implicit declaration of function ‘get_nodes’ Fixes for the above breakage are really appreciated. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[v2] r4098 - in trunk/coreboot-v2/src/mainboard/asus: a8v-e_se m2v-mx_se
by svn＠coreboot.org 13 Apr '09

13 Apr '09

Author: hailfinger Date: 2009-04-13 18:21:16 +0200 (Mon, 13 Apr 2009) New Revision: 4098 Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c Log: Fix the following errors: In file included from src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c:93: src/northbridge/amd/amdk8/raminit.c: In function ?\226?\128?\152sdram_set_spd_registers?\226?\128?\153: src/northbridge/amd/amdk8/raminit.c:2123: error: implicit declaration of function ?\226?\128?\152activate_spd_rom?\226?\128?\153 In file included from src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c:101: src/cpu/amd/model_fxx/init_cpus.c: In function ?\226?\128?\152init_cpus?\226?\128?\153: src/cpu/amd/model_fxx/init_cpus.c:319: error: implicit declaration of function ?\226?\128?\152soft_reset?\226?\128?\153 In file included from src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c:98: src/northbridge/amd/amdk8/raminit_f.c: In function ?\226?\128?\152sdram_set_spd_registers?\226?\128?\153: src/northbridge/amd/amdk8/raminit_f.c:2848: error: implicit declaration of function ?\226?\128?\152activate_spd_rom?\226?\128?\153 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c 2009-04-12 21:47:09 UTC (rev 4097) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c 2009-04-13 16:21:16 UTC (rev 4098) @@ -87,30 +87,10 @@ return smbus_read_byte(device, address); } -#define K8_4RANK_DIMM_SUPPORT 1 - -#include "northbridge/amd/amdk8/amdk8.h" -#include "northbridge/amd/amdk8/raminit.c" -#include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include "sdram/generic_sdram.c" -#include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/via/k8t890/k8t890_early_car.c" -#include "cpu/amd/car/copy_and_run.c" -#include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/model_fxx/init_cpus.c" -#include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/resourcemap.c" - void activate_spd_rom(const struct mem_controller *ctrl) { } -void hard_reset(void) -{ - print_info("NO HARD RESET. FIX ME!\n"); -} - void soft_reset(void) { uint8_t tmp; @@ -129,6 +109,26 @@ } } +#define K8_4RANK_DIMM_SUPPORT 1 + +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/raminit.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "sdram/generic_sdram.c" +#include "cpu/amd/dualcore/dualcore.c" +#include "southbridge/via/k8t890/k8t890_early_car.c" +#include "cpu/amd/car/copy_and_run.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +void hard_reset(void) +{ + print_info("NO HARD RESET. FIX ME!\n"); +} + unsigned int get_sbdn(unsigned bus) { device_t dev; Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2009-04-12 21:47:09 UTC (rev 4097) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2009-04-13 16:21:16 UTC (rev 4098) @@ -90,6 +90,10 @@ return smbus_read_byte(device, address); } +void activate_spd_rom(const struct mem_controller *ctrl) +{ +} + #define K8_4RANK_DIMM_SUPPORT 1 @@ -122,10 +126,6 @@ #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/resourcemap.c" -void activate_spd_rom(const struct mem_controller *ctrl) -{ -} - #warning No hard_reset implemented for this board! void hard_reset(void) {

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coreboot April 2009