coreboot April 2009

coreboot@coreboot.org

69 participants
583 discussions

Romfs -> cbfs conversion
by Myles Watson 16 Apr '09

16 Apr '09

Peter, Do you still have any outstanding patches? It looks like there are still many references to romfs in src/lib/. I also get this in the output of make: rm -f coreboot.cbfs ./cbfstool ./coreboot.romfs create 524288 65536 ./coreboot.rom.bootblock (cbfstool) E: ./coreboot.romfs already exists - cannot create make: *** [coreboot.romfs] Error 255 make: Leaving directory `/home/myles/buildrom-devel/work/coreboot/svn/targets/emulation/qemu-x86/qemu-x86' Thanks, Myles

8 15

[v2] r4125 - trunk/coreboot-v2/src/include
by svn＠coreboot.org 16 Apr '09

16 Apr '09

Author: rminnich Date: 2009-04-17 04:40:20 +0200 (Fri, 17 Apr 2009) New Revision: 4125 Removed: trunk/coreboot-v2/src/include/romfs.h Log: This needed to be removed. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Deleted: trunk/coreboot-v2/src/include/romfs.h =================================================================== --- trunk/coreboot-v2/src/include/romfs.h 2009-04-16 21:09:56 UTC (rev 4124) +++ trunk/coreboot-v2/src/include/romfs.h 2009-04-17 02:40:20 UTC (rev 4125) @@ -1,169 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Jordan Crouse <jordan(a)cosmicpenguin.net> - * - * This file is dual-licensed. You can choose between: - * - The GNU GPL, version 2, as published by the Free Software Foundation - * - The revised BSD license (without advertising clause) - * - * --------------------------------------------------------------------------- - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA - * --------------------------------------------------------------------------- - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * --------------------------------------------------------------------------- - */ - -#ifndef _ROMFS_H_ -#define _ROMFS_H_ - -/** These are standard values for the known compression - alogrithms that coreboot knows about for stages and - payloads. Of course, other LAR users can use whatever - values they want, as long as they understand them. */ - -#define ROMFS_COMPRESS_NONE 0 -#define ROMFS_COMPRESS_LZMA 1 -#define ROMFS_COMPRESS_NRV2B 2 - -/** These are standard component types for well known - components (i.e - those that coreboot needs to consume. - Users are welcome to use any other value for their - components */ - -#define ROMFS_TYPE_STAGE 0x10 -#define ROMFS_TYPE_PAYLOAD 0x20 -#define ROMFS_TYPE_OPTIONROM 0x30 - -/** this is the master romfs header - it need to be - located somewhere in the bootblock. Where it - actually lives is up to coreboot. A pointer to - this header will live at 0xFFFFFFFc, so we can - easily find it. */ - -#define ROMFS_HEADER_MAGIC 0x4F524243 -#define ROMFS_HEADPTR_ADDR 0xFFFFFFFc -#define VERSION1 0x31313131 - -struct romfs_header { - u32 magic; - u32 version; - u32 romsize; - u32 bootblocksize; - u32 align; - u32 offset; - u32 pad[2]; -} __attribute__((packed)); - -/** This is a component header - every entry in the ROMFS - will have this header. - - This is how the component is arranged in the ROM: - - -------------- <- 0 - component header - -------------- <- sizeof(struct component) - component name - -------------- <- offset - data - ... - -------------- <- offset + len -*/ - -#define ROMFS_FILE_MAGIC "LARCHIVE" - -struct romfs_file { - char magic[8]; - u32 len; - u32 type; - u32 checksum; - u32 offset; -} __attribute__((packed)); - -/*** Component sub-headers ***/ - -/* Following are component sub-headers for the "standard" - component types */ - -/** This is the sub-header for stage components. Stages are - loaded by coreboot during the normal boot process */ - -struct romfs_stage { - u32 compression; /** Compression type */ - u64 entry; /** entry point */ - u64 load; /** Where to load in memory */ - u32 len; /** length of data to load */ - u32 memlen; /** total length of object in memory */ -} __attribute__((packed)); - -/** this is the sub-header for payload components. Payloads - are loaded by coreboot at the end of the boot process */ - -struct romfs_payload_segment { - u32 type; - u32 compression; - u32 offset; - u64 load_addr; - u32 len; - u32 mem_len; -} __attribute__((packed)); - -struct romfs_payload { - struct romfs_payload_segment segments; -}; - -#define PAYLOAD_SEGMENT_CODE 0x45444F43 -#define PAYLOAD_SEGMENT_DATA 0x41544144 -#define PAYLOAD_SEGMENT_BSS 0x20535342 -#define PAYLOAD_SEGMENT_PARAMS 0x41524150 -#define PAYLOAD_SEGMENT_ENTRY 0x52544E45 - -struct romfs_optionrom { - u32 compression; - u32 len; -} __attribute__((packed)); - -#define ROMFS_NAME(_c) (((char *) (_c)) + sizeof(struct romfs_file)) -#define ROMFS_SUBHEADER(_p) ( (void *) ((((u8 *) (_p)) + ntohl((_p)->offset))) ) - -void * romfs_load_payload(struct lb_memory *lb_mem, const char *name); -void * romfs_load_stage(const char *name); -int romfs_execute_stage(const char *name); -void * romfs_get_file(const char *name); -void *romfs_load_optionrom(u16 vendor, u16 device, void * dest); -int run_address(void *f); - -#endif -

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build service results for r4124
by coreboot information 16 Apr '09

16 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "ruik" checked in revision 4124 to the coreboot repository. This caused the following changes: Change Log: Following patch flushes the instruction queue when we set PE=0. This is normally done by FAR JMP, but here it is more tricky because we run at EIP>1MB. Many thanks to Marc and Kevin to tell me how to fix it The trick is to use 0x66 prefix (done with ljmpl) it will allow to jump in real mode to any EIP addresses ;) Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of digitallogic:msm800sev is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4124&device=msm800sev&vend… Compilation of pcengines:alix1c is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4124&device=alix1c&vendor=… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] flush CPU queue when PE set 0
by Rudolf Marek 16 Apr '09

16 Apr '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello Following patch flushes the instruction queue when we set PE=0. This is normally done by FAR JMP, but here it is more tricky because we run at EIP>1MB. Many thanks to Marc and Kevin to tell me how to fix it The trick is to use 0x66 prefix (done with ljmpl) it will allow to jump in real mode to any EIP addresses ;) Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Rudolf =================================================================== - --- arch/i386/boot/wakeup.S (revision 4106) +++ arch/i386/boot/wakeup.S (working copy) @@ -45,6 +45,8 @@ movl %cr0, %eax andb $0xfe,%al movl %eax, %cr0 + ljmpl $0x0, $cpu_flushed +cpu_flushed: movw $0x0, %ax movw %ax, %ds movw %ax, %es -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAknjtyIACgkQ3J9wPJqZRNUugwCguIMboaTCW8eUz+JI2RcOanNC zA4An0iflgt3O/3YcJ7hcXBqHUsMSTjZ =Ad2w -----END PGP SIGNATURE-----

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[v2] r4124 - trunk/coreboot-v2/src/arch/i386/boot
by svn＠coreboot.org 16 Apr '09

16 Apr '09

Author: ruik Date: 2009-04-16 23:09:56 +0200 (Thu, 16 Apr 2009) New Revision: 4124 Modified: trunk/coreboot-v2/src/arch/i386/boot/wakeup.S Log: Following patch flushes the instruction queue when we set PE=0. This is normally done by FAR JMP, but here it is more tricky because we run at EIP>1MB. Many thanks to Marc and Kevin to tell me how to fix it The trick is to use 0x66 prefix (done with ljmpl) it will allow to jump in real mode to any EIP addresses ;) Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/arch/i386/boot/wakeup.S =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/wakeup.S 2009-04-16 16:42:05 UTC (rev 4123) +++ trunk/coreboot-v2/src/arch/i386/boot/wakeup.S 2009-04-16 21:09:56 UTC (rev 4124) @@ -45,6 +45,8 @@ movl %cr0, %eax andb $0xfe,%al movl %eax, %cr0 + ljmpl $0x0, $cpu_flushed +cpu_flushed: movw $0x0, %ax movw %ax, %ds movw %ax, %es

1 0

build service results for r4123
by coreboot information 16 Apr '09

16 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4123 to the coreboot repository. This caused the following changes: Change Log: I deleted mptable.c in my patch, but forgot to svn rm it. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of digitallogic:msm800sev is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4123&device=msm800sev&vend… Compilation of pcengines:alix1c is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4123&device=alix1c&vendor=… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4123 - trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se
by svn＠coreboot.org 16 Apr '09

16 Apr '09

Author: myles Date: 2009-04-16 18:42:05 +0200 (Thu, 16 Apr 2009) New Revision: 4123 Removed: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mptable.c Log: I deleted mptable.c in my patch, but forgot to svn rm it. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Deleted: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mptable.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mptable.c 2009-04-15 22:40:43 UTC (rev 4122) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mptable.c 2009-04-16 16:42:05 UTC (rev 4123) @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Rudolf Marek <r.marek(a)assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License v2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <stdint.h> -#include <arch/smp/mpspec.h> -#include <../../../southbridge/via/vt8237r/vt8237r.h> -#include <../../../southbridge/via/k8t890/k8t890.h> - -unsigned long write_smp_table(unsigned long addr) -{ - /* place holder for a table, need to have it defined because - of MP_ used by ACPI */ - - return addr; -}

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[PATCH] VIA CX700 support
by Stefan Reinauer 16 Apr '09

16 Apr '09

See patch. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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Re: [coreboot] Porting coreboot to Intel Atom (Silverthorne) & SCH US15W (Poulsbo) chipset
by bari 16 Apr '09

16 Apr '09

There are several i945 + Atom boards available. This way you can develop and test Atom on a working chipset and then work on the US15W. -Bari Mansoor wrote: > > Thanks bari and joseph for your sugession.I will use i945 code as reference > > Regards > Mansoor > ----- Original Message ----- From: "Joseph Smith" <joe(a)settoplinux.org> > To: "bari" <bari(a)onelabs.com> > Cc: "Mansoor" <mansoor(a)iwavesystems.com>; <coreboot(a)coreboot.org> > Sent: Tuesday, April 14, 2009 7:45 PM > Subject: Re: [coreboot] Porting coreboot to Intel Atom (Silverthorne) & > SCH US15W (Poulsbo) chipset > > >> >> >> >> On Tue, 14 Apr 2009 08:56:06 -0500, bari <bari(a)onelabs.com> wrote: >>> Mansoor wrote: >>>> Hi, >>>> >>>> I have a Atom Silverthorne Poulsbo based board >>>> (http://www.iwavesystems.com/iW-Q7.htm). I want to port coreboot on >>>> this >>>> platform. >>>> >>>> I would like to know if anybody has started/suceeded in porting >>>> coreboot >>>> to Atom, also if there is anyone interested in such a port. >>> >>> There is lots of interest in Atom support. Nobody I am aware of has >>> enough documentation yet. Maybe you do since you have an Atom based COM >>> module? http://iwavesystems.com/iW-Q7.htm >>> >>>> 1)Which version of coreboot can be used (v2 or v3) ? >>>> 2)Which platform (CPU,motherboard,EC) can be taken as reference ? >>> >>> The i945 is supported by v2 so an Atom + i945 board would be the >>> shortest path to success. >>> >> Yes, I would have to agree with Bari here. You should start with the i945 >> code. >> >> -- >> Thanks, >> Joseph Smith >> Set-Top-Linux >> www.settoplinux.org >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> >> ------------------------------------------------------------------------------- >> >> DISCLAIMER: This e-mail and any attachment (s) is for authorised use >> by the >> intended recipient (s) only. It may contain proprietary material, >> confidential >> information and/or be subject to the legal privilege of iWave Systems >> Technologies Private Limited. If you have received this message in error, >> please notify the originator immediately. If you are not the intended >> recipient, you are notified that you are strictly prohibited from >> retaining, >> using, copying, alerting or disclosing the content of this message. >> Thank you >> for your co-operation. >> ------------------------------------------------------------------------------ >> > > ------------------------------------------------------------------------------- > DISCLAIMER: This e-mail and any attachment (s) is for authorised use by the > intended recipient (s) only. It may contain proprietary material, > confidential > information and/or be subject to the legal privilege of iWave Systems > Technologies Private Limited. If you have received this message in error, > please notify the originator immediately. If you are not the intended > recipient, you are notified that you are strictly prohibited from > retaining, > using, copying, alerting or disclosing the content of this message. > Thank you > for your co-operation. > ------------------------------------------------------------------------------ > > >

4 4

build service results for r4122
by coreboot information 15 Apr '09

15 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4122 to the coreboot repository. This caused the following changes: Change Log: Add missing license headers to v1 AMD AMD-768 code. This has been informally ACKed by Eric W. Biederman <ebiederm(a)xmission.com> on the mailing list, thus committing now. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of digitallogic:msm800sev is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4122&device=msm800sev&vend… Compilation of pcengines:alix1c is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4122&device=alix1c&vendor=… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot April 2009