coreboot February 2009

coreboot@coreboot.org

67 participants
232 discussions

r3931 - in trunk/coreboot-v2/src: arch/i386/boot arch/i386/lib arch/i386/smp boot cpu/amd/model_fxx cpu/x86/lapic cpu/x86/mtrr devices mainboard/tyan/s2895 southbridge/nvidia/ck804
by svn＠coreboot.org 09 Feb '09

09 Feb '09

Author: myles Date: 2009-02-09 18:52:54 +0100 (Mon, 09 Feb 2009) New Revision: 3931 Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c trunk/coreboot-v2/src/arch/i386/boot/tables.c trunk/coreboot-v2/src/arch/i386/lib/cpu.c trunk/coreboot-v2/src/arch/i386/lib/exception.c trunk/coreboot-v2/src/arch/i386/smp/mpspec.c trunk/coreboot-v2/src/boot/elfboot.c trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c trunk/coreboot-v2/src/cpu/x86/lapic/lapic.c trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c trunk/coreboot-v2/src/devices/device_util.c trunk/coreboot-v2/src/devices/pci_device.c trunk/coreboot-v2/src/devices/pci_rom.c trunk/coreboot-v2/src/devices/pnp_device.c trunk/coreboot-v2/src/mainboard/tyan/s2895/irq_tables.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c Log: Remove some warnings, mainly from format strings which didn't match the arguments. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -251,7 +251,7 @@ head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes); head->header_checksum = 0; head->header_checksum = compute_ip_checksum(head, sizeof(*head)); - printk_debug("Wrote coreboot table at: %p - %p checksum %lx\n", + printk_debug("Wrote coreboot table at: %p - %p checksum %x\n", head, rec, head->table_checksum); return (unsigned long)rec; } @@ -415,16 +415,16 @@ low_table_end = (unsigned long)head; } - printk_debug("Adjust low_table_end from 0x%08x to ", low_table_end); + printk_debug("Adjust low_table_end from 0x%08lx to ", low_table_end); low_table_end += 0xfff; // 4K aligned low_table_end &= ~0xfff; - printk_debug("0x%08x \n", low_table_end); + printk_debug("0x%08lx \n", low_table_end); /* The Linux kernel assumes this region is reserved */ - printk_debug("Adjust rom_table_end from 0x%08x to ", rom_table_end); + printk_debug("Adjust rom_table_end from 0x%08lx to ", rom_table_end); rom_table_end += 0xffff; // 64K align rom_table_end &= ~0xffff; - printk_debug("0x%08x \n", rom_table_end); + printk_debug("0x%08lx \n", rom_table_end); #if (HAVE_OPTION_TABLE == 1) { Modified: trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -91,7 +91,7 @@ addr &= ~15; /* This table must be betweeen 0xf0000 & 0x100000 */ - printk_info("Copying Interrupt Routing Table to 0x%08x... ", addr); + printk_info("Copying Interrupt Routing Table to 0x%08lx... ", addr); memcpy((void *)addr, &intel_irq_routing_table, intel_irq_routing_table.size); printk_info("done.\n"); verify_copy_pirq_routing_table(addr); Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -92,7 +92,7 @@ mpc_start &= ~1023; rom_table_start = mpc_start; } - printk_debug("move mptable from 0x%0x to 0x%0x, size 0x%0x\n", low_table_end, mpc_start, mptable_size); + printk_debug("move mptable from 0x%0lx to 0x%0x, size 0x%0x\n", low_table_end, mpc_start, mptable_size); memcpy((unsigned char *)mpc_start, (unsigned char *)low_table_end, mptable_size); smp_write_floating_table_physaddr(low_table_end - SMP_FLOATING_TABLE_LEN, mpc_start); memset((unsigned char *)low_table_end, '\0', mptable_size); Modified: trunk/coreboot-v2/src/arch/i386/lib/cpu.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/cpu.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/arch/i386/lib/cpu.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -225,7 +225,7 @@ info = cpu_info(); - printk_notice("Initializing CPU #%d\n", info->index); + printk_notice("Initializing CPU #%ld\n", info->index); cpu = info->cpu; if (!cpu) { @@ -261,7 +261,7 @@ cpu->ops->init(cpu); } - printk_info("CPU #%d initialized\n", info->index); + printk_info("CPU #%ld initialized\n", info->index); return; } Modified: trunk/coreboot-v2/src/arch/i386/lib/exception.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/exception.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/arch/i386/lib/exception.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -481,10 +481,10 @@ } #else /* !CONFIG_GDB_STUB */ printk_emerg( - "Unexpected Exception: %d @ %02x:%08lx - Halting\n" - "Code: %d eflags: %08lx\n" - "eax: %08lx ebx: %08lx ecx: %08lx edx: %08lx\n" - "edi: %08lx esi: %08lx ebp: %08lx esp: %08lx\n", + "Unexpected Exception: %d @ %02x:%08x - Halting\n" + "Code: %d eflags: %08x\n" + "eax: %08x ebx: %08x ecx: %08x edx: %08x\n" + "edi: %08x esi: %08x ebp: %08x esp: %08x\n", info->vector, info->cs, info->eip, info->error_code, info->eflags, info->eax, info->ebx, info->ecx, info->edx, Modified: trunk/coreboot-v2/src/arch/i386/smp/mpspec.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/smp/mpspec.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/arch/i386/smp/mpspec.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -236,7 +236,7 @@ if ((child->class >> 16) != PCI_BASE_CLASS_BRIDGE) { /* pci device */ - printk_debug("route irq: %s %04x\n", dev_path(child)); + printk_debug("route irq: %s\n", dev_path(child)); for (i = 0; i < 4; i++) smp_write_intsrc(mc, irqtype, irqflag, srcbus, (slot<<2)|i, dstapic, dstirq_x[i]); goto next; @@ -246,7 +246,7 @@ case PCI_CLASS_BRIDGE_PCI: case PCI_CLASS_BRIDGE_PCMCIA: case PCI_CLASS_BRIDGE_CARDBUS: - printk_debug("route irq bridge: %s %04x\n", dev_path(child)); + printk_debug("route irq bridge: %s\n", dev_path(child)); smp_write_intsrc_pci_bridge(mc, irqtype, irqflag, child, dstapic, dstirq_x); } Modified: trunk/coreboot-v2/src/boot/elfboot.c =================================================================== --- trunk/coreboot-v2/src/boot/elfboot.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/boot/elfboot.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -76,7 +76,7 @@ memcpy(n_desc, buff, 2); } if (checksum != cb->ip_checksum) { - printk_err("Image checksum: %04x != computed checksum: %04x\n", + printk_err("Image checksum: %04x != computed checksum: %04lx\n", cb->ip_checksum, checksum); } return checksum == cb->ip_checksum; @@ -500,7 +500,7 @@ /* Zero the extra bytes between middle & end */ if (middle < end) { printk_debug("Clearing Segment: addr: 0x%016lx memsz: 0x%016lx\n", - (unsigned long)middle, end - middle); + (unsigned long)middle, (unsigned long)(end - middle)); /* Zero the extra bytes */ memset(middle, 0, end - middle); @@ -590,7 +590,7 @@ /* Reset to booting from this image as late as possible */ boot_successful(); - printk_debug("Jumping to boot code at 0x%x\n", entry); + printk_debug("Jumping to boot code at 0x%p\n", entry); post_code(0xfe); /* Jump to kernel */ Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -231,7 +231,7 @@ size = (limitk - basek) << 10; addr = map_2M_page(basek >> 11); if (addr == MAPPING_ERROR) { - printk_err("Cannot map page: %x\n", basek >> 11); + printk_err("Cannot map page: %lx\n", basek >> 11); return; } @@ -312,7 +312,7 @@ begink = CONFIG_LB_MEM_TOPK; } - printk_debug("Clearing memory %uK - %uK: ", begink, endk); + printk_debug("Clearing memory %luK - %luK: ", begink, endk); /* Save the normal state */ save_mtrr_state(&mtrr_state); @@ -465,7 +465,9 @@ extern void model_fxx_update_microcode(unsigned cpu_deviceid); int init_processor_name(void); +#if CONFIG_USBDEBUG_DIRECT static unsigned ehci_debug_addr; +#endif void model_fxx_init(device_t dev) { Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/lapic.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -55,7 +55,7 @@ LAPIC_DELIVERY_MODE_NMI) ); - printk_debug(" apic_id: 0x%02x ", lapicid()); + printk_debug(" apic_id: 0x%02lx ", lapicid()); #else /* !NEED_LLAPIC */ /* Only Pentium Pro and later have those MSR stuff */ Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -85,14 +85,14 @@ send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { - printk_err("CPU %d: First apic write timed out. Disabling\n", + printk_err("CPU %ld: First apic write timed out. Disabling\n", apicid); // too bad. - printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR)); + printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); if (lapic_read(LAPIC_ESR)) { printk_err("Try to reset ESR\n"); lapic_write_around(LAPIC_ESR, 0); - printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR)); + printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); } return 0; } @@ -114,7 +114,7 @@ send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { - printk_err("CPU %d: Second apic write timed out. Disabling\n", + printk_err("CPU %ld: Second apic write timed out. Disabling\n", apicid); // too bad. return 0; @@ -345,8 +345,6 @@ /* C entry point of secondary cpus */ void secondary_cpu_init(void) { - unsigned long cpunum; - atomic_inc(&active_cpus); #if SERIAL_CPU_INIT == 1 #if CONFIG_MAX_CPUS>2 Modified: trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -241,7 +241,7 @@ align = max_align; } sizek = 1 << align; - printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\n", + printk_debug("Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n", reg, range_startk >>10, sizek >> 10, (type==MTRR_TYPE_UNCACHEABLE)?"UC": ((type==MTRR_TYPE_WRBACK)?"WB":"Other") Modified: trunk/coreboot-v2/src/devices/device_util.c =================================================================== --- trunk/coreboot-v2/src/devices/device_util.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/devices/device_util.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -467,7 +467,7 @@ #endif } printk_debug( - "%s %02x <- [0x%010Lx - 0x%010Lx] size 0x%08Lx gran 0x%02x %s%s%s\n", + "%s %02lx <- [0x%010Lx - 0x%010Lx] size 0x%08Lx gran 0x%02x %s%s%s\n", dev_path(dev), resource->index, base, end, Modified: trunk/coreboot-v2/src/devices/pci_device.c =================================================================== --- trunk/coreboot-v2/src/devices/pci_device.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/devices/pci_device.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -207,7 +207,7 @@ if (moving == 0) { if (value != 0) { printk_debug( - "%s register %02x(%08x), read-only ignoring it\n", + "%s register %02lx(%08lx), read-only ignoring it\n", dev_path(dev), index, value); } resource->flags = 0; @@ -311,7 +311,7 @@ if (moving == 0) { if (value != 0) { - printk_debug("%s register %02x(%08x), read-only ignoring it\n", + printk_debug("%s register %02lx(%08lx), read-only ignoring it\n", dev_path(dev), index, value); } resource->flags = 0; @@ -459,7 +459,7 @@ /* Make certain the resource has actually been set */ if (!(resource->flags & IORESOURCE_ASSIGNED)) { - printk_err("ERROR: %s %02x %s size: 0x%010Lx not assigned\n", + printk_err("ERROR: %s %02lx %s size: 0x%010Lx not assigned\n", dev_path(dev), resource->index, resource_type(resource), resource->size); @@ -546,7 +546,7 @@ else { /* Don't let me think I stored the resource */ resource->flags &= ~IORESOURCE_STORED; - printk_err("ERROR: invalid resource->index %x\n", + printk_err("ERROR: invalid resource->index %lx\n", resource->index); } report_resource_stored(dev, resource, ""); Modified: trunk/coreboot-v2/src/devices/pci_rom.c =================================================================== --- trunk/coreboot-v2/src/devices/pci_rom.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/devices/pci_rom.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -45,7 +45,7 @@ return NULL; } - printk_debug("rom address for %s = %x\n", dev_path(dev), rom_address); + printk_debug("rom address for %s = %lx\n", dev_path(dev), rom_address); if(!dev->on_mainboard) { /* enable expansion ROM address decoding */ @@ -110,12 +110,12 @@ extern device_t vga_pri; // the primary vga device, defined in device.c if (dev != vga_pri) return NULL; // only one VGA supported #endif - printk_debug("copying VGA ROM Image from 0x%x to 0x%x, 0x%x bytes\n", + printk_debug("copying VGA ROM Image from %p to 0x%x, 0x%x bytes\n", rom_header, PCI_VGA_RAM_IMAGE_START, rom_size); memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, rom_size); return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START); } else { - printk_debug("copying non-VGA ROM Image from 0x%x to 0x%x, 0x%x bytes\n", + printk_debug("copying non-VGA ROM Image from %p to %p, 0x%x bytes\n", rom_header, pci_ram_image_start, rom_size); memcpy(pci_ram_image_start, rom_header, rom_size); pci_ram_image_start += rom_size; Modified: trunk/coreboot-v2/src/devices/pnp_device.c =================================================================== --- trunk/coreboot-v2/src/devices/pnp_device.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/devices/pnp_device.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -103,7 +103,7 @@ static void pnp_set_resource(device_t dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { - printk_err("ERROR: %s %02x %s size: 0x%010Lx not assigned\n", + printk_err("ERROR: %s %02lx %s size: 0x%010Lx not assigned\n", dev_path(dev), resource->index, resource_type(resource), resource->size); @@ -121,7 +121,7 @@ pnp_set_irq(dev, resource->index, resource->base); } else { - printk_err("ERROR: %s %02x unknown resource type\n", + printk_err("ERROR: %s %02lx unknown resource type\n", dev_path(dev), resource->index); return; } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/irq_tables.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/irq_tables.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -72,7 +72,7 @@ addr &= ~15; /* This table must be betweeen 0xf0000 & 0x100000 */ - printk_info("Writing IRQ routing tables to 0x%x...", addr); + printk_info("Writing IRQ routing tables to 0x%lx...", addr); pirq = (void *)(addr); v = (uint8_t *)(addr); Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -314,7 +314,7 @@ continue; base = res->base; end = resource_end(res); - printk_debug("ck804 lpc decode:%s, base=0x%08x, end=0x%08x\r\n", dev_path(child), base, end); + printk_debug("ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end); switch (base) { case 0x3f8: // COM1 reg |= (1 << 0); Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -11,6 +11,7 @@ #include <device/pci_ops.h> #include "ck804.h" +#if CK804_SATA_RESET_FOR_ATAPI static void sata_com_reset(struct device *dev, unsigned reset) // reset = 1 : reset // reset = 0 : clear @@ -21,7 +22,7 @@ base = (uint32_t *) pci_read_config32(dev, 0x24); - printk_debug("base = %08x\r\n", base); + printk_debug("base = %08lx\n", base); if (reset) { *(base + 4) = 0xffffffff; @@ -71,6 +72,7 @@ printk_debug("loop=%d, *(base+0x44)=%08x\r\n", loop, dword); } } +#endif static void sata_init(struct device *dev) { @@ -132,7 +134,7 @@ dword |= 2; pci_write_config32(dev, 0xf8, dword); -#if 0 +#if CK804_SATA_RESET_FOR_ATAPI dword = pci_read_config32(dev, 0xac); dword &= ~((1 << 13) | (1 << 14)); dword |= (1 << 13) | (0 << 14);

1 0

[PATCH] cs5536/nand: Allow setting of NAND timing values in the dts.
by Mart Raudsepp 09 Feb '09

09 Feb '09

cs5536/nand: Allow setting of NAND timing values in the dts. The reset value for NAND timings is the slowest possible for Flash interface. Implement optionally setting it to a different value inside the NAND device. Set it to appropriate values for Artec Group DBE61 and DBE62. This results in a roughly two times quicker read time as measured by hdparm for these boards. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- mainboard/artecgroup/dbe61/dts | 5 ++++- mainboard/artecgroup/dbe62/dts | 5 ++++- southbridge/amd/cs5536/cs5536.c | 18 ++++++++++++++++++ southbridge/amd/cs5536/nand | 4 ++++ 4 files changed, 30 insertions(+), 2 deletions(-) diff --git a/mainboard/artecgroup/dbe61/dts b/mainboard/artecgroup/dbe61/dts index a6995ce..cb46292 100644 --- a/mainboard/artecgroup/dbe61/dts +++ b/mainboard/artecgroup/dbe61/dts @@ -109,8 +109,11 @@ end /* USB Port Power Handling setting. */ pph = "0xf5"; }; - pci@f,1 { + pci@f,1 { /* NAND Flash */ /config/("southbridge/amd/cs5536/nand"); + /* Timings */ + nandf_data = "0x01200120"; + nandf_ctl = "0x00000120"; }; }; }; diff --git a/mainboard/artecgroup/dbe62/dts b/mainboard/artecgroup/dbe62/dts index 8089e79..73dc5a7 100644 --- a/mainboard/artecgroup/dbe62/dts +++ b/mainboard/artecgroup/dbe62/dts @@ -63,8 +63,11 @@ /* USB Port Power Handling setting. */ pph = "0xf5"; }; - pci@f,1 { + pci@f,1 { /* NAND Flash */ /config/("southbridge/amd/cs5536/nand"); + /* Timings */ + nandf_data = "0x01200120"; + nandf_ctl = "0x00000120"; }; }; }; diff --git a/southbridge/amd/cs5536/cs5536.c b/southbridge/amd/cs5536/cs5536.c index 5437937..ea90fd4 100644 --- a/southbridge/amd/cs5536/cs5536.c +++ b/southbridge/amd/cs5536/cs5536.c @@ -109,6 +109,24 @@ static void hide_vpci(u32 vpci_devid) static void nand_phase2(struct device *dev) { if (dev->enabled) { + struct southbridge_amd_cs5536_nand_config *nand; + struct msr msr; + + /* Set up timings */ + nand = (struct southbridge_amd_cs5536_nand_config *)dev->device_configuration; + msr.hi = 0x0; + + if (nand->nandf_data) { + msr.lo = nand->nandf_data; + wrmsr(MDD_NANDF_DATA, msr); + printk(BIOS_DEBUG, "NANDF_DATA set to 0x%08x\n", msr.lo); + } + if (nand->nandf_ctl) { + msr.lo = nand->nandf_ctl; + wrmsr(MDD_NANDF_CTL, msr); + printk(BIOS_DEBUG, "NANDF_CTL set to 0x%08x\n", msr.lo); + } + /* Tell VSA to use FLASH PCI header. Not IDE header. */ hide_vpci(0x800079C4); } diff --git a/southbridge/amd/cs5536/nand b/southbridge/amd/cs5536/nand index 69f4fa4..62c28b0 100644 --- a/southbridge/amd/cs5536/nand +++ b/southbridge/amd/cs5536/nand @@ -20,4 +20,8 @@ { device_operations = "cs5536_nand"; + + /* NAND timings per data book and NAND chip on board. 0x0 leaves to reset value. */ + nandf_data = "0x0"; + nandf_ctl = "0x0"; }; -- 1.6.1.1

4 7

[PATCH] cs5536: Fix NAND Flash setup.
by Mart Raudsepp 09 Feb '09

09 Feb '09

cs5536: Fix NAND Flash setup. A NAND device may never be mapped above 0xEFFFFFFF, as these addresses never reach the NAND controller. Only NAND controller, as the only DIVIL component that is allowed to be memory mapped, is affected - other Geode LX and CS5536 peripherals (that are separate GLIU devices outside DIVIL component) can use addresses above that limit (see in-code comment for details). In combination with a new VSA2 version 1.02 or newer, this makes NAND flash finally work in coreboot v3. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Signed-off-by: Anti Sullin <anti.sullin(a)artecdesign.ee> --- southbridge/amd/cs5536/cs5536.c | 22 +++++++++++++++++++++- 1 files changed, 21 insertions(+), 1 deletions(-) diff --git a/southbridge/amd/cs5536/cs5536.c b/southbridge/amd/cs5536/cs5536.c index 729cb7e..5437937 100644 --- a/southbridge/amd/cs5536/cs5536.c +++ b/southbridge/amd/cs5536/cs5536.c @@ -114,6 +114,26 @@ static void nand_phase2(struct device *dev) } } +static void nand_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + + /* All memory accesses in the range of 0xF0000000 - 0xFFFFFFFF routed to + * Diverse Integration Logic (DIVIL) get always sent to the device inside + * DIVIL as set in DIVIL_BALL_OPTS PRI_BOOT_LOC and SEC_BOOT_LOC bits + * (see CS5536 data book chapter 6.6.2.10 DIVIL_BALL_OPTS PRI_BOOT_LOC + * description). + * The virtual PCI address limit test gives us a false upper limit of + * 0xFFFFFFFF for this device, but we do not want NAND Flash to be using + * memory addresses 0xF0000000 and above as those accesses would end up + * somewhere else instead. Therefore if VSA2 gave us a MMIO resource for + * NAND Flash, patch this (fixed) resources higher bound to 0xEFFFFFFF. + */ + if ((dev->resources >= 1) && (dev->resource[0].flags & IORESOURCE_MEM) && + (dev->resource[0].limit > 0xefffffff)) + dev->resource[0].limit = 0xefffffff; +} + /** * Power button setup. * @@ -737,7 +757,7 @@ struct device_operations cs5536_nand = { .constructor = default_device_constructor, .phase2_fixup = nand_phase2, .phase3_scan = 0, - .phase4_read_resources = pci_dev_read_resources, + .phase4_read_resources = nand_read_resources, .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = 0, /* No Option ROMs */ -- 1.6.1.1

2 2

r1125 - coreboot-v3/southbridge/amd/cs5536
by svn＠coreboot.org 09 Feb '09

09 Feb '09

Author: mraudsepp Date: 2009-02-09 17:10:58 +0100 (Mon, 09 Feb 2009) New Revision: 1125 Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c Log: cs5536: Fix NAND Flash setup. A NAND device may never be mapped above 0xEFFFFFFF, as these addresses never reach the NAND controller. Only NAND controller, as the only DIVIL component that is allowed to be memory mapped, is affected - other Geode LX and CS5536 peripherals (that are separate GLIU devices outside DIVIL component) can use addresses above that limit (see in-code comment for details). In combination with a new VSA2 version 1.02 or newer, this makes NAND flash finally work in coreboot v3. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Signed-off-by: Anti Sullin <anti.sullin(a)artecdesign.ee> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2009-02-09 13:40:10 UTC (rev 1124) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2009-02-09 16:10:58 UTC (rev 1125) @@ -114,6 +114,26 @@ } } +static void nand_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + + /* All memory accesses in the range of 0xF0000000 - 0xFFFFFFFF routed to + * Diverse Integration Logic (DIVIL) get always sent to the device inside + * DIVIL as set in DIVIL_BALL_OPTS PRI_BOOT_LOC and SEC_BOOT_LOC bits + * (see CS5536 data book chapter 6.6.2.10 DIVIL_BALL_OPTS PRI_BOOT_LOC + * description). + * The virtual PCI address limit test gives us a false upper limit of + * 0xFFFFFFFF for this device, but we do not want NAND Flash to be using + * memory addresses 0xF0000000 and above as those accesses would end up + * somewhere else instead. Therefore if VSA2 gave us a MMIO resource for + * NAND Flash, patch this (fixed) resources higher bound to 0xEFFFFFFF. + */ + if ((dev->resources >= 1) && (dev->resource[0].flags & IORESOURCE_MEM) && + (dev->resource[0].limit > 0xefffffff)) + dev->resource[0].limit = 0xefffffff; +} + /** * Power button setup. * @@ -737,7 +757,7 @@ .constructor = default_device_constructor, .phase2_fixup = nand_phase2, .phase3_scan = 0, - .phase4_read_resources = pci_dev_read_resources, + .phase4_read_resources = nand_read_resources, .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = 0, /* No Option ROMs */

1 0

r1124 - coreboot-v3/southbridge/amd/cs5536
by svn＠coreboot.org 09 Feb '09

09 Feb '09

Author: mraudsepp Date: 2009-02-09 14:40:10 +0100 (Mon, 09 Feb 2009) New Revision: 1124 Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.h Log: cs5536: Use NANDF_CTL for NAND Flash Control Timing register constant 5140001Ch define, as in data book, not mis-spelled NADF_CNTL Trivial: constant currently not used anywhere. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.h =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.h 2009-01-23 22:18:24 UTC (rev 1123) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.h 2009-02-09 13:40:10 UTC (rev 1124) @@ -147,7 +147,7 @@ #define MDD_NORF_T01 (MSR_SB_MDD + 0x19) #define MDD_NORF_T23 (MSR_SB_MDD + 0x1A) #define MDD_NANDF_DATA (MSR_SB_MDD + 0x1B) -#define MDD_NADF_CNTL (MSR_SB_MDD + 0x1C) +#define MDD_NANDF_CTL (MSR_SB_MDD + 0x1C) #define MDD_AC_DMA (MSR_SB_MDD + 0x1E) #define MDD_KEL_CNTRL (MSR_SB_MDD + 0x1F) #define MDD_IRQM_YLOW (MSR_SB_MDD + 0x20)

1 0

Re: [coreboot] [PATCH] split tar & cpio
by Robert Millan 07 Feb '09

07 Feb '09

On Sat, Nov 08, 2008 at 05:17:15PM +0100, Robert Millan wrote: > > Hi, > > I thought it would be a good idea to split tar & cpio into separate modules > to save some space and make things easier to figure out for the users. I > managed to do this without duplicating code, with a bit of pre-processor > magic. > > The saved size is not much, though (~400 bytes). But users looking for tar > will find it more easily. How do you feel about this? Is it worth it? Committed. coreboot users: if you're using tar to generate GRUB's memdisk image, with latest svn you need to include tar.mod instead of cpio.mod. -- Robert Millan The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and how) you may access your data; but nobody's threatening your freedom: we still allow you to remove your data and not access it at all."

1 0

FW: Two test result(linux+2G-RAM>10minutes and install ubuntu8.10) of vx800 patch
by JasonZhao＠viatech.com.cn 07 Feb '09

07 Feb '09

My VX800 bug of "boot linux with 2G mem >10 minutes" has been proved to be the problem of MTRR setting. Thanks for Carldani, Rudolf and Bari. 1 The root cause is: 1) The free memory I report to coreboot through ram_resource is [0, 1983M=2G-64M(Framebuffer)-1M(TOP 1M SM Memory)]. If I report [0, 1984M=2G-64M(Framebuffer)], then all is OK. 2) The src/cpu/x86/mtrr.c setting result of [0,1983M] is: reg00: base=0x00000000 ( 0MB), size=1024MB: write-back, count=1 reg01: base=0x40000000 (1024MB), size= 512MB: write-back, count=1 reg02: base=0x60000000 (1536MB), size= 256MB: write-back, count=1 reg03: base=0x70000000 (1792MB), size= 128MB: write-back, count=1 reg04: base=0x78000000 (1920MB), size= 32MB: write-back, count=1 reg05: base=0x7a000000 (1952MB), size= 16MB: write-back, count=1 reg06: base=0x7b000000 (1968MB), size= 8MB: write-back, count=1 reg07: base=0x7b800000 (1976MB), size= 4MB: write-back, count=1 This setting make the last 3MB is uncached due to the lack of MTRR registers. And It seems that the last 3MB is frequently used by linux with kernel before(2.6.25.19), so the OS become slow. However XP and the linux with newest kernel (2.6.26.6-49.fc8) are not disturbed by the uncache of last 3MB. The mtrr.c setting of [0,1984M] is: reg00: base=0x00000000 ( 0MB), size=1024MB: write-back, count=1 reg01: base=0x40000000 (1024MB), size= 512MB: write-back, count=1 reg02: base=0x60000000 (1536MB), size= 256MB: write-back, count=1 reg03: base=0x70000000 (1792MB), size= 128MB: write-back, count=1 reg04: base=0x78000000 (1920MB), size= 64MB: write-back, count=1 all of memory area is cached, and all OS run at a good speed. 2 So we need improve mtrr.c to make it can treat with such input[0,1983M]. The legacybios handle my [0,1983] like this Cache [0,2048M] Unchace [1983M, 1984M] size=1M Uncache [1984M,2048M] size =64M. I guess the legacybios compare the number of '1' and '0' in 1983 to decide how to use minimum number of MTRR. Carldaniel, you said on irc that mtrr.c also have the ability like legacybios(cache 2G,then uncache some area of 2G). But I didn't find any logic like that in mtrr.c. 3 And Stefan, your cx700 code will meet the same problem. Since the cx700's northbridge.c report the memory size in the same way of [0,xxxx-1M(TOP 1M SM Memory)]. The last 1M will also confuse the mtrr.c. -jasonzhao -----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] Sent: Saturday, January 24, 2009 7:53 PM To: Jason Zhao Cc: r.marek(a)assembler.cz Subject: Re: [coreboot] Two test result(linux+2G-RAM>10minutes and install ubuntu8.10) of vx800 patch Hi Jason, thanks for the dumps. On 24.01.2009 08:08, JasonZhao(a)viatech.com.cn wrote: > Carl and ruik: > Here is some more result of acpidump, /proc/mtrr and /proc/meminfo. > Some explanation of my memory using in coreboot: > [topmem-64,tompmem] as framebuffer, > [topmem-64M-64k,topmem-64M] as coreboot-table (In > tables.c:rom_table_start = (*mem_top) - 64*1024;). > It is a bit strange that the DSDTs are identical for both memory configurations. The following parts of the code are suspicious: > Method (_CRS, 0, NotSerialized) > { > Name (BUF0, ResourceTemplate () > { > [...] > DWordMemory (ResourceProducer, PosDecode, > MinFixed, MaxFixed, Cacheable, ReadWrite, > 0x00000000, // Granularity > 0x80000000, // Range Minimum > 0xBFFFFFFF, // Range Maximum > 0x00000000, // Translation Offset > 0x40000000, // Length > ,, _Y00, AddressRangeMemory, TypeStatic) > }) That address range is always the same, even if you only have 512M memory. Why? Will it cause problems if you have 3G memory? And our MTRR setup is incomplete for the 2G case. The last 4 MB are uncached because we run out of MTRR registers. That will cause an extreme slowdown during boot. I think the MTRR setup explains almost everything. Regards, Carl-Daniel -- http://www.hailfinger.org/

6 12

intel p6 core msrs
by Holger Hesselbarth 07 Feb '09

07 Feb '09

just for a start here is my first real contribution. here are some answers to questions that Peter Stuge asked.. >> { 17, 5, "L2PBS", "L2 size per bank", PRESENT_DEC, { >> { MSR1(0), "128 kbytes" }, >> { MSR1(1), "256 kbytes" }, >> { MSR1(2), "512 kbytes" }, >> { MSR1(4), "1 Mbytes" }, >> { MSR1(8), "2 Mbytes" }, >> { MSR1(16), "4 Mbytes" }, >> { BITVAL_EOT } >> }}, > > Hmm, can you explain this field a little more? Will only one bit ever > be set at a time? there's no real info on this in the intel documents i have. welcome to intel's msr mystery world :( but based on the available processors with p6 core we can assume this: only one bit will be set or none. the intel celerons have 128kB L2 cache unless they are tualatin cores, then they'll have 256kB cache. all intel pentium ii have 512kB L2 cache. all pentium iii processors have 512kB L2 cache unless they are coppermine, then they'll have 256kB. pentium iii tualatins have 512kB L2 cache again. xeons with drake core(derived from pentium ii deschutes) have 512kB, 1MB or 2MB cache. tanner (derived from pentium iii katmai) core xeons have 1MB or 2MB cache while the cascades cores (derived from pentium iii coppermine) have 256kB (!!!) or 2MB cache. i hope you are not too confused by now. >> { 4, 4, "L2LAT", "L2 latency", PRESENT_DEC, NOBITS }, > > ..and here. Btw, what unit is this latency expressed in? the latency is expressed in intel mystery units. since the docs don't say anything about the units, my guess is the following. it's in units of cycles of the bus speed of the L2 cache bus. on some of the pentium iis and pentium iiis the L2 cache was off-chip but on-module. there the latency makes sense and it was set to 5 (according to intel's recommendations?). on later models the cache went on-chip and the L2 cache latency went down to 1. on abit slot 1 boards the cache latency could be adjusted, too. > A target definition has to be added to msrtool.c as well. A super > simple entry in struct targetdef alltargets[]. i called it P6 since that's what Intel calls this specific processor core in their offical documents. and this msr declaration is for P6 cores only. some tme later it should contain all msrs from the P6 core. but you are free to suggest a better name :) Holger Index: p6.c =================================================================== --- p6.c (revision 0) +++ p6.c (revision 0) @@ -0,0 +1,133 @@ +/* + * This file is part of msrtool. + * + * Copyright (c) 2009 Holger Hesselbarth <popkonserve(a)gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * references: + * http://www.vortex.prodigynet.co.uk/x86test/platform_id.html + */ + +#include "msrtool.h" + +int p6_probe(const struct targetdef *target) { + struct cpuid_t *id = cpuid(); + return ((06 == id->family) && (0 == id->ext_family)); +} + +const struct msrdef p6_msrs[] = { + { 0x00000017, MSRTYPE_RO, MSR2(0, 0), "IA32_PLATFORM_ID", "Platform ID", { + { 63, 3, RESERVED }, + { 60, 1, "CLKRATIO", "Clock Frequency Ratio", PRESENT_DEC, { + { MSR1(0), "" }, + { MSR1(1), "" }, + { BITVAL_EOT } + }}, + { 59, 3, RESERVED }, + { 56, 3, "L2DIS", "L2 cache latency", PRESENT_DEC, NOBITS }, + { 52, 3, "PID", "Platform ID", PRESENT_DEC, { + { MSR1(0), "Processor Flag 0" }, + { MSR1(1), "Processor Flag 1" }, + { MSR1(2), "Processor Flag 2" }, + { MSR1(3), "Processor Flag 3" }, + { MSR1(4), "Processor Flag 4" }, + { MSR1(5), "Processor Flag 5" }, + { MSR1(6), "Processor Flag 6" }, + { MSR1(7), "Processor Flag 7" }, + { BITVAL_EOT } + }}, + { 49, 50, RESERVED }, + { BITS_EOT } + }}, + + { 0x0000011E, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_CTL3", "Control register 3", { + { 63, 38, RESERVED }, + { 25, 1, "CBF", "Cache Bus Fraction", PRESENT_DEC, { + { MSR1(0), "same as core speed" }, + { MSR1(1), "half of core speed" }, + { BITVAL_EOT } + }}, + { 24, 1, RESERVED }, + { 23, 1, "L2DIS", "L2 cache hardware", PRESENT_DEC, { + { MSR1(0), "enabled" }, + { MSR1(1), "disabled" }, + { BITVAL_EOT } + }}, + { 22, 3, "L2ADR", "L2 physical address range", PRESENT_DEC, { + { MSR1(0), "512 Mbytes" }, + { MSR1(1), "1 Gbytes" }, + { MSR1(2), "2 Gbytes" }, + { MSR1(3), "4 Gbytes" }, + { MSR1(4), "8 Gbytes" }, + { MSR1(5), "16 Gbytes" }, + { MSR1(6), "32 Gbytes" }, + { MSR1(7), "64 Gbytes" }, + { BITVAL_EOT } + }}, + { 19, 1, RESERVED }, + { 18, 1, "L2SCHK", "L2 state error checking", PRESENT_DEC, { + { MSR1(0), "disabled" }, + { MSR1(1), "enabled" }, + { BITVAL_EOT } + }}, + { 17, 5, "L2PBS", "L2 size per bank", PRESENT_DEC, { + { MSR1(0), "128 kbytes" }, + { MSR1(1), "256 kbytes" }, + { MSR1(2), "512 kbytes" }, + { MSR1(4), "1 Mbytes" }, + { MSR1(8), "2 Mbytes" }, + { MSR1(16), "4 Mbytes" }, + { BITVAL_EOT } + }}, + { 12, 2, "L2BAN", "Number of L2 banks", PRESENT_DEC, NOBITS }, + { 10, 2, "L2WAY", "L2 Associativity", PRESENT_DEC, { + { MSR1(0), "Direct Mapped" }, + { MSR1(1), "2 Way" }, + { MSR1(2), "4 Way" }, + { MSR1(3), "reserved" }, + { BITVAL_EOT } + }}, + { 8, 1, "L2EN", "L2 status", PRESENT_DEC, { + { MSR1(0), "disabled" }, + { MSR1(1), "enabled" }, + { BITVAL_EOT } + }}, + { 7, 1, "L2CRTN", "CRTN Parity Check", PRESENT_DEC, { + { MSR1(0), "disabled" }, + { MSR1(1), "enabled" }, + { BITVAL_EOT } + }}, + { 6, 1, "L2ADDR", "Address Parity Check", PRESENT_DEC, { + { MSR1(0), "disabled" }, + { MSR1(1), "enabled" }, + { BITVAL_EOT } + }}, + { 5, 1, "L2ECC", "ECC Check", PRESENT_DEC, { + { MSR1(0), "disabled" }, + { MSR1(1), "enabled" }, + { BITVAL_EOT } + }}, + { 4, 4, "L2LAT", "L2 latency", PRESENT_DEC, NOBITS }, + { 0, 1, "L2CONF", "L2 configured", PRESENT_DEC, { + { MSR1(0), "disabled" }, + { MSR1(1), "enabled" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { MSR_EOT } +}; Index: msrtool.c =================================================================== --- msrtool.c (revision 3930) +++ msrtool.c (working copy) @@ -42,6 +42,7 @@ static struct targetdef alltargets[] = { { "geodelx", "AMD Geode(tm) LX", geodelx_probe, geodelx_msrs }, { "cs5536", "AMD Geode(tm) CS5536", cs5536_probe, cs5536_msrs }, + { "p6", "Intel(c) P6 core", p6_probe, p6_msrs }, { TARGET_EOT } };

1 0

kontron 9865lcd
by ron minnich 06 Feb '09

06 Feb '09

output with X right now is terrible. If anyone was an xconfig file that works with these boards, let me know. We're just trying to boot with standard bios first. thanks ron

2 1

intel p6 core msrs
by Holger Hesselbarth 06 Feb '09

06 Feb '09

1 0

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coreboot February 2009