coreboot February 2009

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r3950 - trunk/payloads/libpayload/bin
by svn＠coreboot.org 15 Feb '09

15 Feb '09

Author: rminnich Date: 2009-02-16 00:32:57 +0100 (Mon, 16 Feb 2009) New Revision: 3950 Modified: trunk/payloads/libpayload/bin/lpgcc Log: This is a safety measure, since the shipping buildrom fails badly at present. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/payloads/libpayload/bin/lpgcc =================================================================== --- trunk/payloads/libpayload/bin/lpgcc 2009-02-15 02:53:18 UTC (rev 3949) +++ trunk/payloads/libpayload/bin/lpgcc 2009-02-15 23:32:57 UTC (rev 3950) @@ -27,7 +27,16 @@ ## SUCH DAMAGE. # GCC wrapper for libpayload +# let's not recurse. +# This is a hack, I know, but it makes sure that really simple user errors +# don't fork-bomb your machine. +b=`basename $CC` +if [ "$b" = "lpgcc" ]; then +CC="" +fi + + if [ "$CC" != "" ]; then DEFAULT_CC=$CC else

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[patch][v3] Improve stage1 MTRR setup
by Marc Jones 15 Feb '09

15 Feb '09

Improve the setup of MTRRs in stage1 to handle alignment and power of 2 size calculations. Signed-off-by: Marc Jones <marcj303(a)gmail.com>

2 2

r1133 - in coreboot-v3: arch/x86 arch/x86/amd/k8 include/arch/x86
by svn＠coreboot.org 15 Feb '09

15 Feb '09

Author: mjones Date: 2009-02-15 19:12:34 +0100 (Sun, 15 Feb 2009) New Revision: 1133 Modified: coreboot-v3/arch/x86/amd/k8/stage1.c coreboot-v3/arch/x86/stage1_mtrr.c coreboot-v3/include/arch/x86/mtrr.h Log: Improve the setup of MTRRs in stage1 to handle alignment and power of 2 size calculations. Signed-off-by: Marc Jones <marcj303(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/amd/k8/stage1.c =================================================================== --- coreboot-v3/arch/x86/amd/k8/stage1.c 2009-02-13 11:00:21 UTC (rev 1132) +++ coreboot-v3/arch/x86/amd/k8/stage1.c 2009-02-15 18:12:34 UTC (rev 1133) @@ -38,6 +38,9 @@ void set_mtrr_ram_access(void) { struct msr msr; + u8 mtrr_reg; + u32 mem_sizek; + u32 mem_basek; disable_cache(); @@ -68,20 +71,31 @@ stage1_set_fix_mtrr(MTRRfix4K_F8000_MSR, MTRR_READ_MEM | MTRR_WRITE_MEM | MTRR_TYPE_WRBACK); - /* 1MB - TOM */ + /* 0MB - TOM */ + /* The fixed MTRRS will override 0MB-1MB but because the size needs to + * be power of two aligned we want the base to be power of two aligned(0). + * Otherwise we will use all the MTRRs up. + */ msr = rdmsr(TOP_MEM); - stage1_set_var_mtrr_x(0, 0x00100000, 0x0, msr.lo, msr.hi, MTRR_TYPE_WRBACK); + mem_sizek = stage1_resk((msr.hi << 32) | msr.lo); + mem_basek = 0x0; + mtrr_reg = 0; + mtrr_reg = stage1_range_to_mtrr(mtrr_reg, mem_basek, mem_sizek, + MTRR_TYPE_WRBACK, CPU_ADDR_BITS); /* System ROM (Assume 1MB) */ - stage1_set_var_mtrr(1, 0xFFFFFFFF - (u32)((CONFIG_COREBOOT_ROMSIZE_KB << 10) - 1), - CONFIG_COREBOOT_ROMSIZE_KB << 10, MTRR_TYPE_WRTHROUGH); + mtrr_reg = stage1_range_to_mtrr(mtrr_reg, + (u32)(0xFFFFFFFF >> 10) - (u32)(CONFIG_COREBOOT_ROMSIZE_KB - 1), + CONFIG_COREBOOT_ROMSIZE_KB, MTRR_TYPE_WRBACK, CPU_ADDR_BITS); /* 4GB - TOM2 */ msr = rdmsr(SYSCFG_MSR); if (msr.lo & SYSCFG_MSR_TOM2En) { msr = rdmsr(TOP_MEM2); - stage1_set_var_mtrr_x(2, 0x0, 0x00000001, msr.lo, msr.hi, - MTRR_TYPE_WRBACK); + mem_sizek = stage1_resk((msr.hi << 32) | msr.lo); + mem_basek = (0xFFFFFFFF >> 10) + 1; /* 4GB */ + mtrr_reg = stage1_range_to_mtrr(mtrr_reg, mem_basek, mem_sizek, + MTRR_TYPE_WRBACK, CPU_ADDR_BITS); } /* Enable Fixed and Variable MTRRs MSRs*/ Modified: coreboot-v3/arch/x86/stage1_mtrr.c =================================================================== --- coreboot-v3/arch/x86/stage1_mtrr.c 2009-02-13 11:00:21 UTC (rev 1132) +++ coreboot-v3/arch/x86/stage1_mtrr.c 2009-02-15 18:12:34 UTC (rev 1133) @@ -14,49 +14,49 @@ #include <msr.h> #include <mtrr.h> -void disable_var_mtrr(unsigned int reg) +#if 1 +#define BIOS_MTRRS 6 +#define OS_MTRRS 2 +#else +#define BIOS_MTRRS 8 +#define OS_MTRRS 0 +#endif +#define MTRRS (BIOS_MTRRS + OS_MTRRS) + +/* fms: find most sigificant bit set, stolen from Linux Kernel Source. */ +static inline u32 fms(u32 x) { - /* The invalid bit is kept in the mask so we simply - * clear the relevent mask register to disable a - * range. - */ - struct msr zero; - zero.lo = zero.hi = 0; - wrmsr(MTRRphysMask_MSR(reg), zero); + int r; + + __asm__("bsrl %1,%0\n\t" + "jnz 1f\n\t" + "movl $0,%0\n" + "1:" : "=r" (r) : "g" (x)); + return r; } -void stage1_set_var_mtrr( - unsigned long reg, unsigned long base, unsigned long size, unsigned long type) +/* fls: find least sigificant bit set */ +static inline u32 fls(u32 x) +{ + int r; -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - /* FIXME: It only support 4G less range */ - struct msr basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.lo = ~(size - 1) | 0x800; - maskm.hi = (1<<(CPU_ADDR_BITS-32))-1; - wrmsr(MTRRphysMask_MSR(reg), maskm); + __asm__("bsfl %1,%0\n\t" + "jnz 1f\n\t" + "movl $32,%0\n" + "1:" : "=r" (r) : "g" (x)); + return r; } -void stage1_set_var_mtrr_x( - unsigned long reg, u32 base_lo, u32 base_hi, u32 size_lo, u32 size_hi, unsigned long type) - +u32 stage1_resk(u64 value) { - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - struct msr basem, maskm; - basem.lo = (base_lo & 0xfffff000) | type; - basem.hi = base_hi & ((1<<(CPU_ADDR_BITS-32))-1); - wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.hi = (1<<(CPU_ADDR_BITS-32))-1; - if(size_lo) { - maskm.lo = ~(size_lo - 1) | 0x800; - } else { - maskm.lo = 0x800; - maskm.hi &= ~(size_hi - 1); + u32 resultk; + if (value < (1ULL << 42)) { + resultk = value >> 10; } - wrmsr(MTRRphysMask_MSR(reg), maskm); + else { + resultk = 0xffffffff; + } + return resultk; } /* Sets the entire fixed mtrr to a cache type. */ @@ -77,14 +77,114 @@ msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; wrmsr(SYSCFG_MSR, msr); +} +/* Set a variable MTRR, comes from linux kernel source + * use stage1_range_to_mtrr() to set variable MTRRs. + */ +static void stage1_set_var_mtrr(u8 reg, u32 basek, u32 sizek, + u8 type, u32 address_bits) +{ + struct msr base, mask; + u32 address_mask_high; + + if (reg >= MTRRS) { + printk(BIOS_ERR,"Requested MTRR is out of range!\n"); + return; + } + + if (sizek == 0) { + struct msr zero; + zero.lo = zero.hi = 0; + + disable_cache(); /* disable/enable cache when setting MTRRs */ + + /* The invalid bit is kept in the mask, so we simply clear the + relevant mask register to disable a range. */ + wrmsr (MTRRphysMask_MSR(reg), zero); + + enable_cache(); + return; + } + + + address_mask_high = ((1u << (address_bits - 32u)) - 1u); + + base.hi = basek >> 22; + base.lo = basek << 10; + + printk(BIOS_SPEW, "ADDRESS_MASK_HIGH=%#x\n", address_mask_high); + + if (sizek < 4*1024*1024) { + mask.hi = address_mask_high; + mask.lo = ~((sizek << 10) -1); + } + else { + mask.hi = address_mask_high & (~((sizek >> 22) -1)); + mask.lo = 0; + } + + disable_cache(); /* disable/enable cache when setting MTRRs */ + + /* Bit 32-35 of MTRRphysMask should be set to 1 */ + base.lo |= type; + mask.lo |= 0x800; + wrmsr (MTRRphysBase_MSR(reg), base); + wrmsr (MTRRphysMask_MSR(reg), mask); + + enable_cache(); } +/* Set a memory range to variable MTRRs. + * This handles the power of 2 alignment requirement. + */ +u8 stage1_range_to_mtrr(u8 reg, u32 range_startk, u32 range_sizek, + u8 type, u32 address_bits) +{ + if (!range_sizek) { + printk(BIOS_SPEW, "Zero-sized MTRR range @%dKB\n", range_startk); + return reg; + } + + if (reg >= BIOS_MTRRS) { + printk(BIOS_ERR, "ERROR: Out of MTRRs for base: %4dMB, range: %dMB, type %s\n", + range_startk >>10, range_sizek >> 10, + (type==MTRR_TYPE_UNCACHEABLE)?"UC": + ((type==MTRR_TYPE_WRBACK)?"WB":"Other") ); + return reg; + } + + while(range_sizek) { + u32 max_align, align; + u32 sizek; + /* Compute the maximum size I can make a range */ + max_align = fls(range_startk); + align = fms(range_sizek); + if (align > max_align) { + align = max_align; + } + sizek = 1 << align; + printk(BIOS_DEBUG,"Setting variable MTRR %d, base: %dKB, range: %dKB, type %s\n", + reg, range_startk, sizek, + (type==MTRR_TYPE_UNCACHEABLE)?"UC": + ((type==MTRR_TYPE_WRBACK)?"WB":"Other") + ); + stage1_set_var_mtrr(reg++, range_startk, sizek, type, address_bits); + range_startk += sizek; + range_sizek -= sizek; + if (reg >= BIOS_MTRRS) { + printk(BIOS_ERR, "Out of variable MTRRs!\n"); + break; + } + } + return reg; +} + void cache_cbmem(int type) { - /* Enable caching for 0 - 1MB using variable mtrr */ + /* Enable caching for 0 - 1MB(CONFIG_CBMEMK) using variable mtrr */ disable_cache(); - stage1_set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, type); + stage1_range_to_mtrr(0, 0, CONFIG_CBMEMK, MTRR_TYPE_WRBACK, CPU_ADDR_BITS); enable_cache(); } @@ -119,7 +219,8 @@ /* enable write through caching so we can do execute in place * on the flash rom. */ - stage1_set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK); + stage1_range_to_mtrr(1, 0, XIP_ROM_BASE >> 10, XIP_ROM_SIZE >> 10, + MTRR_TYPE_WRBACK, CPU_ADDR_BITS); #endif #endif Modified: coreboot-v3/include/arch/x86/mtrr.h =================================================================== --- coreboot-v3/include/arch/x86/mtrr.h 2009-02-13 11:00:21 UTC (rev 1132) +++ coreboot-v3/include/arch/x86/mtrr.h 2009-02-15 18:12:34 UTC (rev 1133) @@ -35,13 +35,11 @@ void x86_setup_var_mtrrs(unsigned address_bits); void x86_setup_mtrrs(unsigned address_bits); int x86_mtrr_check(void); -void stage1_set_var_mtrr(unsigned long reg, unsigned long base, - unsigned long size, unsigned long type); void stage1_set_fix_mtrr(u32 reg, u8 type); -void stage1_set_var_mtrr_x(unsigned long reg, u32 base_lo, u32 base_hi, - u32 size_lo, u32 size_hi, unsigned long type); +u8 stage1_range_to_mtrr(u8 reg, u32 range_startk, u32 range_sizek, + u8 type, u32 address_bits); +u32 stage1_resk(u64 value); - #endif #endif /* ARCH_X86_MTRR_H */

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Trac reminder: list of new ticket(s)
by coreboot tracker 15 Feb '09

15 Feb '09

1 0

r3949 build service
by coreboot information 14 Feb '09

14 Feb '09

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3949 to the coreboot source repository and caused the following changes: Change Log: - Fix up amd pistachio and dbm690t. - make uma_memory_base and uma_memory_size uint64_t as they may be 64bit BARs on some platforms. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:dbm690t has been fixed Compilation of amd:pistachio has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] Warn if we run out of MTRRs
by Carl-Daniel Hailfinger 14 Feb '09

14 Feb '09

Print a loud warning message if we run out of MTRRs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> ================================================================== --- corebootv2/src/cpu/x86/mtrr/mtrr.c (revision 3935) +++ corebootv2/src/cpu/x86/mtrr/mtrr.c (working copy) @@ -228,9 +228,14 @@ unsigned long range_startk, unsigned long range_sizek, unsigned long next_range_startk, unsigned char type, unsigned address_bits) { - if (!range_sizek || (reg >= BIOS_MTRRS)) { + if (!range_sizek) { + printk_debug("range_to_mtrr called for empty range\n"); return reg; } + if (reg >= BIOS_MTRRS) { + printk_emerg("Running out of variable MTRRs!\n"); + return reg; + } while(range_sizek) { unsigned long max_align, align; unsigned long sizek; @@ -249,8 +254,10 @@ set_var_mtrr(reg++, range_startk, sizek, type, address_bits); range_startk += sizek; range_sizek -= sizek; - if (reg >= BIOS_MTRRS) + if (reg >= BIOS_MTRRS) { + printk_emerg("Running out of variable MTRRs!\n"); break; + } } return reg; } -- http://www.hailfinger.org/

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r3949 - in trunk/coreboot-v2/src: mainboard/amd/dbm690t mainboard/amd/pistachio southbridge/amd/rs690
by svn＠coreboot.org 14 Feb '09

14 Feb '09

Author: stepan Date: 2009-02-15 03:53:18 +0100 (Sun, 15 Feb 2009) New Revision: 3949 Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c Log: - Fix up amd pistachio and dbm690t. - make uma_memory_base and uma_memory_size uint64_t as they may be 64bit BARs on some platforms. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2009-02-14 16:23:16 UTC (rev 3948) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2009-02-15 02:53:18 UTC (rev 3949) @@ -44,7 +44,7 @@ #define ADT7461_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) -unsigned long uma_memory_start, uma_memory_size; +uint64_t uma_memory_base, uma_memory_size; /******************************************************** * dbm690t uses a BCM5789 as on-board NIC. @@ -235,14 +235,14 @@ break; } - uma_memory_start = msr.lo - uma_memory_size; /* TOP_MEM1 */ - printk_info("%s: uma size 0x%08x, memory start 0x%08x\n", - __func__, uma_memory_size, uma_memory_start); + uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + printk_info("%s: uma size 0x%08lx, memory start 0x%08lx\n", + __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ #else uma_memory_size = 0x8000000; /* 128M recommended UMA */ - uma_memory_start = 0x38000000; /* 1GB system memory supposed */ + uma_memory_base = 0x38000000; /* 1GB system memory supposed */ #endif enable_onboard_nic(); @@ -256,10 +256,10 @@ * in some circumstances we want the memory mentioned as reserved. */ #if (CONFIG_GFXUMA == 1) - printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n", - uma_memory_start, uma_memory_size); + printk_info("uma_memory_base=0x%lx, uma_memory_size=0x%lx \n", + uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, - uma_memory_start, uma_memory_size); + uma_memory_base, uma_memory_size); #endif } Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c 2009-02-14 16:23:16 UTC (rev 3948) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c 2009-02-15 02:53:18 UTC (rev 3949) @@ -42,7 +42,7 @@ #define ADT7475_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address, val) -unsigned long uma_memory_start, uma_memory_size; +uint64_t uma_memory_base, uma_memory_size; /******************************************************** * pistachio uses a BCM5787 as on-board NIC. @@ -307,14 +307,14 @@ break; } - uma_memory_start = msr.lo - uma_memory_size; /* TOP_MEM1 */ - printk_info("%s: uma size 0x%08x, memory start 0x%08x\n", - __func__, uma_memory_size, uma_memory_start); + uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + printk_info("%s: uma size 0x%08lx, memory start 0x%08lx\n", + __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ #else uma_memory_size = 0x8000000; /* 128M recommended UMA */ - uma_memory_start = 0x38000000; /* 1GB system memory supposed */ + uma_memory_base = 0x38000000; /* 1GB system memory supposed */ #endif enable_onboard_nic(); @@ -328,10 +328,10 @@ * in some circumstances we want the memory mentioned as reserved. */ #if (CONFIG_GFXUMA == 1) - printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n", - uma_memory_start, uma_memory_size); + printk_info("uma_memory_base=0x%lx, uma_memory_size=0x%lx \n", + uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, - uma_memory_start, uma_memory_size); + uma_memory_base, uma_memory_size); #endif } Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c 2009-02-14 16:23:16 UTC (rev 3948) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c 2009-02-15 02:53:18 UTC (rev 3949) @@ -307,10 +307,10 @@ */ void rs690_set_tom(device_t nb_dev) { - extern unsigned long uma_memory_start; + extern uint64_t uma_memory_base; /* set TOM */ - pci_write_config32(nb_dev, 0x90, uma_memory_start); - nbmc_write_index(nb_dev, 0x1e, uma_memory_start); + pci_write_config32(nb_dev, 0x90, uma_memory_base); + nbmc_write_index(nb_dev, 0x1e, uma_memory_base); }

1 0

r3948 build service
by coreboot information 14 Feb '09

14 Feb '09

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ruik" checked in revision 3948 to the coreboot source repository and caused the following changes: Change Log: Change Log: Bellongs to r3947 Following patch adds dynamically generated P-States infrastructure as well as M2V-MX SE as example how to do that. It is based on AMD code and mine code for ACPI generation. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of amd:dbm690t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3948&device=dbm690t&vendor… Compilation of amd:pistachio is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3948&device=pistachio&vend… Compilation of amd:serengeti_cheetah has been fixed Compilation of arima:hdama has been fixed Compilation of asus:a8n_e has been fixed Compilation of asus:a8v-e_se has been fixed Compilation of asus:m2v-mx_se has been fixed Compilation of broadcom:blast has been fixed Compilation of gigabyte:ga_2761gxdk has been fixed Compilation of gigabyte:m57sli has been fixed Compilation of ibm:e325 has been fixed Compilation of ibm:e326 has been fixed Compilation of iwill:dk8_htx has been fixed Compilation of iwill:dk8s2 has been fixed Compilation of iwill:dk8x has been fixed Compilation of msi:ms7135 has been fixed Compilation of msi:ms7260 has been fixed Compilation of msi:ms9185 has been fixed Compilation of msi:ms9282 has been fixed Compilation of newisys:khepri has been fixed Compilation of nvidia:l1_2pvv has been fixed Compilation of sunw:ultra40 has been fixed Compilation of supermicro:h8dmr has been fixed Compilation of tyan:s2850 has been fixed Compilation of tyan:s2875 has been fixed Compilation of tyan:s2880 has been fixed Compilation of tyan:s2881 has been fixed Compilation of tyan:s2882 has been fixed Compilation of tyan:s2885 has been fixed Compilation of tyan:s2891 has been fixed Compilation of tyan:s2892 has been fixed Compilation of tyan:s2895 has been fixed Compilation of tyan:s2912 has been fixed Compilation of tyan:s4880 has been fixed Compilation of tyan:s4882 has been fixed If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3947 build service
by coreboot information 14 Feb '09

14 Feb '09

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ruik" checked in revision 3947 to the coreboot source repository and caused the following changes: Change Log: Bellongs to r3946 Following patch adds dynamically generated P-States infrastructure as well as M2V-MX SE as example how to do that. It is based on AMD code and mine code for ACPI generation. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of amd:dbm690t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=dbm690t&vendor… Compilation of amd:pistachio is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=pistachio&vend… Compilation of amd:serengeti_cheetah is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=serengeti_chee… Compilation of arima:hdama is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=hdama&vendor=a… Compilation of asus:a8n_e is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=a8n_e&vendor=a… Compilation of asus:a8v-e_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=a8v-e_se&vendo… Compilation of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=m2v-mx_se&vend… Compilation of broadcom:blast is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=blast&vendor=b… Compilation of gigabyte:ga_2761gxdk is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=ga_2761gxdk&ve… Compilation of gigabyte:m57sli is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=m57sli&vendor=… Compilation of ibm:e325 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=e325&vendor=ibm Compilation of ibm:e326 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=e326&vendor=ibm Compilation of iwill:dk8_htx is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=dk8_htx&vendor… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=dk8s2&vendor=i… Compilation of iwill:dk8x is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=dk8x&vendor=iw… Compilation of msi:ms7135 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=ms7135&vendor=… Compilation of msi:ms7260 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=ms7260&vendor=… Compilation of msi:ms9185 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=ms9185&vendor=… Compilation of msi:ms9282 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=ms9282&vendor=… Compilation of newisys:khepri is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=khepri&vendor=… Compilation of nvidia:l1_2pvv is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=l1_2pvv&vendor… Compilation of sunw:ultra40 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=ultra40&vendor… Compilation of supermicro:h8dmr is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=h8dmr&vendor=s… Compilation of tyan:s2850 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=s2850&vendor=t… Compilation of tyan:s2875 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=s2875&vendor=t… Compilation of tyan:s2880 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=s2880&vendor=t… Compilation of tyan:s2881 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=s2881&vendor=t… Compilation of tyan:s2882 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=s2882&vendor=t… Compilation of tyan:s2885 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=s2885&vendor=t… Compilation of tyan:s2891 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=s2891&vendor=t… Compilation of tyan:s2892 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=s2892&vendor=t… Compilation of tyan:s2895 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=s2895&vendor=t… Compilation of tyan:s2912 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=s2912&vendor=t… Compilation of tyan:s4880 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=s4880&vendor=t… Compilation of tyan:s4882 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3947&device=s4882&vendor=t… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3948 - trunk/coreboot-v2/src/include/cpu/amd
by svn＠coreboot.org 14 Feb '09

14 Feb '09

Author: ruik Date: 2009-02-14 17:23:16 +0100 (Sat, 14 Feb 2009) New Revision: 3948 Added: trunk/coreboot-v2/src/include/cpu/amd/model_fxx_powernow.h Log: Change Log: Bellongs to r3947 Following patch adds dynamically generated P-States infrastructure as well as M2V-MX SE as example how to do that. It is based on AMD code and mine code for ACPI generation. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> Added: trunk/coreboot-v2/src/include/cpu/amd/model_fxx_powernow.h =================================================================== --- trunk/coreboot-v2/src/include/cpu/amd/model_fxx_powernow.h (rev 0) +++ trunk/coreboot-v2/src/include/cpu/amd/model_fxx_powernow.h 2009-02-14 16:23:16 UTC (rev 3948) @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef MODEL_FXX_POWERNOW_H +#define MODEL_FXX_POWERNOW_H + +int amd_model_fxx_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP); + +#endif

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coreboot February 2009