coreboot October 2009

coreboot@coreboot.org

63 participants
534 discussions

Re: [coreboot] [PATCH] consolidate K8M890 VGA code
by r.marek＠assembler.cz 29 Oct '09

29 Oct '09

> Do you really want to get rid of dynamically being able to set the FB size? Well as we agreed? on IRC, I would like to have Kconfig settable default and the CMOS option as the most preferred state. Second reason is because as you pointed out the CMOS option does not work for M2V SE. Reason was that I never understood how it is supposed to be done. Third is I like to have a settable default in Kconfig. > Don't you think that this is a feature that regular users of probably > the only fully implemented coreboot motherboards might actually want > to touch? Please don't take it as offense. I like the CMOS options but other stuff must be fixed here to make CMOS usable for M2V-MX. > Why is no time being spent on removing the other options that > actually harm booting this device? Why does this feel like more > pointless pedanticity? It sounds you are really pissed off - please try no to look like exploded supernova ;) I completely agree with you that CMOS is right way. But it never worked here, so I changed it back - it was not evil intention and I would love to see the solution I written above. To have a Kconfig settable default and CMOS option which will be used if CMOS is valid. I think the code I wrote can be used for the CMOS option too, just simple change is needed. Rudolf ---------------------------------------------------------------- This message was sent using IMP, the Internet Messaging Program.

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[PATCH] Add prototypes for wrapped libgcc calls
by Myles Watson 29 Oct '09

29 Oct '09

Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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[v2] r4888 - trunk/coreboot-v2/src/lib
by svn＠coreboot.org 29 Oct '09

29 Oct '09

Author: myles Date: 2009-10-29 17:49:50 +0100 (Thu, 29 Oct 2009) New Revision: 4888 Modified: trunk/coreboot-v2/src/lib/gcc.c Log: Add prototypes to silence these warnings. src/lib/gcc.c:30: warning: no previous prototype for '__wrap___divdi3' The prototypes were not added to lib.h because the functions should never be called directly. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/lib/gcc.c =================================================================== --- trunk/coreboot-v2/src/lib/gcc.c 2009-10-28 19:56:34 UTC (rev 4887) +++ trunk/coreboot-v2/src/lib/gcc.c 2009-10-29 16:49:50 UTC (rev 4888) @@ -22,9 +22,9 @@ * compiler call specifies. Therefore we need a wrapper around those * functions. See gcc bug PR41055 for more information. */ - #define WRAP_LIBGCC_CALL(type, name) \ type __real_##name(type a, type b) __attribute__((regparm(0))); \ + type __wrap_##name(type a, type b); \ type __wrap_##name(type a, type b) { return __real_##name(a, b); } WRAP_LIBGCC_CALL(long long, __divdi3)

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FW: Intel GS45 / ICH9M chipset support?
by Ken.Fuchs＠bench.com 29 Oct '09

29 Oct '09

Ken.Fuchs wrote: > Anyone working on Intel GS45 / ICH9M chipset support? > > http://www.intel.com/design/chipsets/embedded/GS45/index.htm > > http://ark.intel.com/ProductCollection.aspx?codeName=26757&code=ICH9 Well, no one responded, so it seems no one is porting coreboot to this embedded chipset. Is anyone interested in coreboot support for this embedded platform (Core 2 Duo / Intel GS45 / ICH9M chipset)? Thanks, Ken Fuchs

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SerialICE - Qemu based x86 firmware debugger
by Stefan Reinauer 29 Oct '09

29 Oct '09

Dear x86 hardware and low-level software developers and enthusiasts! coresystems GmbH is glad to release a new version of our "Integrated Circuit Emulator over Serial", short SerialICE. Short description: SerialICE (http://www.serialice.com) is a BIOS/Firmware debugging tool. It allows you to run and observe BIOS images (such as coreboot®: http://www.coreboot.org/) written for real hardware in Qemu (http://www.qemu.org) for debugging purposes. Thanks to Qemu's compelling feature set, it's also possible to debug this BIOS code with GNU GDB. SerialICE consists of three parts: - a serial console "rom shell" compiled with romcc, with minimal footprint. - a patch to Qemu 0.11.0, which adds a new "SerialICE" machine. - a LUA script that contains filters, loggers and other SerialICE specific configuration and adaption SerialICE can be downloaded from http://www.serialice.com/. With "qemu -m serialice -serialice /dev/ttyS0 -L path-to-your-bios.bin-dir -hda /dev/zero" you can run an arbitrary BIOS binary written for your target hardware in Qemu, thus logging all IO and memory accesses. Those operations will additionally be transmitted to the target system's shell and are executed there, while their results are submitted back to Qemu. Operations sent to the target: - memory reads/writes (some of them) - IO reads/writes - MSR reads/writes - CPUID calls (the bios code path might rely on this) Note: The code is still quite experimental and only supports a few number of mainboard out of the box, but it was already useful in some debugging scenarios we had and was able to reveil information that would normally only be available with a hardware debugger of the price of a new car. Don't expect SerialICE to completely replace a ICE/JTAG/ITP device, but it might just work for your case, as it did for us. The ROM code needs minimal board/chipset specific setup in order to establish serial communication with Qemu. See mainboard/* for a few examples. This release contains setup code for 7 mainboards. Also, some hardware accesses have to be caught in the LUA code (scripts/serialice.lua) in order to prevent the system from locking up (ie. when the BIOS is disabling the serial console). Among the new features: - Completely scriptable filtering and logging with LUA and bitlib. - Kconfig/Kbuild support (make menuconfig) - New mainboards supported: Intel D945GCLF, ASUS M2V-MX SE, MSI MS6178, Thomson IP1000, Dell PowerEdge s1850, RCA RM4100 - Patch against latest Qemu version 0.11.0. - Support for compiling with XMMSTACK and ROMCC. - Many bugs fixed: serial communication, data corruption by signed/unsigned casts, ... Known issues: - microcode updates from within emulated ROM code will fail. - some rarely used calls of cpuid and rdmsr/wrmsr might not give the correct information Special thanks go to Daniel Liu, Rudolf Marek, Ron Minnich, Joe Smith, Uwe Hermann and Mark Marshall for their bug fixes and contributions to this release. See http://www.serialice.com/ for more information. Comments and patches are of course very welcome! Best regards, Stefan Reinauer -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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Re: [coreboot] [v2] r4886 - in trunk/coreboot-v2/util: . amdtools amdtools/example_input
by Carl-Daniel Hailfinger 29 Oct '09

29 Oct '09

Hi Ward, was it intentional that you placed these tools below coreboot-v2/ in the tree? On 28.10.2009 20:41, svn(a)coreboot.org wrote: > Author: ward > New Revision: 4886 > > Added: > trunk/coreboot-v2/util/amdtools/ > Log: > > Add an initial version of some tools to compare (extended) K8 memory settings. > Regards, Carl-Daniel -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

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LPC/FWH/Parallel buses on Intel ICH, VIA VT82*
by Carl-Daniel Hailfinger 28 Oct '09

28 Oct '09

Hi, I'm trying to get an overview about which flash buses are supported on which chipsets. SPI support is pretty clear for all chipsets. For ICH I don't know if they ever supported LPC flash, and when Parallel support stopped and FWH support started (and if there was any overlap). For VIA VT82*, I heard that FWH flash was never supported, but I'm not sure when Parallel support stopped and LPC support started (and if there was any overlap). Any insights appreciated. Regards, Carl-Daniel -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

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[PATCH] consolidate K8M890 VGA code
by Rudolf Marek 28 Oct '09

28 Oct '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello all, Following patch changes the K8M890 VGA handling. It reverts the framebuffer size to option based (similar what Uwe did) and also it uses GFXUMA to handle the high_tables_start offset from memory top. It adds HAVE_MOTHERBOARD_RESOURCES to kconfig because we do have the resources ;) Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkrooN8ACgkQ3J9wPJqZRNUGeACeM7QCbwiHj6QpTDaCojxC8NjK Qy0AnAl61XJfK/UB1NQOd4gB5HYJ8pJV =f8uT -----END PGP SIGNATURE-----

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build service results for r4887
by coreboot information 28 Oct '09

28 Oct '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4887 to the coreboot repository. This caused the following changes: Change Log: Comment out option ROM line in Config-abuild.lb to fix build. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of intel:d945gclf has been fixed If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r4886
by coreboot information 28 Oct '09

28 Oct '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "ward" checked in revision 4886 to the coreboot repository. This caused the following changes: Change Log: Add an initial version of some tools to compare (extended) K8 memory settings. This generates (dirty) html with interpreted differences between PCI dumps, based on the K8 socket F bkdg. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Stepan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of intel:d945gclf is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4886&device=d945gclf&vendo… If something broke during this checkin please be a pain in ward's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot October 2009