Author: rminnich
Date: 2008-08-05 04:48:54 +0200 (Tue, 05 Aug 2008)
New Revision: 722
Modified:
coreboot-v3/arch/x86/amd/k8/stage1.c
coreboot-v3/arch/x86/resourcemap.c
coreboot-v3/include/arch/x86/amd/k8/k8.h
coreboot-v3/include/arch/x86/amd/k8/raminit.h
coreboot-v3/include/arch/x86/cpu.h
coreboot-v3/mainboard/gigabyte/Kconfig
coreboot-v3/northbridge/amd/k8/raminit.c
coreboot-v3/southbridge/nvidia/mcp55/stage1.c
Log:
State of the tree for K8
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
Acked-by: Peter Stuge <peter(a)stuge.se>
Modified: coreboot-v3/arch/x86/amd/k8/stage1.c
===================================================================
--- coreboot-v3/arch/x86/amd/k8/stage1.c 2008-08-05 01:24:38 UTC (rev 721)
+++ coreboot-v3/arch/x86/amd/k8/stage1.c 2008-08-05 02:48:54 UTC (rev 722)
@@ -23,6 +23,7 @@
#include <console.h>
#include <msr.h>
#include <macros.h>
+#include <cpu.h>
#include <amd/k8/k8.h>
/**
Modified: coreboot-v3/arch/x86/resourcemap.c
===================================================================
--- coreboot-v3/arch/x86/resourcemap.c 2008-08-05 01:24:38 UTC (rev 721)
+++ coreboot-v3/arch/x86/resourcemap.c 2008-08-05 02:48:54 UTC (rev 722)
@@ -29,10 +29,8 @@
*
* @param rm The resource map
* @param max The map size
- * @param offset_dev pci device offset. This can be useful on e.g. k8
- * we have a number of similar devices which need the same setups
- * we can use one map for more than one device. NOTE:
- * offset_dev IS NOT ASSUMED TO BE OFFSET BY FN (i.e. it is not << 3)
+ * @param offset_bdf pci device offset. Note this is a u32 in
+ * busdevfn format. See PCI_BDF macro if you are not sure what that is.
* @param offset_pciio added to the OR value for setting up PCI IO
* @param offset_io offset from the io base in the resource map
*/
@@ -40,11 +38,11 @@
/* NOTE: By doing the config write in this manner we guarantee that this
* will work in stage1 or stage2.
*/
-#define pci_config_read32(bus, dev, where) pci_cf8_conf1.read32(NULL, r->pcm.bus, dev, where)
-#define pci_config_write32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, r->pcm.bus, dev, where, what)
+#define pci_read_config32(bus, dev, where) pci_cf8_conf1.read32(NULL, r->pcm.bus, dev, where)
+#define pci_write_config32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, r->pcm.bus, dev, where, what)
void setup_resource_map_x_offset(const rmap *rm, u32 max,
- u32 offset_dev, u32 offset_pciio,
+ u32 offset_bdf, u32 offset_pciio,
u32 offset_io)
{
u32 i;
@@ -53,26 +51,30 @@
for(i = 0; i < max; i++, rm++) {
switch (rm->type){
- case PCIRM:
+ case TPCIRM:
{
u32 dev;
unsigned where;
unsigned long reg;
- printk(BIOS_DEBUG, "(%x,%x+%x,%x,%x) & %08x | %08x+%08x\n", rm->pcm.bus,rm->pcm.dev+offset_dev,
- rm->pcm.fn,rm->pcm.reg,
+ u8 offset_devfn = offset_bdf;
+#warning make sure offset_bus is right for extended PCI addressing
+ u32 offset_bus = offset_bdf >> 8;
+ printk(BIOS_DEBUG, "(%x+%x,%x+%x,%x+%x,%x) & %08x | %08x+%08x\n", rm->pcm.bus,
+ offset_bus, rm->pcm.dev+offset_devfn>>3,
+ rm->pcm.fn, offset_devfn&3, rm->pcm.reg,
rm->pcm.and,rm->pcm.or, offset_pciio);
dev = rm->pcm.dev;
- dev += offset_dev;
- where = rm->pcm.reg;
+ where = rm->pcm.reg;
dev <<= 3;
dev |= rm->pcm.fn;
- reg = pci_config_read32(rm->pcm.bus, dev, where);
+ dev += offset_devfn;
+ reg = pci_read_config32(rm->pcm.bus + offset_bus, dev, where);
reg &= rm->pcm.and;
reg |= rm->pcm.or + offset_pciio;
- pci_config_write32(rm->pcm.bus, dev, where, reg);
+ pci_write_config32(rm->pcm.bus, dev, where, reg);
}
break;
- case IO8:
+ case TIO8:
{
u32 where;
u8 reg;
@@ -84,7 +86,7 @@
outb(reg, where);
}
break;
- case IO32:
+ case TIO32:
{
u32 where;
u32 reg;
Modified: coreboot-v3/include/arch/x86/amd/k8/k8.h
===================================================================
--- coreboot-v3/include/arch/x86/amd/k8/k8.h 2008-08-05 01:24:38 UTC (rev 721)
+++ coreboot-v3/include/arch/x86/amd/k8/k8.h 2008-08-05 02:48:54 UTC (rev 722)
@@ -17,6 +17,12 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+
+/* Until we resolve a better way to do this, work around it with a value "too large to fail" */
+#warning clean up setting of DIMM_SOCKETS and NODE_NUMS
+#define DIMM_SOCKETS 4
+#define NODE_NUMS 16
+
#define ROM_CODE_SEG 0x08
#define ROM_DATA_SEG 0x10
@@ -347,6 +353,7 @@
struct dimm_size {
u8 per_rank; // it is rows + col + bank_lines + data lines */
+ u8 side1, side2;
u8 rows;
u8 col;
u8 bank; //1, 2, 3 mean 2, 4, 8
@@ -370,11 +377,18 @@
u8 rsv[3];
} __attribute__((packed));
+struct mem_controller {
+ unsigned node_id;
+ u32 f0, f1, f2, f3;
+ u32 channel0[DIMM_SOCKETS];
+ u32 channel1[DIMM_SOCKETS];
+};
+
struct link_pair_st {
- struct device * udev;
+ u32 udev;
u32 upos;
u32 uoffs;
- struct device * dev;
+ u32 dev;
u32 pos;
u32 offs;
Modified: coreboot-v3/include/arch/x86/amd/k8/raminit.h
===================================================================
--- coreboot-v3/include/arch/x86/amd/k8/raminit.h 2008-08-05 01:24:38 UTC (rev 721)
+++ coreboot-v3/include/arch/x86/amd/k8/raminit.h 2008-08-05 02:48:54 UTC (rev 722)
@@ -8,7 +8,7 @@
#define DIMM_SOCKETS 4
struct mem_controller {
unsigned node_id;
- struct device *f0, *f1, *f2, *f3;
+ u32 f0, f1, f2, f3;
u16 channel0[DIMM_SOCKETS];
u16 channel1[DIMM_SOCKETS];
};
Modified: coreboot-v3/include/arch/x86/cpu.h
===================================================================
--- coreboot-v3/include/arch/x86/cpu.h 2008-08-05 01:24:38 UTC (rev 721)
+++ coreboot-v3/include/arch/x86/cpu.h 2008-08-05 02:48:54 UTC (rev 722)
@@ -211,9 +211,9 @@
* there are tables that are combinations of all three (or the code supports it anyway)
*/
/* types of resource maps */
-#define PCIRM 'p'
-#define IO8 '8'
-#define IO32 'I'
+#define TPCIRM 'p'
+#define TIO8 '8'
+#define TIO32 'I'
/* pci config map */
struct pcm {
@@ -234,9 +234,9 @@
/* convenience initializer */
-#define PCM(abus,adev,afn,areg,aand,aor) {.type = PCIRM, {.pcm ={.bus=abus,.dev=adev,.fn=afn,.reg=areg,.and=aand,.or=aor}}}
-#define EIO8(aport, aand, aor) {.type=IO8, {.io8 = {.port = aport, .and = aand, .or = aor}}}
-#define EIO32(aport, aand, aaor) {.type = IO32, {.io32 = {.port = aport, .and = aand, .or = aor}}}
+#define PCM(abus,adev,afn,areg,aand,aor) {.type = TPCIRM, {.pcm ={.bus=abus,.dev=adev,.fn=afn,.reg=areg,.and=aand,.or=aor}}}
+#define IO8(aport, aand, aor) {.type=TIO8, {.io8 = {.port = aport, .and = aand, .or = aor}}}
+#define IO32(aport, aand, aor) {.type = TIO32, {.io32 = {.port = aport, .and = aand, .or = aor}}}
struct rmap {
int type;
union {
Modified: coreboot-v3/mainboard/gigabyte/Kconfig
===================================================================
--- coreboot-v3/mainboard/gigabyte/Kconfig 2008-08-05 01:24:38 UTC (rev 721)
+++ coreboot-v3/mainboard/gigabyte/Kconfig 2008-08-05 02:48:54 UTC (rev 722)
@@ -29,7 +29,7 @@
select OPTION_TABLE
select CPU_AMD_K8
select NORTHBRIDGE_AMD_K8
-# select SOUTHBRIDGE_NVIDIA_MCP55
+ select SOUTHBRIDGE_NVIDIA_MCP55
select SUPERIO_ITE_IT8716F
help
Gigabyte M57SLI
Modified: coreboot-v3/northbridge/amd/k8/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-05 01:24:38 UTC (rev 721)
+++ coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-05 02:48:54 UTC (rev 722)
@@ -36,7 +36,6 @@
#include <spd.h>
#include <cpu.h>
#include <msr.h>
-#include <amd/k8/raminit.h>
#include <amd/k8/k8.h>
#include <amd/k8/sysconf.h>
#include <device/pci.h>
@@ -56,13 +55,13 @@
extern const struct pci_bus_operations pci_cf8_conf1;
static void hard_reset(void);
-#define pci_config_read32(bus, dev, where) pci_cf8_conf1.read32(NULL, bus, dev, where)
-#define pci_config_write32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, bus, dev, where, what)
+#define pci_read_config32(bus, dev, where) pci_cf8_conf1.read32(NULL, bus, dev, where)
+#define pci_write_config32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, bus, dev, where, what)
static int controller_present(const struct mem_controller *ctrl)
{
- return pci_config_read32(0, ctrl->f0, 0) == 0x11001022;
+ return pci_read_config32(0, ctrl->f0, 0) == 0x11001022;
}
static void sdram_set_registers(const struct mem_controller *ctrl)
@@ -551,8 +550,8 @@
static void hw_enable_ecc(const struct mem_controller *ctrl)
{
u32 dcl, nbcap, opt = 1;
- nbcap = pci_config_read32(0, ctrl->f3, NORTHBRIDGE_CAP);
- dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
+ nbcap = pci_read_config32(0, ctrl->f3, NORTHBRIDGE_CAP);
+ dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
dcl &= ~DCL_DimmEccEn;
if (nbcap & NBCAP_ECC) {
dcl |= DCL_DimmEccEn;
@@ -560,14 +559,14 @@
if (get_option(&opt, "ECC_memory") || opt) {
dcl &= ~DCL_DimmEccEn;
}
- pci_config_write32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
+ pci_write_config32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
}
static int is_dual_channel(const struct mem_controller *ctrl)
{
u32 dcl;
- dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
+ dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
return dcl & DCL_128BitEn;
}
@@ -579,7 +578,7 @@
*/
#warning "FIXME: Implement a better test for Opterons"
u32 nbcap;
- nbcap = pci_config_read32(0, ctrl->f3, NORTHBRIDGE_CAP);
+ nbcap = pci_read_config32(0, ctrl->f3, NORTHBRIDGE_CAP);
return !!(nbcap & NBCAP_128Bit);
}
@@ -590,7 +589,7 @@
* This function must be called after spd_handle_unbuffered_dimms.
*/
u32 dcl;
- dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
+ dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
return !(dcl & DCL_UnBufDimm);
}
@@ -722,25 +721,25 @@
base1 &= ~0x001ffffe;
/* Set the appropriate DIMM base address register */
- pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
- pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
+ pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
+ pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
#if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) {
- pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
- pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
+ pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
+ pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
}
#endif
/* Enable the memory clocks for this DIMM */
if (base0) {
- dch = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_HIGH);
+ dch = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_HIGH);
dch |= DCH_MEMCLK_EN0 << index;
#if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) {
dch |= DCH_MEMCLK_EN0 << (index + 2);
}
#endif
- pci_config_write32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
+ pci_write_config32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
}
}
@@ -756,7 +755,7 @@
u32 map;
u32 dch;
- map = pci_config_read32(0, ctrl->f2, DRAM_BANK_ADDR_MAP);
+ map = pci_read_config32(0, ctrl->f2, DRAM_BANK_ADDR_MAP);
map &= ~(0xf << (index * 4));
#if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) {
@@ -785,7 +784,7 @@
}
}
- pci_config_write32(0, ctrl->f2, DRAM_BANK_ADDR_MAP, map);
+ pci_write_config32(0, ctrl->f2, DRAM_BANK_ADDR_MAP, map);
}
@@ -832,8 +831,8 @@
limit_reg = 0x44 + index;
base_reg = 0x40 + index;
for(device = PCI_BDF(0, 0x18, 1); device <= PCI_BDF(0, 0x1f, 1); device += PCI_BDF(0, 1, 0)) {
- pci_config_write32(0, device, limit_reg, limit);
- pci_config_write32(0, device, base_reg, base);
+ pci_write_config32(0, device, limit_reg, limit);
+ pci_write_config32(0, device, base_reg, base);
}
}
@@ -918,7 +917,7 @@
unsigned cs_mode;
u32 value;
- value = pci_config_read32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
+ value = pci_read_config32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
/* Is it enabled? */
if (!(value & 1)) {
@@ -934,7 +933,7 @@
return 0;
}
- value = pci_config_read32(0, ctrl->f2, DRAM_BANK_ADDR_MAP);
+ value = pci_read_config32(0, ctrl->f2, DRAM_BANK_ADDR_MAP);
cs_mode =( value >> ((index>>1)*4)) & 0xf;
if(cs_mode == 0 ) continue;
if(common_cs_mode == 0) {
@@ -987,13 +986,13 @@
for(index = 0; index < 8; index++) {
u32 value;
- value = pci_config_read32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
+ value = pci_read_config32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
/* Is it enabled? */
if (!(value & 1)) {
continue;
}
- pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
- pci_config_write32(0, ctrl->f2, DRAM_CSMASK + (index << 2), csmask);
+ pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
+ pci_write_config32(0, ctrl->f2, DRAM_CSMASK + (index << 2), csmask);
csbase += csbase_inc;
}
@@ -1018,7 +1017,7 @@
candidate = 0;
for(index = 0; index < 8; index++) {
u32 value;
- value = pci_config_read32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
+ value = pci_read_config32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
/* Is it enabled? */
if (!(value & 1)) {
@@ -1060,9 +1059,9 @@
csmask |= 0xfe00; /* For now don't optimize */
/* Write the new base register */
- pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (candidate << 2), csbase);
+ pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (candidate << 2), csbase);
/* Write the new mask register */
- pci_config_write32(0, ctrl->f2, DRAM_CSMASK + (candidate << 2), csmask);
+ pci_write_config32(0, ctrl->f2, DRAM_CSMASK + (candidate << 2), csmask);
}
/* Return the memory size in K */
@@ -1079,10 +1078,10 @@
u32 limit, base;
unsigned index;
index = node_id << 3;
- base = pci_config_read32(0, ctrl->f1, 0x40 + index);
+ base = pci_read_config32(0, ctrl->f1, 0x40 + index);
/* Only look at the limit if the base is enabled */
if ((base & 3) == 3) {
- limit = pci_config_read32(0, ctrl->f1, 0x44 + index);
+ limit = pci_read_config32(0, ctrl->f1, 0x44 + index);
end_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
}
}
@@ -1113,8 +1112,8 @@
static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask)
{
printk(BIOS_DEBUG, "disabling dimm 0x%x\n", index);
- pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
- pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
+ pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
+ pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
dimm_mask &= ~(1 << index);
return dimm_mask;
}
@@ -1150,7 +1149,7 @@
die("Mixed buffered and registered dimms not supported");
}
- dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
+ dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
dcl &= ~DCL_UnBufDimm;
if (unbuffered) {
if ((has_dualch) && (!is_cpu_pre_d0())) {
@@ -1166,7 +1165,7 @@
dcl |= DCL_UnBufDimm;
}
}
- pci_config_write32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
+ pci_write_config32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
if (is_registered(ctrl)) {
printk(BIOS_DEBUG, "Registered\n");
} else {
@@ -1234,7 +1233,7 @@
goto single_channel;
}
/* If the cpu is not capable of doing dual channels don't do dual channels */
- nbcap = pci_config_read32(0, ctrl->f3, NORTHBRIDGE_CAP);
+ nbcap = pci_read_config32(0, ctrl->f3, NORTHBRIDGE_CAP);
if (!(nbcap & NBCAP_128Bit)) {
goto single_channel;
}
@@ -1266,10 +1265,10 @@
}
printk(BIOS_SPEW, "Enabling dual channel memory\n");
u32 dcl;
- dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
+ dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
dcl &= ~DCL_32ByteEn;
dcl |= DCL_128BitEn;
- pci_config_write32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
+ pci_write_config32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
return dimm_mask;
single_channel:
dimm_mask &= ~((1 << (DIMM_SOCKETS *2)) - (1 << DIMM_SOCKETS));
@@ -1390,7 +1389,7 @@
[NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */
};
- value = pci_config_read32(0, ctrl->f3, NORTHBRIDGE_CAP);
+ value = pci_read_config32(0, ctrl->f3, NORTHBRIDGE_CAP);
min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
@@ -1541,7 +1540,7 @@
result.param = get_mem_param(min_cycle_time);
/* Update DRAM Config High with our selected memory speed */
- value = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_HIGH);
+ value = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_HIGH);
value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT);
#if 0
/* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed
@@ -1555,14 +1554,14 @@
#endif
value |= result.param->dch_memclk;
- pci_config_write32(0, ctrl->f2, DRAM_CONFIG_HIGH, value);
+ pci_write_config32(0, ctrl->f2, DRAM_CONFIG_HIGH, value);
static const unsigned latencies[] = { DTL_CL_2, DTL_CL_2_5, DTL_CL_3 };
/* Update DRAM Timing Low with our selected cas latency */
- value = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+ value = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
value |= latencies[min_latency - 2] << DTL_TCL_SHIFT;
- pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, value);
+ pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, value);
result.dimm_mask = dimm_mask;
return result;
@@ -1591,14 +1590,14 @@
return 0;
}
- dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+ dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE;
if (old_clocks > clocks) {
clocks = old_clocks;
}
dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT);
dtl |= ((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT);
- pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
+ pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
return 1;
}
@@ -1619,14 +1618,14 @@
if (clocks > DTL_TRFC_MAX) {
return 0;
}
- dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+ dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
old_clocks = ((dtl >> DTL_TRFC_SHIFT) & DTL_TRFC_MASK) + DTL_TRFC_BASE;
if (old_clocks > clocks) {
clocks = old_clocks;
}
dtl &= ~(DTL_TRFC_MASK << DTL_TRFC_SHIFT);
dtl |= ((clocks - DTL_TRFC_BASE) << DTL_TRFC_SHIFT);
- pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
+ pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
return 1;
}
@@ -1645,14 +1644,14 @@
if (clocks > DTL_TRCD_MAX) {
return 0;
}
- dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+ dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
old_clocks = ((dtl >> DTL_TRCD_SHIFT) & DTL_TRCD_MASK) + DTL_TRCD_BASE;
if (old_clocks > clocks) {
clocks = old_clocks;
}
dtl &= ~(DTL_TRCD_MASK << DTL_TRCD_SHIFT);
dtl |= ((clocks - DTL_TRCD_BASE) << DTL_TRCD_SHIFT);
- pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
+ pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
return 1;
}
@@ -1670,14 +1669,14 @@
if (clocks > DTL_TRRD_MAX) {
return 0;
}
- dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+ dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
old_clocks = ((dtl >> DTL_TRRD_SHIFT) & DTL_TRRD_MASK) + DTL_TRRD_BASE;
if (old_clocks > clocks) {
clocks = old_clocks;
}
dtl &= ~(DTL_TRRD_MASK << DTL_TRRD_SHIFT);
dtl |= ((clocks - DTL_TRRD_BASE) << DTL_TRRD_SHIFT);
- pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
+ pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
return 1;
}
@@ -1695,14 +1694,14 @@
if (clocks > DTL_TRAS_MAX) {
return 0;
}
- dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+ dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
if (old_clocks > clocks) {
clocks = old_clocks;
}
dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
- pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
+ pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
return 1;
}
@@ -1720,34 +1719,34 @@
if (clocks > DTL_TRP_MAX) {
return 0;
}
- dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+ dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
old_clocks = ((dtl >> DTL_TRP_SHIFT) & DTL_TRP_MASK) + DTL_TRP_BASE;
if (old_clocks > clocks) {
clocks = old_clocks;
}
dtl &= ~(DTL_TRP_MASK << DTL_TRP_SHIFT);
dtl |= ((clocks - DTL_TRP_BASE) << DTL_TRP_SHIFT);
- pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
+ pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
return 1;
}
static void set_Twr(const struct mem_controller *ctrl, const struct mem_param *param)
{
u32 dtl;
- dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+ dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
dtl &= ~(DTL_TWR_MASK << DTL_TWR_SHIFT);
dtl |= (param->dtl_twr - DTL_TWR_BASE) << DTL_TWR_SHIFT;
- pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
+ pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
}
static void init_Tref(const struct mem_controller *ctrl, const struct mem_param *param)
{
u32 dth;
- dth = pci_config_read32(0, ctrl->f2, DRAM_TIMING_HIGH);
+ dth = pci_read_config32(0, ctrl->f2, DRAM_TIMING_HIGH);
dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
dth |= (param->dch_tref4k << DTH_TREF_SHIFT);
- pci_config_write32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
+ pci_write_config32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
}
static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i)
@@ -1764,7 +1763,7 @@
tref = param->dch_tref4k;
}
- dth = pci_config_read32(0, ctrl->f2, DRAM_TIMING_HIGH);
+ dth = pci_read_config32(0, ctrl->f2, DRAM_TIMING_HIGH);
old_tref = (dth >> DTH_TREF_SHIFT) & DTH_TREF_MASK;
if ((value == 12) && (old_tref == param->dch_tref4k)) {
tref = param->dch_tref4k;
@@ -1773,7 +1772,7 @@
}
dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
dth |= (tref << DTH_TREF_SHIFT);
- pci_config_write32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
+ pci_write_config32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
return 1;
}
@@ -1804,12 +1803,12 @@
dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2);
}
#endif
- dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
+ dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
dcl &= ~dimm;
if (value == 4) {
dcl |= dimm;
}
- pci_config_write32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
+ pci_write_config32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
return 1;
}
@@ -1822,9 +1821,9 @@
return -1;
}
if (value != 2) {
- dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
+ dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
dcl &= ~DCL_DimmEccEn;
- pci_config_write32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
+ pci_write_config32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
}
return 1;
}
@@ -1836,7 +1835,7 @@
dimms = 0;
for(index = 0; index < 8; index += 2) {
u32 csbase;
- csbase = pci_config_read32(0, ctrl->f2, (DRAM_CSBASE + (index << 2)));
+ csbase = pci_read_config32(0, ctrl->f2, (DRAM_CSBASE + (index << 2)));
if (csbase & 1) {
dimms += 1;
}
@@ -1848,10 +1847,10 @@
{
u32 dth;
- dth = pci_config_read32(0, ctrl->f2, DRAM_TIMING_HIGH);
+ dth = pci_read_config32(0, ctrl->f2, DRAM_TIMING_HIGH);
dth &= ~(DTH_TWTR_MASK << DTH_TWTR_SHIFT);
dth |= ((param->dtl_twtr - DTH_TWTR_BASE) << DTH_TWTR_SHIFT);
- pci_config_write32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
+ pci_write_config32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
}
static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *param)
@@ -1862,7 +1861,7 @@
int lat, mtype;
clocks = 0;
- dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+ dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
latency = (dtl >> DTL_TCL_SHIFT) & DTL_TCL_MASK;
if (is_opteron(ctrl)) {
@@ -1892,10 +1891,10 @@
die("Unknown Trwt\n");
}
- dth = pci_config_read32(0, ctrl->f2, DRAM_TIMING_HIGH);
+ dth = pci_read_config32(0, ctrl->f2, DRAM_TIMING_HIGH);
dth &= ~(DTH_TRWT_MASK << DTH_TRWT_SHIFT);
dth |= ((clocks - DTH_TRWT_BASE) << DTH_TRWT_SHIFT);
- pci_config_write32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
+ pci_write_config32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
return;
}
@@ -1909,10 +1908,10 @@
} else {
clocks = 1;
}
- dth = pci_config_read32(0, ctrl->f2, DRAM_TIMING_HIGH);
+ dth = pci_read_config32(0, ctrl->f2, DRAM_TIMING_HIGH);
dth &= ~(DTH_TWCL_MASK << DTH_TWCL_SHIFT);
dth |= ((clocks - DTH_TWCL_BASE) << DTH_TWCL_SHIFT);
- pci_config_write32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
+ pci_write_config32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
}
@@ -1943,7 +1942,7 @@
die("Unknown rdpreamble for this nr of slots");
}
- dch = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_HIGH);
+ dch = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_HIGH);
dch &= ~(DCH_RDPREAMBLE_MASK << DCH_RDPREAMBLE_SHIFT);
rdpreamble = param->rdpreamble[i];
@@ -1952,7 +1951,7 @@
}
dch |= (rdpreamble - DCH_RDPREAMBLE_BASE) << DCH_RDPREAMBLE_SHIFT;
- pci_config_write32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
+ pci_write_config32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
}
static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
@@ -1963,7 +1962,7 @@
dimms = count_dimms(ctrl);
- dch = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_HIGH);
+ dch = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_HIGH);
dch &= ~(DCH_ASYNC_LAT_MASK << DCH_ASYNC_LAT_SHIFT);
async_lat = 0;
if (is_registered(ctrl)) {
@@ -1990,18 +1989,18 @@
}
}
dch |= ((async_lat - DCH_ASYNC_LAT_BASE) << DCH_ASYNC_LAT_SHIFT);
- pci_config_write32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
+ pci_write_config32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
}
static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param)
{
u32 dch;
/* AMD says to Hardcode this */
- dch = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_HIGH);
+ dch = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_HIGH);
dch &= ~(DCH_IDLE_LIMIT_MASK << DCH_IDLE_LIMIT_SHIFT);
dch |= DCH_IDLE_LIMIT_16 << DCH_IDLE_LIMIT_SHIFT;
dch |= DCH_DYN_IDLE_CTR_EN;
- pci_config_write32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
+ pci_write_config32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
}
static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, long dimm_mask)
@@ -2107,22 +2106,22 @@
carry_over = (4*1024*1024) - hole_startk;
for(ii=controllers - 1;ii>i;ii--) {
- base = pci_config_read32(0, ctrl[0].f1, 0x40 + (ii << 3));
+ base = pci_read_config32(0, ctrl[0].f1, 0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
- limit = pci_config_read32(0, ctrl[0].f1, 0x44 + (ii << 3));
+ limit = pci_read_config32(0, ctrl[0].f1, 0x44 + (ii << 3));
for(j = 0; j < controllers; j++) {
- pci_config_write32(0, ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
- pci_config_write32(0, ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
+ pci_write_config32(0, ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
+ pci_write_config32(0, ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
}
}
- limit = pci_config_read32(0, ctrl[0].f1, 0x44 + (i << 3));
+ limit = pci_read_config32(0, ctrl[0].f1, 0x44 + (i << 3));
for(j = 0; j < controllers; j++) {
- pci_config_write32(0, ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
+ pci_write_config32(0, ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
}
dev = ctrl[i].f1;
- base = pci_config_read32(0, dev, 0x40 + (i << 3));
+ base = pci_read_config32(0, dev, 0x40 + (i << 3));
basek = (base & 0xffff0000) >> 2;
if(basek == hole_startk) {
//don't need set memhole here, because hole off set will be 0, overflow
@@ -2130,7 +2129,7 @@
base &= 0x0000ffff;
base |= (4*1024*1024)<<2;
for(j = 0; j < controllers; j++) {
- pci_config_write32(0, ctrl[j].f1, 0x40 + (i<<3), base);
+ pci_write_config32(0, ctrl[j].f1, 0x40 + (i<<3), base);
}
}
else {
@@ -2140,7 +2139,7 @@
(((basek + carry_over) >> 6) & 0x0000ff00) +
/* enable */
1;
- pci_config_write32(0, dev, 0xf0, hoist);
+ pci_write_config32(0, dev, 0xf0, hoist);
}
return carry_over;
@@ -2164,7 +2163,7 @@
for(i=0; i<controllers; i++) {
u32 base;
unsigned base_k;
- base = pci_config_read32(0, ctrl[0].f1, 0x40 + (i << 3));
+ base = pci_read_config32(0, ctrl[0].f1, 0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
@@ -2184,11 +2183,11 @@
for(i=0; i<controllers; i++) {
u32 base, limit;
unsigned base_k, limit_k;
- base = pci_config_read32(0, ctrl[0].f1, 0x40 + (i << 3));
+ base = pci_read_config32(0, ctrl[0].f1, 0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
- limit = pci_config_read32(0, ctrl[0].f1, 0x44 + (i << 3));
+ limit = pci_read_config32(0, ctrl[0].f1, 0x44 + (i << 3));
base_k = (base & 0xffff0000) >> 2;
limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
if ((base_k <= hole_startk) && (limit_k > hole_startk)) {
@@ -2219,17 +2218,17 @@
u32 dch;
if (!controller_present(ctrl + i))
continue;
- dch = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
+ dch = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
if (dch & (DCH_MEMCLK_EN0|DCH_MEMCLK_EN1|DCH_MEMCLK_EN2|DCH_MEMCLK_EN3)) {
dch |= DCH_MEMCLK_VALID;
- pci_config_write32(0, ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
+ pci_write_config32(0, ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
}
else {
/* Disable dram receivers */
u32 dcl;
- dcl = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
+ dcl = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
dcl |= DCL_DisInRcvrs;
- pci_config_write32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+ pci_write_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
}
}
@@ -2243,31 +2242,31 @@
if (!controller_present(ctrl + i))
continue;
/* Skip everything if I don't have any memory on this controller */
- dch = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
+ dch = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
if (!(dch & DCH_MEMCLK_VALID)) {
continue;
}
/* Toggle DisDqsHys to get it working */
- dcl = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
+ dcl = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
if (dcl & DCL_DimmEccEn) {
u32 mnc;
printk(BIOS_SPEW, "ECC enabled\n");
- mnc = pci_config_read32(0, ctrl[i].f3, MCA_NB_CONFIG);
+ mnc = pci_read_config32(0, ctrl[i].f3, MCA_NB_CONFIG);
mnc |= MNC_ECC_EN;
if (dcl & DCL_128BitEn) {
mnc |= MNC_CHIPKILL_EN;
}
- pci_config_write32(0, ctrl[i].f3, MCA_NB_CONFIG, mnc);
+ pci_write_config32(0, ctrl[i].f3, MCA_NB_CONFIG, mnc);
}
dcl |= DCL_DisDqsHys;
- pci_config_write32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+ pci_write_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
dcl &= ~DCL_DisDqsHys;
dcl &= ~DCL_DLL_Disable;
dcl &= ~DCL_D_DRV;
dcl &= ~DCL_QFC_EN;
dcl |= DCL_DramInit;
- pci_config_write32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+ pci_write_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
}
for(i = 0; i < controllers; i++) {
@@ -2275,7 +2274,7 @@
if (!controller_present(ctrl + i))
continue;
/* Skip everything if I don't have any memory on this controller */
- dch = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
+ dch = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
if (!(dch & DCH_MEMCLK_VALID)) {
continue;
}
@@ -2284,7 +2283,7 @@
int loops = 0;
do {
- dcl = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
+ dcl = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
loops += 1;
if ((loops & 1023) == 0) {
printk(BIOS_DEBUG, ".");
@@ -2298,9 +2297,9 @@
if (!is_cpu_pre_c0()) {
/* Wait until it is safe to touch memory */
dcl &= ~(DCL_MemClrStatus | DCL_DramEnable);
- pci_config_write32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+ pci_write_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
do {
- dcl = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
+ dcl = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
} while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) );
}
Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-08-05 01:24:38 UTC (rev 721)
+++ coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-08-05 02:48:54 UTC (rev 722)
@@ -23,10 +23,11 @@
#include <io.h>
#include <device/device.h>
#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
+#include <cpu.h>
#include <amd/k8/k8.h>
#include "mcp55.h"
+#define pci_read_config32(bus, dev, where) pci_cf8_conf1.read32(NULL, bus, dev, where)
+#define pci_write_config32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, bus, dev, where, what)
#warning fix disgusting define of MCP55_NUM it is mainboard dependent
#define MCP55_NUM 1
@@ -107,35 +108,33 @@
static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base)
{
-
- static const unsigned int ctrl_devport_conf[] = {
- PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
- PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
- PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE,
+ static const struct rmap ctrl_devport_conf[] = {
+ PCM(0, 1, 1, ANACTRL_REG_POS, ~0x0000ff00, ANACTRL_IO_BASE),
+ PCM(0, 1, 1, SYSCTRL_REG_POS, ~0x0000ff00, SYSCTRL_IO_BASE),
+ PCM(0, 1, 1, ACPICTRL_REG_POS, ~0x0000ff00, ACPICTRL_IO_BASE),
};
int j;
for(j = 0; j < mcp55_num; j++ ) {
- setup_resource_map_offset(ctrl_devport_conf,
+ setup_resource_map_x_offset(ctrl_devport_conf,
sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
- PCI_BDF(busn[j], devn[j], 0) , io_base[j]);
+ PCI_BDF(busn[j], devn[j], 0) , io_base[j], 0);
}
}
-
static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base)
{
- static const unsigned int ctrl_devport_conf_clear[] = {
- PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0,
- PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
- PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0,
+ static const struct rmap ctrl_devport_conf_clear[] = {
+ PCM(0, 1, 1, ANACTRL_REG_POS, ~0x0000ff00, 0),
+ PCM(0, 1, 1, SYSCTRL_REG_POS, ~0x0000ff00, 0),
+ PCM(0, 1, 1, ACPICTRL_REG_POS, ~0x0000ff00, 0),
};
int j;
for(j = 0; j < mcp55_num; j++ ) {
- setup_resource_map_offset(ctrl_devport_conf_clear,
+ setup_resource_map_x_offset(ctrl_devport_conf_clear,
sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
- PCI_BDF(busn[j], devn[j], 0) , io_base[j]);
+ PCI_BDF(busn[j], devn[j], 0) , io_base[j], 0);
}
@@ -155,13 +154,11 @@
u32 pll_ctrl;
u32 dword;
int i;
- //struct device dev;
- struct device *dev;
-#error dev is not set up
+ u32 dev;
// dev = PCI_BDF(busnx, devnx+1, 1);
- dword = pci_read_config32(dev, 0xe4);
+ dword = pci_read_config32(busnx, (devnx+1)<<3 | 1, 0xe4);
dword |= 0x3f0; // disable it at first
- pci_write_config32(dev, 0xe4, dword);
+ pci_write_config32(busnx, (devnx+1)<<3 | 1, 0xe4, dword);
for(i=0; i<3; i++) {
tgio_ctrl = inl(anactrl_io_base + 0xcc);
@@ -183,9 +180,9 @@
// wait 100us
delayx(1);
- dword = pci_read_config32(dev, 0xe4);
+ dword = pci_read_config32(busnx, (devnx+1)<<3 | 1, 0xe4);
dword &= ~(0x3f0); // enable
- pci_write_config32(dev, 0xe4, dword);
+ pci_write_config32(busnx, (devnx+1)<<3 | 1, 0xe4, dword);
// need to wait 100ms
delayx(1000);
@@ -194,102 +191,100 @@
static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x)
{
- static const unsigned int ctrl_conf_1[] = {
- RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000,
- RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000,
- RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200,
- RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xb4, 0xfffffffd, 0x0000002,
+ static const struct rmap ctrl_conf_1[] = {
+ IO32(ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000),
+ IO32(ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000),
+ IO32(ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200),
+ IO32(ACPICTRL_IO_BASE + 0xb4, 0xfffffffd, 0x0000002),
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc0f0f08f, 0x26020230,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x34, 0x00000000, 0x22222222,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, 0x7FFFFFFF, 0x00000000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x2C, 0x7FFFFFFF, 0x80000000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000200,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000400,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, 0xFFFF0FF5, 0x0000F000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, 0xFF00FF00, 0x00100010,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7C, 0xFF0FF0FF, 0x00500500,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0xFFFFFFE7, 0x00000000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFCFFFFF, 0x00300000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000,
+ IO32(ANACTRL_IO_BASE + 0x24, 0xc0f0f08f, 0x26020230),
+ IO32(ANACTRL_IO_BASE + 0x34, 0x00000000, 0x22222222),
+ IO32(ANACTRL_IO_BASE + 0x08, 0x7FFFFFFF, 0x00000000),
+ IO32(ANACTRL_IO_BASE + 0x2C, 0x7FFFFFFF, 0x80000000),
+ IO32(ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000000),
+ IO32(ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000),
+ IO32(ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000200),
+ IO32(ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000),
+ IO32(ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000400),
+ IO32(ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000),
+ IO32(ANACTRL_IO_BASE + 0x74, 0xFFFF0FF5, 0x0000F000),
+ IO32(ANACTRL_IO_BASE + 0x78, 0xFF00FF00, 0x00100010),
+ IO32(ANACTRL_IO_BASE + 0x7C, 0xFF0FF0FF, 0x00500500),
+ IO32(ANACTRL_IO_BASE + 0x80, 0xFFFFFFE7, 0x00000000),
+ IO32(ANACTRL_IO_BASE + 0x60, 0xFFCFFFFF, 0x00300000),
+ IO32(ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00),
+ IO32(ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000),
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x40), 0x00000000, 0xCB8410DE,
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xFFFFDCED, 0x00002002,
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x78), 0xFFFFFF8E, 0x00000011,
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x80), 0xFFFF0000, 0x00009923,
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x88), 0xFFFFFFFE, 0x00000000,
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8C), 0xFFFF0000, 0x0000007F,
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xDC), 0xFFFEFFFF, 0x00010000,
+ PCM(0, 0, 0, 0x40, 0x00000000, 0xCB8410DE),
+ PCM(0, 0, 0, 0x48, 0xFFFFDCED, 0x00002002),
+ PCM(0, 0, 0, 0x78, 0xFFFFFF8E, 0x00000011),
+ PCM(0, 0, 0, 0x80, 0xFFFF0000, 0x00009923),
+ PCM(0, 0, 0, 0x88, 0xFFFFFFFE, 0x00000000),
+ PCM(0, 0, 0, 0x8C, 0xFFFF0000, 0x0000007F),
+ PCM(0, 0, 0, 0xDC, 0xFFFEFFFF, 0x00010000),
- RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x40), 0x00000000, 0xCB8410DE,
- RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFFFF7B, 0x00000084,
- RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
+ PCM(0, 1, 0, 0x40, 0x00000000, 0xCB8410DE),
+ PCM(0, 1, 0, 0x74, 0xFFFFFF7B, 0x00000084),
+ PCM(0, 1, 0, 0xF8, 0xFFFFFFCF, 0x00000010),
- RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xC4), 0xFFFFFFFE, 0x00000001,
- RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF0), 0x7FFFFFFD, 0x00000002,
- RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
+ PCM(0, 1, 1, 0xC4, 0xFFFFFFFE, 0x00000001),
+ PCM(0, 1, 1, 0xF0, 0x7FFFFFFD, 0x00000002),
+ PCM(0, 1, 1, 0xF8, 0xFFFFFFCF, 0x00000010),
- RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x40), 0x00000000, 0xCB8410DE,
- RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), 0xFFFFFF00, 0x000000FF,
- RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
+ PCM(0, 8, 0, 0x40, 0x00000000, 0xCB8410DE),
+ PCM(0, 8, 0, 0x68, 0xFFFFFF00, 0x000000FF),
+ PCM(0, 8, 0, 0xF8, 0xFFFFFFBF, 0x00000040), //Enable bridge mode
- RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE,
- RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF,
- RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
+ PCM(0, 9, 0, 0x40, 0x00000000, 0xCB8410DE),
+ PCM(0, 9, 0, 0x68, 0xFFFFFF00, 0x000000FF),
+ PCM(0, 9, 0, 0xF8, 0xFFFFFFBF, 0x00000040), //Enable bridge mode
};
- static const unsigned int ctrl_conf_1_1[] = {
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x40), 0x00000000, 0xCB8410DE,
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x50), 0xFFFFFFFC, 0x00000003,
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x64), 0xFFFFFFFE, 0x00000001,
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x70), 0xFFF0FFFF, 0x00040000,
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xAC), 0xFFFFF0FF, 0x00000100,
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x7C), 0xFFFFFFEF, 0x00000000,
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xC8), 0xFF00FF00, 0x000A000A,
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xD0), 0xF0FFFFFF, 0x03000000,
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000,
+ static const struct rmap ctrl_conf_1_1[] = {
+ PCM(0, 5, 0, 0x40, 0x00000000, 0xCB8410DE),
+ PCM(0, 5, 0, 0x50, 0xFFFFFFFC, 0x00000003),
+ PCM(0, 5, 0, 0x64, 0xFFFFFFFE, 0x00000001),
+ PCM(0, 5, 0, 0x70, 0xFFF0FFFF, 0x00040000),
+ PCM(0, 5, 0, 0xAC, 0xFFFFF0FF, 0x00000100),
+ PCM(0, 5, 0, 0x7C, 0xFFFFFFEF, 0x00000000),
+ PCM(0, 5, 0, 0xC8, 0xFF00FF00, 0x000A000A),
+ PCM(0, 5, 0, 0xD0, 0xF0FFFFFF, 0x03000000),
+ PCM(0, 5, 0, 0xE0, 0xF0FFFFFF, 0x03000000),
};
+ static const struct rmap ctrl_conf_mcp55_only[] = {
+ PCM(0, 1, 1, 0x40, 0x00000000, 0xCB8410DE),
+ PCM(0, 1, 1, 0xE0, 0xFFFFFEFF, 0x00000000),
+ PCM(0, 1, 1, 0xE4, 0xFFFFFFFB, 0x00000000),
+ PCM(0, 1, 1, 0xE8, 0xFFA9C8FF, 0x00003000),
- static const unsigned int ctrl_conf_mcp55_only[] = {
- RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE,
- RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000,
- RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), 0xFFFFFFFB, 0x00000000,
- RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE8), 0xFFA9C8FF, 0x00003000,
+ PCM(0, 4, 0, 0x40, 0x00000000, 0xCB8410DE),
+ PCM(0, 4, 0, 0xF8, 0xFFFFFFCF, 0x00000010),
- RES_PCI_IO, PCI_ADDR(0, 4, 0, 0x40), 0x00000000, 0xCB8410DE,
- RES_PCI_IO, PCI_ADDR(0, 4, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
+ PCM(0, 2, 0, 0x40, 0x00000000, 0xCB8410DE),
- RES_PCI_IO, PCI_ADDR(0, 2, 0, 0x40), 0x00000000, 0xCB8410DE,
+ PCM(0, 2, 1, 0x40, 0x00000000, 0xCB8410DE),
+ PCM(0, 2, 1, 0x64, 0xF87FFFFF, 0x05000000),
+ PCM(0, 2, 1, 0x78, 0xFFC07FFF, 0x00360000),
+ PCM(0, 2, 1, 0x68, 0xFE00D03F, 0x013F2C00),
+ PCM(0, 2, 1, 0x70, 0xFFF7FFFF, 0x00080000),
+ PCM(0, 2, 1, 0x7C, 0xFFFFF00F, 0x00000570),
+ PCM(0, 2, 1, 0xF8, 0xFFFFFFCF, 0x00000010),
- RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x40), 0x00000000, 0xCB8410DE,
- RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x64), 0xF87FFFFF, 0x05000000,
- RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x78), 0xFFC07FFF, 0x00360000,
- RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x68), 0xFE00D03F, 0x013F2C00,
- RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x70), 0xFFF7FFFF, 0x00080000,
- RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x7C), 0xFFFFF00F, 0x00000570,
- RES_PCI_IO, PCI_ADDR(0, 2, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
+ PCM(0, 6, 0, 0x04, 0xFFFFFEFB, 0x00000104),
+ PCM(0, 6, 0, 0x3C, 0xF5FFFFFF, 0x0A000000),
+ PCM(0, 6, 0, 0x40, 0x00C8FFFF, 0x07330000),
+ PCM(0, 6, 0, 0x48, 0xFFFFFFF8, 0x00000005),
+ PCM(0, 6, 0, 0x4C, 0xFE02FFFF, 0x004C0000),
+ PCM(0, 6, 0, 0x74, 0xFFFFFFC0, 0x00000000),
+ PCM(0, 6, 0, 0xC0, 0x00000000, 0xCB8410DE),
+ PCM(0, 6, 0, 0xC4, 0xFFFFFFF8, 0x00000007),
- RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x04), 0xFFFFFEFB, 0x00000104,
- RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000,
- RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x40), 0x00C8FFFF, 0x07330000,
- RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x48), 0xFFFFFFF8, 0x00000005,
- RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x4C), 0xFE02FFFF, 0x004C0000,
- RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000,
- RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE,
- RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
-
- RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
-
+ PCM(0, 1, 0, 0x78, 0xC0FFFFFF, 0x19000000),
#if MCP55_USE_AZA == 1
- RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,
+ PCM(0, 6, 1, 0x40, 0x00000000, 0xCB8410DE),
-// RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1<<14), 1<<14,
+// PCM(0, 1, 1, 0xE4), ~(1<<14, 1<<14)),
#endif
// play a while with GPIO in MCP55
#ifdef MCP55_MB_SETUP
@@ -297,39 +292,39 @@
#endif
#if MCP55_USE_AZA == 1
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3<<2), (2<<2),
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3<<2), (2<<2),
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3<<2), (2<<2),
+ IO8(SYSCTRL_IO_BASE + 0xc0+ 21, ~(3<<2), (2<<2)),
+ IO8(SYSCTRL_IO_BASE + 0xc0+ 22, ~(3<<2), (2<<2)),
+ IO8(SYSCTRL_IO_BASE + 0xc0+ 46, ~(3<<2), (2<<2)),
#endif
};
- static const unsigned int ctrl_conf_master_only[] = {
+ static const struct rmap ctrl_conf_master_only[] = {
- RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000,
+ IO32(ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000),
//Master MCP55 ????YHLU
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
+ IO8( SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2)),
};
- static const unsigned int ctrl_conf_2[] = {
+ static const struct rmap ctrl_conf_2[] = {
/* I didn't put pcie related stuff here */
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0,
- RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFF7FFF, 0x00008000,
+ PCM(0, 0, 0, 0x74, 0xFFFFF00F, 0x000009D0),
+ PCM(0, 1, 0, 0x74, 0xFFFF7FFF, 0x00008000),
- RES_PORT_IO_32, SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000,
+ IO32(SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000),
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012,
+ IO32(ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012),
#if MCP55_USE_NIC == 1
- RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1<<22)|(1<<20)), (1<<22)|(1<<20),
+ PCM(0, 1, 1, 0xe4, ~((1<<22)|(1<<20)), (1<<22)|(1<<20)),
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
+ IO8(SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(0<<0))),
+ IO8(SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(1<<0))),
#endif
};
@@ -341,23 +336,23 @@
mcp55_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]),
- PCI_BDF(busn[j], devn[j], 0), io_base[j]);
+ PCI_BDF(busn[j], devn[j], 0), io_base[j], 0);
for(i=0; i<3; i++) { // three SATA
setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]),
- PCI_BDF(busn[j], devn[j], i), io_base[j]);
+ PCI_BDF(busn[j], devn[j], i), io_base[j], 0);
}
if(busn[j] == 0) {
setup_resource_map_x_offset(ctrl_conf_mcp55_only, sizeof(ctrl_conf_mcp55_only)/sizeof(ctrl_conf_mcp55_only[0]),
- PCI_BDF(busn[j], devn[j], 0), io_base[j]);
+ PCI_BDF(busn[j], devn[j], 0), io_base[j], 0);
}
if( (busn[j] == 0) && (mcp55_num>1) ) {
setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]),
- PCI_BDF(busn[j], devn[j], 0), io_base[j]);
+ PCI_BDF(busn[j], devn[j], 0), io_base[j], 0);
}
setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]),
- PCI_BDF(busn[j], devn[j], 0), io_base[j]);
+ PCI_BDF(busn[j], devn[j], 0), io_base[j], 0);
}
@@ -408,10 +403,8 @@
busnx = ht_c_index * HT_CHAIN_BUSN_D;
for(devnx=0;devnx<0x20;devnx++) {
u32 id;
- struct device *dev;
-#error dev is not set up
// dev = PCI_BDF(busnx, devnx, 0);
- id = pci_read_config32(dev, PCI_VENDOR_ID);
+ id = pci_read_config32(busnx, devnx<<3, PCI_VENDOR_ID);
if(id == 0x036910de) {
busn[mcp55_num] = busnx;
devn[mcp55_num] = devnx;
