coreboot July 2008

coreboot@coreboot.org

58 participants
214 discussions

Re: [coreboot] r3416 - trunk/util/flashrom
by Stefan Reinauer 07 Jul '08

07 Jul '08

svn(a)coreboot.org wrote: > Author: hailfinger > Date: 2008-07-07 01:04:01 +0200 (Mon, 07 Jul 2008) > New Revision: 3416 > > Modified: > trunk/util/flashrom/flash.h > trunk/util/flashrom/flashchips.c > Log: > r3415 removed symbolic constants for device IDs by accident. > flash.h is a database of known IDs, whereas flashchips.c is a database > of chips for which support has been implemented. Keep it that way. > > Trivial. > > NACK. This was done on purpose, not by accident. As discussed before, we will not pursue the useless facility of defines for those IDs anymore because they serve no purpose. Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

3 3

r3418 - trunk/util/flashrom
by svn＠coreboot.org 07 Jul '08

07 Jul '08

Author: stuge Date: 2008-07-07 08:38:51 +0200 (Mon, 07 Jul 2008) New Revision: 3418 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/it87spi.c trunk/util/flashrom/spi.c trunk/util/flashrom/spi.h Log: flashrom: Trivial SPI cleanups While writing a new SPI driver I fixed some things in the SPI code: All calls to spi_command() had unneccessary #define duplications, and in some cases the read count define could theoretically become harmful because NULL was passed for the read buffer. Avoid a crash, should someone change the #defines. I also noticed that the only caller of spi_page_program() was the it87 driver, and spi_page_program() could only call back into the it87 driver. Removed the function for easier-to-follow code and made it8716f_spi_page_program() static. The ichspi driver's static page functions are already static. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-07-07 05:14:06 UTC (rev 3417) +++ trunk/util/flashrom/flash.h 2008-07-07 06:38:51 UTC (rev 3418) @@ -423,7 +423,6 @@ uint8_t spi_read_status_register(); void spi_disable_blockprotect(void); void spi_byte_program(int address, uint8_t byte); -void spi_page_program(int block, uint8_t *buf, uint8_t *bios); void spi_nbyte_read(int address, uint8_t *bytes, int len); /* 82802ab.c */ @@ -447,7 +446,6 @@ int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf); int it8716f_spi_chip_write(struct flashchip *flash, uint8_t *buf); -void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios); /* jedec.c */ uint8_t oddparity(uint8_t val); Modified: trunk/util/flashrom/it87spi.c =================================================================== --- trunk/util/flashrom/it87spi.c 2008-07-07 05:14:06 UTC (rev 3417) +++ trunk/util/flashrom/it87spi.c 2008-07-07 06:38:51 UTC (rev 3418) @@ -192,7 +192,7 @@ } /* Page size is usually 256 bytes */ -void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios) { +static void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios) { int i; spi_write_enable(); @@ -261,7 +261,7 @@ it8716f_over512k_spi_chip_write(flash, buf); } else { for (i = 0; i < total_size / 256; i++) { - spi_page_program(i, buf, (uint8_t *)flash->virtual_memory); + it8716f_spi_page_program(i, buf, (uint8_t *)flash->virtual_memory); } } return 0; Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2008-07-07 05:14:06 UTC (rev 3417) +++ trunk/util/flashrom/spi.c 2008-07-07 06:38:51 UTC (rev 3418) @@ -51,7 +51,7 @@ { const unsigned char cmd[JEDEC_RDID_OUTSIZE] = {JEDEC_RDID}; - if (spi_command(JEDEC_RDID_OUTSIZE, bytes, cmd, readarr)) + if (spi_command(sizeof(cmd), bytes, cmd, readarr)) return 1; printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1], readarr[2]); return 0; @@ -61,7 +61,7 @@ { const unsigned char cmd[JEDEC_RES_OUTSIZE] = {JEDEC_RES, 0, 0, 0}; - if (spi_command(JEDEC_RES_OUTSIZE, JEDEC_RES_INSIZE, cmd, readarr)) + if (spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr)) return 1; printf_debug("RES returned %02x.\n", readarr[0]); return 0; @@ -72,7 +72,7 @@ const unsigned char cmd[JEDEC_WREN_OUTSIZE] = {JEDEC_WREN}; /* Send WREN (Write Enable) */ - spi_command(JEDEC_WREN_OUTSIZE, JEDEC_WREN_INSIZE, cmd, NULL); + spi_command(sizeof(cmd), 0, cmd, NULL); } void spi_write_disable() @@ -80,7 +80,7 @@ const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = {JEDEC_WRDI}; /* Send WRDI (Write Disable) */ - spi_command(JEDEC_WRDI_OUTSIZE, JEDEC_WRDI_INSIZE, cmd, NULL); + spi_command(sizeof(cmd), 0, cmd, NULL); } static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) @@ -182,10 +182,10 @@ uint8_t spi_read_status_register() { const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = {JEDEC_RDSR}; - unsigned char readarr[1]; + unsigned char readarr[JEDEC_RDSR_INSIZE]; /* Read Status Register */ - spi_command(JEDEC_RDSR_OUTSIZE, JEDEC_RDSR_INSIZE, cmd, readarr); + spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr); return readarr[0]; } @@ -273,7 +273,7 @@ spi_disable_blockprotect(); spi_write_enable(); /* Send CE (Chip Erase) */ - spi_command(JEDEC_CE_C7_OUTSIZE, JEDEC_CE_C7_INSIZE, cmd, NULL); + spi_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-85 s, so wait in 1 s steps. */ @@ -296,7 +296,7 @@ cmd[3] = (addr & 0x000000ff); spi_write_enable(); /* Send BE (Block Erase) */ - spi_command(JEDEC_BE_D8_OUTSIZE, JEDEC_BE_D8_INSIZE, cmd, NULL); + spi_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -315,7 +315,7 @@ spi_write_enable(); /* Send SE (Sector Erase) */ - spi_command(JEDEC_SE_OUTSIZE, JEDEC_SE_INSIZE, cmd, NULL); + spi_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 15-800 ms, so wait in 10 ms steps. */ @@ -324,21 +324,6 @@ return 0; } -void spi_page_program(int block, uint8_t *buf, uint8_t *bios) -{ - switch (flashbus) { - case BUS_TYPE_IT87XX_SPI: - it8716f_spi_page_program(block, buf, bios); - break; - case BUS_TYPE_ICH7_SPI: - case BUS_TYPE_ICH9_SPI: - printf_debug("%s called, but not implemented for ICH\n", __FUNCTION__); - break; - default: - printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__); - } -} - /* * This is according the SST25VF016 datasheet, who knows it is more * generic that this... @@ -348,7 +333,7 @@ const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = {JEDEC_WRSR, (unsigned char)status}; /* Send WRSR (Write Status Register) */ - spi_command(JEDEC_WRSR_OUTSIZE, JEDEC_WRSR_INSIZE, cmd, NULL); + spi_command(sizeof(cmd), 0, cmd, NULL); } void spi_byte_program(int address, uint8_t byte) @@ -361,7 +346,7 @@ }; /* Send Byte-Program */ - spi_command(JEDEC_BYTE_PROGRAM_OUTSIZE, JEDEC_BYTE_PROGRAM_INSIZE, cmd, NULL); + spi_command(sizeof(cmd), 0, cmd, NULL); } void spi_disable_blockprotect(void) @@ -386,7 +371,7 @@ }; /* Send Read */ - spi_command(JEDEC_READ_OUTSIZE, len, cmd, bytes); + spi_command(sizeof(cmd), len, cmd, bytes); } int spi_chip_read(struct flashchip *flash, uint8_t *buf) Modified: trunk/util/flashrom/spi.h =================================================================== --- trunk/util/flashrom/spi.h 2008-07-07 05:14:06 UTC (rev 3417) +++ trunk/util/flashrom/spi.h 2008-07-07 06:38:51 UTC (rev 3418) @@ -49,7 +49,7 @@ #define JEDEC_CE_60_OUTSIZE 0x01 #define JEDEC_CE_60_INSIZE 0x00 -/* Chip Erase 0xc7 is supported by ST/EON/Macronix chips. */ +/* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */ #define JEDEC_CE_C7 0xc7 #define JEDEC_CE_C7_OUTSIZE 0x01 #define JEDEC_CE_C7_INSIZE 0x00

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r3417 - trunk/util/flashrom
by svn＠coreboot.org 07 Jul '08

07 Jul '08

Author: stuge Date: 2008-07-07 07:14:06 +0200 (Mon, 07 Jul 2008) New Revision: 3417 Modified: trunk/util/flashrom/ichspi.c Log: flashrom: Trivial indent fix in ichspi.c Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/ichspi.c =================================================================== --- trunk/util/flashrom/ichspi.c 2008-07-06 23:04:01 UTC (rev 3416) +++ trunk/util/flashrom/ichspi.c 2008-07-07 05:14:06 UTC (rev 3417) @@ -573,9 +573,9 @@ break; } - if (flashbus == BUS_TYPE_VIA_SPI) { - maxdata = 16; - } + if (flashbus == BUS_TYPE_VIA_SPI) + maxdata = 16; + for (j = 0; j < erase_size / page_size; j++) { ich_spi_write_page(flash, (void *)(buf + (i * erase_size) + (j * page_size)), (i * erase_size) + (j * page_size), maxdata);

1 0

r3416 - trunk/util/flashrom
by svn＠coreboot.org 07 Jul '08

07 Jul '08

Author: hailfinger Date: 2008-07-07 01:04:01 +0200 (Mon, 07 Jul 2008) New Revision: 3416 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c Log: r3415 removed symbolic constants for device IDs by accident. flash.h is a database of known IDs, whereas flashchips.c is a database of chips for which support has been implemented. Keep it that way. Trivial. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-07-06 17:35:30 UTC (rev 3415) +++ trunk/util/flashrom/flash.h 2008-07-06 23:04:01 UTC (rev 3416) @@ -119,6 +119,9 @@ #define AMIC_ID 0x7F37 /* AMIC */ #define AMIC_ID_NOPREFIX 0x37 /* AMIC */ #define AMIC_A25L40P 0x2013 +#define AMIC_A29002B 0x0d +#define AMIC_A29002T 0x8c +#define AMIC_A29040B 0x86 #define AMIC_A49LF040A 0x9d #define ASD_ID 0x25 /* ASD, not listed in JEP106W */ Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-07-06 17:35:30 UTC (rev 3415) +++ trunk/util/flashrom/flashchips.c 2008-07-06 23:04:01 UTC (rev 3416) @@ -42,9 +42,9 @@ {"Atmel", "AT49F002(N)T", ATMEL_ID, AT_49F002NT, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"AMIC", "A25L40P", AMIC_ID, AMIC_A25L40P, 512, 256, TEST_OK_PREW, probe_spi_rdid4, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"AMIC", "A29002B", 0x37, 0x0d, 256, 64 * 1024, TEST_UNTESTED, probe_29f002, erase_29f002, write_29f002}, - {"AMIC", "A29002T", 0x37, 0x8c, 256, 64 * 1024, TEST_OK_PREW, probe_29f002, erase_29f002, write_29f002}, - {"AMIC", "A29040B", 0x37, 0x86, 512, 64 * 1024, TEST_OK_PR, probe_29f040b, erase_29f040b, write_29f040b}, + {"AMIC", "A29002B", AMIC_ID_NOPREFIX, AMIC_A29002B, 256, 64 * 1024, TEST_UNTESTED, probe_29f002, erase_29f002, write_29f002}, + {"AMIC", "A29002T", AMIC_ID_NOPREFIX, AMIC_A29002T, 256, 64 * 1024, TEST_OK_PREW, probe_29f002, erase_29f002, write_29f002}, + {"AMIC", "A29040B", AMIC_ID_NOPREFIX, AMIC_A29040B, 512, 64 * 1024, TEST_OK_PR, probe_29f040b, erase_29f040b, write_29f040b}, {"AMIC", "A49LF040A", AMIC_ID_NOPREFIX, AMIC_A49LF040A, 512, 64 * 1024, TEST_OK_PREW, probe_49fl00x, erase_49fl00x, write_49fl00x}, {"EMST", "F49B002UA", EMST_ID, EMST_F49B002UA, 256, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, {"EON", "EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec},

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[PATCH] Add A29002bt support to flashrom
by Andreas Thienemann 06 Jul '08

06 Jul '08

This patch adds support to the AMIC A29002 chip in its top and bottom configuration to flashrom. Additionally, the alphabetic order of the AMIC chips was fixed. The datasheet is at <http://www.amictechnology.com/pdf/A29002.pdf>. A29002T PREW functionality was tested and works. Signed-off-by: Andreas Thienemann <andreas(a)bawue.net> --- flash.h | 2 ++ flashchips.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) regards, andreas

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r3415 - trunk/util/flashrom
by svn＠coreboot.org 06 Jul '08

06 Jul '08

Author: stuge Date: 2008-07-06 19:35:30 +0200 (Sun, 06 Jul 2008) New Revision: 3415 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c Log: flashrom: Add AMIC A29002 This patch adds support to the AMIC A29002 chip in its top and bottom configuration to flashrom. Additionally, the alphabetic order of the AMIC chips was fixed. The datasheet is at <http://www.amictechnology.com/pdf/A29002.pdf>. A29002T PREW functionality was tested and works. This flash chip has asymmetric sector layout so it is important to use the mx29f002 driver, which does chip erase before writing, rather than am29f040b, which uses sector erase. Signed-off-by: Andreas Thienemann <andreas(a)bawue.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-07-05 09:48:30 UTC (rev 3414) +++ trunk/util/flashrom/flash.h 2008-07-06 17:35:30 UTC (rev 3415) @@ -119,7 +119,6 @@ #define AMIC_ID 0x7F37 /* AMIC */ #define AMIC_ID_NOPREFIX 0x37 /* AMIC */ #define AMIC_A25L40P 0x2013 -#define AMIC_A29040B 0x86 #define AMIC_A49LF040A 0x9d #define ASD_ID 0x25 /* ASD, not listed in JEP106W */ Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-07-05 09:48:30 UTC (rev 3414) +++ trunk/util/flashrom/flashchips.c 2008-07-06 17:35:30 UTC (rev 3415) @@ -42,8 +42,10 @@ {"Atmel", "AT49F002(N)T", ATMEL_ID, AT_49F002NT, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"AMIC", "A25L40P", AMIC_ID, AMIC_A25L40P, 512, 256, TEST_OK_PREW, probe_spi_rdid4, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"AMIC", "A29002B", 0x37, 0x0d, 256, 64 * 1024, TEST_UNTESTED, probe_29f002, erase_29f002, write_29f002}, + {"AMIC", "A29002T", 0x37, 0x8c, 256, 64 * 1024, TEST_OK_PREW, probe_29f002, erase_29f002, write_29f002}, + {"AMIC", "A29040B", 0x37, 0x86, 512, 64 * 1024, TEST_OK_PR, probe_29f040b, erase_29f040b, write_29f040b}, {"AMIC", "A49LF040A", AMIC_ID_NOPREFIX, AMIC_A49LF040A, 512, 64 * 1024, TEST_OK_PREW, probe_49fl00x, erase_49fl00x, write_49fl00x}, - {"AMIC", "A29040B", AMIC_ID_NOPREFIX, AMIC_A29040B, 512, 64 * 1024, TEST_OK_PR, probe_29f040b, erase_29f040b, write_29f040b}, {"EMST", "F49B002UA", EMST_ID, EMST_F49B002UA, 256, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, {"EON", "EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"EON", "EN29F002(A)(N)T", EON_ID, EN_29F002T, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec},

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[PATCH] Add A29002bt support to flashrom
by Andreas Thienemann 06 Jul '08

06 Jul '08

1 0

Question about call LegacyBIOS in the memory(GSoC__SCSI boot)
by Zhang Rui 06 Jul '08

06 Jul '08

Hello, LegacyBIOS could be added to coreboot.rom by lar tool now. I modified the Makefile in arch/x86 I am now a little lost in x86emu of coreboot v3. And I have some questions. Please help me. 1. What is the address of post() in LegacyBIOS? >> and then how can we call the post() function? > > Well, that will require some work. :-) Take a look at how the build > exports the assembler stub "post32" (in post.c) - which calls _start() > (also in post.c). > asm( ".global post32\n" "post32:\n" "cli\n" "cld\n" "lidtl " __stringify(0xf0000 | OFFSET_pmode_IDT_info) "\n" "lgdtl " __stringify(0xf0000 | OFFSET_rombios32_gdt_48) "\n" "movl $" __stringify(BUILD_STACK_ADDR) ", %esp\n" "ljmp $0x10, $_start\n" ); According to these asm codes, we should load the idt and gdt and set the stack point esp before we jump to the start() function. But these codes are in LegacyBIOS, so "_start" can be used to present the address of start(). How can I call post outside LegacyBIOS but just use the bios.bin file(copied to 0xf0000)? Can this function have a fixed address? or is there another approach? 2. How to modify the post() method in LegacyBIOS? post() will auto boot the system at the end. But we want it return to coreboot. So what is the boot code at the end of the function? Is this? init_boot_vectors(); dprintf(1, "Scan for option roms\n"); rom_scan(0xc8000, 0xe0000); May be we could write another funcion post_noboot() without the boot code and have a fixed address? 3. How to get the address of idt of LegacyBIOS? "lidtl " __stringify(0xf0000 | OFFSET_pmode_IDT_info) "\n" "lgdtl " __stringify(0xf0000 | OFFSET_rombios32_gdt_48) "\n" "movl $" __stringify(BUILD_STACK_ADDR) ", %esp\n" I noticed that OFFSET_pmode_IDT_info is defined in rom16.offset.auto.h. But this header file is generated in building process and I do not find the rule for it in the Makefile. So I want to know how can I get the value of OFFSET_pmode_IDT_info? So do OFFSET_rombios32_gdt_48 and BUILD_STACK_ADDR. Kevin, could you help me with these three questions? Thanks. 4. Where is the entrance call of util/x86emu in coreboot v3? There are several x86EMU_XXX function exported in e86emu.h. But they are called only in run_bios() in biosemu.c. I placed a printk at the beginning of run_bios() but it seems not executed. How does the codes in util/x86emu used? Where is the entrance call of util/x86emu in coreboot v3? Where should I place the code to extract LegacyBIOS to the memory? Should I write a new function and export it? Stefan, could you help me with this question? Thanks. Best regards. Zhang Rui

2 2

Top 256 bytes in ROM for Nvidia
by Carl-Daniel Hailfinger 06 Jul '08

06 Jul '08

Hi Yinghai, is there any public information about the usage of the top 256 bytes in ROM for Nvidia chipsets? The only information I found was http://coreboot.org/pipermail/coreboot/2005-November/012918.html but that does not explain the reasons or give me a memory map. I'm looking at this diff and wonder if 0x80 is the only possible location for ID information in the ROM. --- ./src/arch/i386/lib/id.lds 2007-12-30 01:04:02.000000000 +0100 +++ ./src/southbridge/nvidia/ck804/id.lds 2007-12-30 01:04:06.000000000 +0100 @@ -1,5 +1,5 @@ SECTIONS { - . = (_ROMBASE + ROM_IMAGE_SIZE - 0x10) - (__id_end - __id_start); + . = (_ROMBASE + ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start); .id (.): { *(.id) } Regards, Carl-Daniel

2 1

[PATCH] flashrom: Recognize the MSI K8N Neo3
by Carl-Daniel Hailfinger 05 Jul '08

05 Jul '08

Recognize the MSI K8N Neo3 coreboot ID string in flashrom. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-tmp1/board_enable.c =================================================================== --- flashrom-tmp1/board_enable.c (Revision 3412) +++ flashrom-tmp1/board_enable.c (Arbeitskopie) @@ -586,7 +586,7 @@ {0x1022, 0x7468, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, "iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise_2e}, {0x10de, 0x005e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - "msi", "k8n-neo3", "MSI K8N Neo3", w83627thf_gpio4_4_raise_4e}, + "MSI", "K8N Neo3 (MS-7135)", "MSI K8N Neo3", w83627thf_gpio4_4_raise_4e}, {0x1022, 0x746B, 0x1022, 0x36C0, 0x0000, 0x0000, 0x0000, 0x0000, "AGAMI", "ARUMA", "agami Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, -- http://www.hailfinger.org/

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coreboot July 2008