coreboot April 2008

coreboot@coreboot.org

75 participants
404 discussions

r3276 - trunk/coreboot-v2/src/southbridge/intel/i3100
by svn＠coreboot.org 30 Apr '08

30 Apr '08

Author: eswierk Date: 2008-04-30 20:29:35 +0200 (Wed, 30 Apr 2008) New Revision: 3276 Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c Log: By default, the Intel 3100 LPC interface enables only I/O range 0x3f8 for both serial ports, making it challenging to use COM2 for the early console. Enable the traditional I/O ranges 0x3f8 for COM1 and 0x2f8 for COM2. Signed-off-by: Ed Swierk <eswierk(a)arastra.com> Acked-by: Joseph Smith <joe(a)settoplinux.org> Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c 2008-04-29 13:46:38 UTC (rev 3275) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c 2008-04-30 18:29:35 UTC (rev 3276) @@ -23,6 +23,7 @@ device_t dev = PCI_DEV(0x0, 0x1f, 0x0); /* Enable decoding of I/O locations for SuperIO devices */ + pci_write_config16(dev, 0x80, 0x0010); pci_write_config16(dev, 0x82, 0x340f); }

1 0

QEMU Keyboard problems in v2
by Myles Watson 30 Apr '08

30 Apr '08

Does anyone know why the keyboard isn't working in v2 for qemu? I'll try to track it down, but I was hoping someone knew already. If you use tint, filo, or adlo as a payload (probably others as well), the key mappings are wrong. Thanks, Myles

2 4

flashrom-1.0
by Peter Stuge 30 Apr '08

30 Apr '08

I would like to release flashrom-1.0 before the weekend. There was a bit of discussion on IRC tonight and I found there are others who are also looking forward to a release. Not so much because we think flashrom is currently in a particularly awesome state, but rather because we would like to get it packaged, distributed, used and marketed more - and that is really all version numbers are good for anyway. There are many pending patches in people's working copies that are on their way into the repo, and that is great. I would like nothing more than to make a 1.1 release shortly after 1.0, and I hope noone feels that flashrom should freeze somehow just because it now has a version number. I think flashrom will always be work in progress to a high degree, especially since the probing can never be fool proof because of our dearest PC architecture, but I still would like to make releases. While some parts of trunk flashrom may not be production quality, there are some parts that are indeed production quality and that have been heavily used. I think 1.0 is a nice round number and a great starting point for future improvements. It also communicates the fact that at least parts of flashrom are very good and quite usable, as has been the case for several years already. :) I've made a preliminary roadmap or action plan for 1.0: 1 handle the possibility of NULL flash chip function pointer derefs 2 add a tested flag to the flash chip table, most will be untested now 3 Carl-Daniel has a patch with fake flash chips of different sizes that is good to let people at least read the flash chip even if there is no support. Either this goes in as is and we add a -C --force-chip option (or similar) or we could make a special --force-read command to avoid cluttering the flash chip list with dirty fake chips. 4 go over text output to find and do possible UI improvements 5 change -s and -e into -S and -E, and change -E into -e with the rationale that erase is much more common than "exclude end position" 6 make probes advisory rather than controlling? always have the user confirm the probed chipset before continuing? I can do 1, 2 and 4. If there is agreement I'd love to do 5 too. In 4 I include adding a message for the user about the mainboards that need to be specified manually when board probing fails. Please share your thoughts - and in particular anything on 3 or 6. The plan is to create a repos/tags/flashrom-1.0 tag of the rev that goes into release, and publish the release with a tarball on the Flashrom wiki page. For a bit of fun (gotta have some fun! :) we can have codenames for releases when we feel like it, the 1.0 favorite is "apt apology." Objections? More must-have stuff before 1.0? I don't want to add too much stuff, just trim away the worst rough edges and make a release very soon. //Peter

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[PATCH] v3: rework Geode LX RAMinit DIMM size formula
by Carl-Daniel Hailfinger 30 Apr '08

30 Apr '08

Rework Geode LX RAMinit DIMM size formula to be more understandable. Added benefit is complaining loudly for unsupported 2 GB DIMM size. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-stuff/northbridge/amd/geodelx/raminit.c =================================================================== --- LinuxBIOSv3-stuff/northbridge/amd/geodelx/raminit.c (Revision 659) +++ LinuxBIOSv3-stuff/northbridge/amd/geodelx/raminit.c (Arbeitskopie) @@ -151,16 +151,12 @@ banner(BIOS_DEBUG, "SPDBANKDENSITY"); dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY); - /* Align so 1 GB (bit 0) is bit 8. This is a little weird to get gcc - * to not optimize this out. + /* Bits 0-1 have been redefined by JEDEC to contain what would have + * been in non-existing bits 8 (1GB) and 9 (2GB). Move bits 0-1 to + * bits 8-9 and mask bits 0-1 off. */ - dimm_size |= (dimm_size << 8); + dimm_size = ((dimm_size & 0x3) << 8) | (dimm_size & ~0x3); - /* And off 2 GB DIMM size: not supported and the 1 GB size we just - * moved up to bit 8 as well as all the extra on top. - */ - dimm_size &= 0x01FC; - /* Module Density * Module Banks */ /* Shift to multiply by the number of DIMM banks. */ dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; -- http://www.hailfinger.org/

2 2

DBE62 v3 strangeness since v3 rev 649
by Carl-Daniel Hailfinger 30 Apr '08

30 Apr '08

Hi Ron, this one is for you: Your commit 649 had a few probably unintended side effects: - set_delay_control thinks zero DIMMs are installed because SPD_PRIMARY_SDRAM_WIDTH does not exist in the SPD table. - Due to that, the GLCP_DELAY_CONTROLS msr is set to 0. Please confirm that you really wanted these settings. Regards, Carl-Daniel

3 8

r672 - coreboot-v3/mainboard/artecgroup/dbe62
by svn＠coreboot.org 30 Apr '08

30 Apr '08

Author: rminnich Date: 2008-04-30 06:14:52 +0200 (Wed, 30 Apr 2008) New Revision: 672 Modified: coreboot-v3/mainboard/artecgroup/dbe62/initram.c Log: Add back in missing line of DRAM info. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: coreboot-v3/mainboard/artecgroup/dbe62/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/initram.c 2008-04-30 04:12:56 UTC (rev 671) +++ coreboot-v3/mainboard/artecgroup/dbe62/initram.c 2008-04-30 04:14:52 UTC (rev 672) @@ -63,6 +63,7 @@ {SPD_MIN_RAS_TO_CAS_DELAY, 0x58}, {SPD_tRRD, 0x3c}, {SPD_tRP, 0x58}, + {SPD_PRIMARY_SDRAM_WIDTH, 8}, {SPD_NUM_BANKS_PER_SDRAM, 0x4}, {SPD_NUM_COLUMNS, 0x8}, {SPD_NUM_DIMM_BANKS, 0x1},

1 0

r671 - coreboot-v3/northbridge/amd/geodelx
by svn＠coreboot.org 30 Apr '08

30 Apr '08

Author: rminnich Date: 2008-04-30 06:12:56 +0200 (Wed, 30 Apr 2008) New Revision: 671 Modified: coreboot-v3/northbridge/amd/geodelx/raminit.c Log: Rework Geode LX RAMinit DIMM size formula to be more understandable. Added benefit is complaining loudly for unsupported 2 GB DIMM size. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested on the dbe62 up to and including Etherboot. Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/northbridge/amd/geodelx/raminit.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-04-29 11:49:42 UTC (rev 670) +++ coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-04-30 04:12:56 UTC (rev 671) @@ -151,16 +151,12 @@ banner(BIOS_DEBUG, "SPDBANKDENSITY"); dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY); - /* Align so 1 GB (bit 0) is bit 8. This is a little weird to get gcc - * to not optimize this out. - */ - dimm_size |= (dimm_size << 8); + /* Bits 0-1 have been redefined by JEDEC to contain what would have + * been in non-existing bits 8 (1GB) and 9 (2GB). Move bits 0-1 to + * bits 8-9 and mask bits 0-1 off. + */ + dimm_size = ((dimm_size & 0x3) << 8) | (dimm_size & ~0x3); - /* And off 2 GB DIMM size: not supported and the 1 GB size we just - * moved up to bit 8 as well as all the extra on top. - */ - dimm_size &= 0x01FC; - /* Module Density * Module Banks */ /* Shift to multiply by the number of DIMM banks. */ dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1;

1 0

ASUS SP98-N BIOS
by Andreas Rudin 29 Apr '08

29 Apr '08

Hello. We have 600 PCs with ASUS SP98-N mainboards (supersocket7, 2 sdram slots, usb, vga, sound and lan onboard) here with us, which we want to get running as clients on LTSP (www.ltsp.org) - systems, we provide for social and educational projects in different African countries. To use these mainboards with LTSP it would be a great advantage to be able to boot from the onboard LAN. This mainboard has a SIS 5598 chip and an onboard Intel 82558 LAN-Chip. Although you find in the manual of the mainboard in section 4.4.1 "Details of Bios Features Setup", in the boot sequence the options: LAN,A,C and LAN,C,A I tried all the available BIOS-versions provided by ASUS, and none of them have this option. On coreboot.org neither this mainboard nor the SIS 5598 is mentioned. Is there anyone, who already has some experience with this mainboard or chipset? If not, I'm now searching for someone, who could help me to understand the ASUS Bios in order to be able to eventually change the settings. The third way would be to integrate the boot image for the Intel 82558 chip, which can be found on etherboot.org to the mainbaord bios. We already have tried this, but there is the problem, that there is not enough empty space for it in the existing bios. This means we have to throw unneeded components out to make place for the etherboot rom. But here again I need help, because we don't understand, where the different parts of the bios are located inside the binary code of the bios. So any further ideas and help are really appriciated very much :-) Thanks Andreas -- revamp-it Rosengartenstr. 1 8037 Zürich 0041 43 960 32 64 sip:arevamp@ekiga.net skype: arevamp www.revamp-it.ch https://wiki.ubuntu.com/AndreasRudin OpenPGP public key: www.revamp-it.ch/keys/Andreas_Rudin_0xBACC2013_pub.asc

2 1

Problem booting 2.6.24 with db800-Board
by Uwe Schwarz 29 Apr '08

29 Apr '08

Hi, I try to boot linux 2.6.24 with coreboot-v2 and filo on a db800 (geode lx) board, but it hangs when probing for PCI. I tried to follow instructions on http://www.coreboot.org/Creating_Valid_IRQ_Tables to find out my IRQ-Table. Attached is a Capture of my boot. With coreinfo as payload it boots up correct. Maybe someone can point me in the right direction to solve this issue. Uwe

4 4

r3275 - trunk/util/flashrom
by svn＠coreboot.org 29 Apr '08

29 Apr '08

Author: stepan Date: 2008-04-29 15:46:38 +0200 (Tue, 29 Apr 2008) New Revision: 3275 Modified: trunk/util/flashrom/chipset_enable.c Log: flashrom: Enable ROM decode range to 1MB for vt8237r Signed-off-by: Bari Ari <bari(a)onelabs.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2008-04-28 17:51:09 UTC (rev 3274) +++ trunk/util/flashrom/chipset_enable.c 2008-04-29 13:46:38 UTC (rev 3275) @@ -234,6 +234,9 @@ { uint8_t val; + /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF*/ + pci_write_byte(dev, 0x41, 0x7f); + /* ROM write enable */ val = pci_read_byte(dev, 0x40); val |= 0x10;

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coreboot April 2008