coreboot June 2007

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Re: [LinuxBIOS] r396 - in LinuxBIOSv3: include/arch/x86 southbridge/amd/cs5536
by Uwe Hermann 29 Jun '07

29 Jun '07

On Thu, Jun 28, 2007 at 07:00:36PM +0200, svn(a)openbios.org wrote: > Modified: LinuxBIOSv3/include/arch/x86/msr.h > =================================================================== > --- LinuxBIOSv3/include/arch/x86/msr.h 2007-06-28 16:48:40 UTC (rev 395) > +++ LinuxBIOSv3/include/arch/x86/msr.h 2007-06-28 17:00:36 UTC (rev 396) > @@ -21,16 +21,15 @@ > #define CPU_X86_MSR_H > > /* standard MSR operations, everyone has written these one hundred times */ > - > -typedef struct msr_struct > +struct msr > { > unsigned lo; > unsigned hi; No 'unsigned' please, use u8, u16, u32, etc. as needed. > -} msr_t; > +}; > > -static inline msr_t rdmsr(unsigned index) > +static inline struct msr rdmsr(unsigned index) ^^^^^^^^ Ditto > { > - msr_t result; > + struct msr result; > __asm__ __volatile__ ( > "rdmsr" > : "=a" (result.lo), "=d" (result.hi) > @@ -39,7 +38,7 @@ > return result; > } > > -static inline void wrmsr(unsigned index, msr_t msr) > +static inline void wrmsr(unsigned index, struct msr msr) Ditto. > { > __asm__ __volatile__ ( > "wrmsr" > > void chipsetinit(void) > { > struct device *dev; > - msr_t msr; > + struct msr msr; ^^ Two spaces where only one should be. I'll fix it one of these days when this patch orgy is over... Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 1

[LinuxBIOS] r409 - LinuxBIOSv3/include/arch/x86
by svn＠openbios.org 29 Jun '07

29 Jun '07

Author: rminnich Date: 2007-06-29 02:23:18 +0200 (Fri, 29 Jun 2007) New Revision: 409 Modified: LinuxBIOSv3/include/arch/x86/msr.h Log: two more unsigned! Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: LinuxBIOSv3/include/arch/x86/msr.h =================================================================== --- LinuxBIOSv3/include/arch/x86/msr.h 2007-06-29 00:22:19 UTC (rev 408) +++ LinuxBIOSv3/include/arch/x86/msr.h 2007-06-29 00:23:18 UTC (rev 409) @@ -27,7 +27,7 @@ u32 hi; }; -static inline struct msr rdmsr(unsigned index) +static inline struct msr rdmsr(u32 index) { struct msr result; __asm__ __volatile__ ( @@ -38,7 +38,7 @@ return result; } -static inline void wrmsr(unsigned index, struct msr msr) +static inline void wrmsr(u32 index, struct msr msr) { __asm__ __volatile__ ( "wrmsr"

1 0

[LinuxBIOS] r408 - LinuxBIOSv3/include/arch/x86
by svn＠openbios.org 29 Jun '07

29 Jun '07

Author: rminnich Date: 2007-06-29 02:22:19 +0200 (Fri, 29 Jun 2007) New Revision: 408 Modified: LinuxBIOSv3/include/arch/x86/msr.h Log: minor cleanup; trivial fix so I'm just committing it. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: LinuxBIOSv3/include/arch/x86/msr.h =================================================================== --- LinuxBIOSv3/include/arch/x86/msr.h 2007-06-29 00:09:24 UTC (rev 407) +++ LinuxBIOSv3/include/arch/x86/msr.h 2007-06-29 00:22:19 UTC (rev 408) @@ -23,11 +23,11 @@ /* standard MSR operations, everyone has written these one hundred times */ struct msr { - unsigned lo; - unsigned hi; + u32 lo; + u32 hi; }; -static inline struct msr rdmsr(unsigned index) +static inline struct msr rdmsr(unsigned index) { struct msr result; __asm__ __volatile__ (

1 0

Re: [LinuxBIOS] r395 - in LinuxBIOSv3/mainboard: adl/msm800sev amd/norwich artecgroup/dbe61 emulation/qemu-x86
by Uwe Hermann 29 Jun '07

29 Jun '07

On Thu, Jun 28, 2007 at 06:48:40PM +0200, svn(a)openbios.org wrote: > Modified: LinuxBIOSv3/mainboard/artecgroup/dbe61/initram.c > =================================================================== > --- LinuxBIOSv3/mainboard/artecgroup/dbe61/initram.c 2007-06-28 16:21:38 UTC (rev 394) > +++ LinuxBIOSv3/mainboard/artecgroup/dbe61/initram.c 2007-06-28 16:48:40 UTC (rev 395) > @@ -43,9 +43,15 @@ > */ > #define GPIO_BASE 0x6100 > > +/* empty function to always fail smbus reads */ Is this done because every board needs this function but this one doesn't use it? > +int smbus_read_byte(unsigned device, unsigned address) No unsigned, please use u16 or something. > +{ > + return -1; > +} > + > static void init_gpio(void) > { > - msr_t msr; > + struct msr_struct msr; > printk(BIOS_DEBUG, "Initializing GPIO module...\n"); > > // initialize the GPIO LBAR > @@ -63,7 +69,7 @@ > * width in bits (byte 6,7) > * = Density per side (byte 31) * number of sides (byte 5) */ > /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */ > - msr_t msr; > + struct msr_struct msr; > > msr.hi = 0x10075012; > msr.lo = 0x00000040; > @@ -101,13 +107,21 @@ > /* Hold Count - how long we will sit in reset */ > #define PLLMSRlo 0x00DE0000 > > +struct wmsr { > + u32 reg; > + struct msr_struct msr; > +} dbe61_msr[] = { > + {.reg = 0x10000020, {.lo = 0xfff80, .hi = 0x20000000}}, > + {.reg = 0x10000021, {.lo = 0x80fffe0, .hi = 0x20000000}}, > + {.reg = 0x40000020, {.lo = 0xfff80, .hi = 0x20000000}}, > + {.reg = 0x40000021, {.lo = 0x80fffe0, .hi = 0x20000000}}, > +}; > + > static void dbe61_msr_init(void) > { > - __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); > - __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); > - > - __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); > - __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); > + int i; > + for(i = 0; i < sizeof(dbe61_msr)/sizeof(dbe61_msr[0]); i++) We want an ARRAY_SIZE macro in some header file for this, it's even recommnended by the coding guidelines. > + wrmsr(dbe61_msr[i].reg, dbe61_msr[i].msr); > } > > int main(void) Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 1

[LinuxBIOS] r407 - in LinuxBIOSv3: arch/x86 arch/x86/geodelx mainboard/adl/msm800sev southbridge/amd/cs5536 superio/winbond/w83627hf
by svn＠openbios.org 29 Jun '07

29 Jun '07

Author: rminnich Date: 2007-06-29 02:09:24 +0200 (Fri, 29 Jun 2007) New Revision: 407 Added: LinuxBIOSv3/arch/x86/geodelx/stage1.c LinuxBIOSv3/mainboard/adl/msm800sev/stage1.c LinuxBIOSv3/southbridge/amd/cs5536/stage1.c LinuxBIOSv3/superio/winbond/w83627hf/stage1.c Removed: LinuxBIOSv3/arch/x86/geodelx/early_init.c LinuxBIOSv3/mainboard/adl/msm800sev/early_init.c LinuxBIOSv3/southbridge/amd/cs5536/cs5536_early_setup.c LinuxBIOSv3/superio/winbond/w83627hf/w83627hf_early_serial.c Modified: LinuxBIOSv3/arch/x86/cachemain.c LinuxBIOSv3/mainboard/adl/msm800sev/Makefile LinuxBIOSv3/southbridge/amd/cs5536/cs5536.h Log: 1. move early_* names to stage1.c 2. rename *_early_init symbols to *_stage1 3. Rename early_init to hardware_stage1 now people can see when things are supposed to happen. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: LinuxBIOSv3/arch/x86/cachemain.c =================================================================== --- LinuxBIOSv3/arch/x86/cachemain.c 2007-06-28 23:59:40 UTC (rev 406) +++ LinuxBIOSv3/arch/x86/cachemain.c 2007-06-29 00:09:24 UTC (rev 407) @@ -29,7 +29,7 @@ void uart_init(void); void die(const char *msg); int find_file(struct mem_file *archive, char *filename, struct mem_file *result); -void early_init(void); +void hardware_stage1(void); // Is this value correct? #define DCACHE_RAM_SIZE 0x8000 @@ -82,7 +82,7 @@ // We have cache as ram running and can start executing code in C. // - early_init(); + hardware_stage1(); // uart_init(); // initialize serial port Deleted: LinuxBIOSv3/arch/x86/geodelx/early_init.c =================================================================== --- LinuxBIOSv3/arch/x86/geodelx/early_init.c 2007-06-28 23:59:40 UTC (rev 406) +++ LinuxBIOSv3/arch/x86/geodelx/early_init.c 2007-06-29 00:09:24 UTC (rev 407) @@ -1,71 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa(a)artecdesign.ee> - * Copyright (C) 2006 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <types.h> -#include <lib.h> -#include <console.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> -#include <msr.h> -#include <io.h> -#include <amd_geodelx.h> -#include <spd.h> - -/** - * geodelx_msr_init Set up Geode LX registers for sane behaviour. Set - * all low memory (under 1MB) to write back. Do some setup for cache - * as ram as well. - */ -void geodelx_msr_init(void) -{ - struct msr msr; - /* Setup access to the cache for under 1MB. */ - msr.hi = 0x24fffc02; - msr.lo = 0x1000A000; /* 0-A0000 write back */ - wrmsr(CPU_RCONF_DEFAULT, msr); - - msr.hi = 0x0; /* write back */ - msr.lo = 0x0; - wrmsr(CPU_RCONF_A0_BF, msr); - wrmsr(CPU_RCONF_C0_DF, msr); - wrmsr(CPU_RCONF_E0_FF, msr); - - /* Setup access to the cache for under 640K. Note MC not setup yet. */ - msr.hi = 0x20000000; - msr.lo = 0xfff80; - wrmsr(MSR_GLIU0 + 0x20, msr); - - msr.hi = 0x20000000; - msr.lo = 0x80fffe0; - wrmsr(MSR_GLIU0 + 0x21, msr); - - msr.hi = 0x20000000; - msr.lo = 0xfff80; - wrmsr(MSR_GLIU1 + 0x20, msr); - - msr.hi = 0x20000000; - msr.lo = 0x80fffe0; - wrmsr(MSR_GLIU1 + 0x21, msr); - -} - Copied: LinuxBIOSv3/arch/x86/geodelx/stage1.c (from rev 406, LinuxBIOSv3/arch/x86/geodelx/early_init.c) =================================================================== --- LinuxBIOSv3/arch/x86/geodelx/stage1.c (rev 0) +++ LinuxBIOSv3/arch/x86/geodelx/stage1.c 2007-06-29 00:09:24 UTC (rev 407) @@ -0,0 +1,71 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa(a)artecdesign.ee> + * Copyright (C) 2006 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd_geodelx.h> +#include <spd.h> + +/** + * geodelx_msr_init Set up Geode LX registers for sane behaviour. Set + * all low memory (under 1MB) to write back. Do some setup for cache + * as ram as well. + */ +void geodelx_msr_init(void) +{ + struct msr msr; + /* Setup access to the cache for under 1MB. */ + msr.hi = 0x24fffc02; + msr.lo = 0x1000A000; /* 0-A0000 write back */ + wrmsr(CPU_RCONF_DEFAULT, msr); + + msr.hi = 0x0; /* write back */ + msr.lo = 0x0; + wrmsr(CPU_RCONF_A0_BF, msr); + wrmsr(CPU_RCONF_C0_DF, msr); + wrmsr(CPU_RCONF_E0_FF, msr); + + /* Setup access to the cache for under 640K. Note MC not setup yet. */ + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU0 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU0 + 0x21, msr); + + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU1 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU1 + 0x21, msr); + +} + Modified: LinuxBIOSv3/mainboard/adl/msm800sev/Makefile =================================================================== --- LinuxBIOSv3/mainboard/adl/msm800sev/Makefile 2007-06-28 23:59:40 UTC (rev 406) +++ LinuxBIOSv3/mainboard/adl/msm800sev/Makefile 2007-06-29 00:09:24 UTC (rev 407) @@ -19,11 +19,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -STAGE0_MAINBOARD_OBJ := $(obj)/superio/winbond/w83627hf/w83627hf_early_serial.o \ +STAGE0_MAINBOARD_OBJ := $(obj)/superio/winbond/w83627hf/stage1.o \ $(obj)/device/pnp_raw.o \ - $(obj)/southbridge/amd/cs5536/cs5536_early_setup.o\ - $(obj)/arch/x86/geodelx/early_init.o \ - $(obj)/mainboard/$(MAINBOARDDIR)/early_init.o + $(obj)/southbridge/amd/cs5536/stage1.o\ + $(obj)/arch/x86/geodelx/stage1.o \ + $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o $(obj)/linuxbios.vpd: $(Q)printf " BUILD DUMMY VPD\n" Deleted: LinuxBIOSv3/mainboard/adl/msm800sev/early_init.c =================================================================== --- LinuxBIOSv3/mainboard/adl/msm800sev/early_init.c 2007-06-28 23:59:40 UTC (rev 406) +++ LinuxBIOSv3/mainboard/adl/msm800sev/early_init.c 2007-06-29 00:09:24 UTC (rev 407) @@ -1,54 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <types.h> -#include <lib.h> -#include <console.h> -#include <post_code.h> -#include <device/device.h> -#include <device/pci.h> -#include <io.h> -#include <device/pnp.h> -#include <string.h> -#include <msr.h> -#include <io.h> -#include <amd_geodelx.h> -#include <southbridge/amd/cs5536/cs5536.h> -#include <superio/winbond/w83627hf/w83627hf.h> - -#define SERIAL_DEV 0x30 - -int early_init(void) -{ - void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase); - post_code(POST_START_OF_MAIN); - - geodelx_msr_init(); - - cs5536_early_setup(); - - /* NOTE: must do this AFTER the early_setup! - * it is counting on some early MSR setup - * for cs5536 - */ - cs5536_disable_internal_uart(); - w83627hf_enable_serial(0x2e, 0x30, 0x3f8); - printk(BIOS_DEBUG, "Done %s\n", __FUNCTION__); -} Copied: LinuxBIOSv3/mainboard/adl/msm800sev/stage1.c (from rev 406, LinuxBIOSv3/mainboard/adl/msm800sev/early_init.c) =================================================================== --- LinuxBIOSv3/mainboard/adl/msm800sev/stage1.c (rev 0) +++ LinuxBIOSv3/mainboard/adl/msm800sev/stage1.c 2007-06-29 00:09:24 UTC (rev 407) @@ -0,0 +1,54 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <post_code.h> +#include <device/device.h> +#include <device/pci.h> +#include <io.h> +#include <device/pnp.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd_geodelx.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <superio/winbond/w83627hf/w83627hf.h> + +#define SERIAL_DEV 0x30 + +int hardware_stage1(void) +{ + void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase); + post_code(POST_START_OF_MAIN); + + geodelx_msr_init(); + + cs5536_stage1(); + + /* NOTE: must do this AFTER the early_setup! + * it is counting on some early MSR setup + * for cs5536 + */ + cs5536_disable_internal_uart(); + w83627hf_enable_serial(0x2e, 0x30, 0x3f8); + printk(BIOS_DEBUG, "Done %s\n", __FUNCTION__); +} Modified: LinuxBIOSv3/southbridge/amd/cs5536/cs5536.h =================================================================== --- LinuxBIOSv3/southbridge/amd/cs5536/cs5536.h 2007-06-28 23:59:40 UTC (rev 406) +++ LinuxBIOSv3/southbridge/amd/cs5536/cs5536.h 2007-06-29 00:09:24 UTC (rev 407) @@ -451,7 +451,7 @@ void cs5536_disable_internal_uart(void); void cs5536_setup_cis_mode(void); void cs5536_setup_onchipuart(void); -void cs5536_early_setup(void); +void cs5536_stage1(void); #endif /* SOUTHBRIDGE_AMD_CS5536_CS5536_H */ Deleted: LinuxBIOSv3/southbridge/amd/cs5536/cs5536_early_setup.c =================================================================== --- LinuxBIOSv3/southbridge/amd/cs5536/cs5536_early_setup.c 2007-06-28 23:59:40 UTC (rev 406) +++ LinuxBIOSv3/southbridge/amd/cs5536/cs5536_early_setup.c 2007-06-29 00:09:24 UTC (rev 407) @@ -1,299 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console.h> -#include <io.h> -#include <msr.h> -#include <amd_geodelx.h> -#include "cs5536.h" - -/* - * Early chipset initialization for the AMD CS5536 Companion Device. - * - * This code is needed for setting up RAM, since we need SMBus working as - * well as a serial port. - * - * This file implements the initialization sequence documented in section 4.2 - * of AMD Geode GX Processor CS5536 Companion Device GoedeROM Porting Guide. - */ - -/** - * Set up GLINK routing for this part. - * - * The routing is controlled by an MSR. This appears to be the same on - * all boards. - */ -void cs5536_setup_extmsr(void) -{ - struct msr msr; - - /* Forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM. */ - msr.hi = msr.lo = 0x00000000; - -#if CS5536_GLINK_PORT_NUM <= 4 - msr.lo = CS5536_DEV_NUM << - (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8); -#else - msr.hi = CS5536_DEV_NUM << - (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8); -#endif - - wrmsr(GLPCI_ExtMSR, msr); -} - -/** - * Setup PCI IDSEL for CS5536. There is a Magic Register that must be - * written so that the chip appears at the expected place in the PCI tree. - */ -void cs5536_setup_idsel(void) -{ - /* Write IDSEL to the write once register at address 0x0000. */ - outl(0x1 << (CS5536_DEV_NUM + 10), 0); -} - -/** - * Magic Bits for undocumented register. You don't need to see those papers. - * These are not the bits you're looking for. You can go about your business. - * Move along, move along. - */ -void cs5536_usb_swapsif(void) -{ - struct msr msr; - - msr = rdmsr(USB1_SB_GLD_MSR_CAP + 0x5); - - /* USB Serial short detect bit. */ - if (msr.hi & 0x10) { - /* We need to preserve bits 32,33,35 and not clear any BIST - * error, but clear the SERSHRT error bit. - */ - msr.hi &= 0xFFFFFFFB; - wrmsr(USB1_SB_GLD_MSR_CAP + 0x5, msr); - } -} - -/** - * Set up I/O bases for SMBus, GPIO, MFGPT, ACPI, and PM. - * - * These can be changed by Linux later. We set some initial value so that - * the resources are there as needed. The values are hardcoded because, - * this early in the process, fancy allocation can do more harm than good. - */ -void cs5536_setup_iobase(void) -{ - struct msr msr; - - /* Setup LBAR for SMBus controller. */ - msr.hi = 0x0000f001; - msr.lo = SMBUS_IO_BASE; - wrmsr(MDD_LBAR_SMB, msr); - - /* Setup LBAR for GPIO. */ - msr.hi = 0x0000f001; - msr.lo = GPIO_IO_BASE; - wrmsr(MDD_LBAR_GPIO, msr); - - /* Setup LBAR for MFGPT. */ - msr.hi = 0x0000f001; - msr.lo = MFGPT_IO_BASE; - wrmsr(MDD_LBAR_MFGPT, msr); - - /* Setup LBAR for ACPI. */ - msr.hi = 0x0000f001; - msr.lo = ACPI_IO_BASE; - wrmsr(MDD_LBAR_ACPI, msr); - - /* Setup LBAR for PM support. */ - msr.hi = 0x0000f001; - msr.lo = PMS_IO_BASE; - wrmsr(MDD_LBAR_PMS, msr); -} - -/** - * Power Button Setup. - * - * Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which - * controls all voltage rails except Vstandby & Vmem. We need to enable, - * OUT_AUX1 and OUTPUT_ENABLE in this order. - * - * If GPIO24 is not enabled then soft-off will not work. - */ -void cs5536_setup_power_button(void) -{ - outl(0x40020000, PMS_IO_BASE + 0x40); - outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT); - outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE); -} - -/** - * Set the various GPIOs. - * - * An unknown question at this point is how general this is to all mainboards. - * At the same time, many boards seem to follow this particular reference spec. - */ -void cs5536_setup_smbus_gpio(void) -{ - u32 val; - - /* Setup GPIO pins 14/15 for SDA/SCL. */ - val = GPIOL_15_SET | GPIOL_14_SET; - - /* Output Enable */ - outl(val, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); - - /* Output AUX1 */ - outl(val, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); - - /* Input Enable */ - outl(val, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); - - /* Input AUX1 */ - outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); -} - -/** - * Disable the internal UART. - * - * Different boards have different UARTs for COM1. - */ -void cs5536_disable_internal_uart(void) -{ - struct msr msr; - - /* The UARTs default to enabled. - * Disable and reset them and configure them later (SIO init). - */ - msr = rdmsr(MDD_UART1_CONF); - msr.lo = 1; // reset - wrmsr(MDD_UART1_CONF, msr); - msr.lo = 0; // disabled - wrmsr(MDD_UART1_CONF, msr); - - msr = rdmsr(MDD_UART2_CONF); - msr.lo = 1; // reset - wrmsr(MDD_UART2_CONF, msr); - msr.lo = 0; // disabled - wrmsr(MDD_UART2_CONF, msr); -} - -/** - * Set up the CS5536 CIS interface to CPU interface to match modes. - * - * The CIS is related to the interrupt system. It is important to match - * the southbridge and the CPU chips. At the same time, they always seem - * to use mode B. - */ -void cs5536_setup_cis_mode(void) -{ - struct msr msr; - - /* Setup CPU interface serial to mode B to match CPU. */ - msr = rdmsr(GLPCI_SB_CTRL); - msr.lo &= ~0x18; - msr.lo |= 0x10; - wrmsr(GLPCI_SB_CTRL, msr); -} - -/** - * Enable the on chip UART. - * - * See page 412 of the AMD Geode CS5536 Companion Device data book. - */ -void cs5536_setup_onchipuart(void) -{ - struct msr msr; - - /* Setup early for polling only mode. - * 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1. - * GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34 - * 2. Enable UART I/O space in MDD. - * MSR 0x51400014 bit 18:16 - * 3. Enable UART controller. - * MSR 0x5140003A bit 0, 1 - */ - - /* GPIO8 - UART1_TX */ - /* Set: Output Enable (0x4) */ - outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); - /* Set: OUTAUX1 Select (0x10) */ - outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); - - /* GPIO9 - UART1_RX */ - /* Set: Input Enable (0x20) */ - outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); - /* Set: INAUX1 Select (0x34) */ - outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); - - /* Set address to 0x3F8. */ - msr = rdmsr(MDD_LEG_IO); - msr.lo |= 0x7 << 16; - wrmsr(MDD_LEG_IO, msr); - - /* Bit 1 = DEVEN (device enable) - * Bit 4 = EN_BANKS (allow access to the upper banks) - */ - msr.lo = (1 << 4) | (1 << 1); - msr.hi = 0; - - /* Enable COM1. */ - wrmsr(MDD_UART1_CONF, msr); -} - -/** - * Board setup. - * - * Known to work on the AMD Norwich and DIGITIAL-LOGIC boards. - * - * The extmsr and cis_mode are common for sure. The RSTPLL check is mandatory. - * IDSEL of course is required, so the chip appears in PCI config space, - * and the swapsif covers a necessary chip fix. - * - * Finally, the iobase is needed for DRAM, the GPIOs are likely common to all - * boards, and the power button seems to be the same on all. At the same time, - * we may need to move GPIO and power button out as developments demand. - * - * Note we do NOT do any UART setup here -- this is done later by the - * mainboard setup, since UART usage is not universal. - * - * See also a comment from Marc Jones: - * http://www.linuxbios.org/pipermail/linuxbios/2007-June/021958.html - */ -void cs5536_early_setup(void) -{ - struct msr msr; - - /* Note: you can't do prints in here in most cases, and we don't want - * to hang on serial, so they are commented out. - */ - cs5536_setup_extmsr(); - cs5536_setup_cis_mode(); - - msr = rdmsr(GLCP_SYS_RSTPLL); - if (msr.lo & (0x3f << 26)) { - /* PLL is already set and we are reboot from PLL reset. */ - return; - } - - cs5536_setup_idsel(); - cs5536_usb_swapsif(); - cs5536_setup_iobase(); - cs5536_setup_smbus_gpio(); - /* cs5536_enable_smbus(); -- Leave this out for now. */ - cs5536_setup_power_button(); -} Copied: LinuxBIOSv3/southbridge/amd/cs5536/stage1.c (from rev 405, LinuxBIOSv3/southbridge/amd/cs5536/cs5536_early_setup.c) =================================================================== --- LinuxBIOSv3/southbridge/amd/cs5536/stage1.c (rev 0) +++ LinuxBIOSv3/southbridge/amd/cs5536/stage1.c 2007-06-29 00:09:24 UTC (rev 407) @@ -0,0 +1,299 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console.h> +#include <io.h> +#include <msr.h> +#include <amd_geodelx.h> +#include "cs5536.h" + +/* + * Early chipset initialization for the AMD CS5536 Companion Device. + * + * This code is needed for setting up RAM, since we need SMBus working as + * well as a serial port. + * + * This file implements the initialization sequence documented in section 4.2 + * of AMD Geode GX Processor CS5536 Companion Device GoedeROM Porting Guide. + */ + +/** + * Set up GLINK routing for this part. + * + * The routing is controlled by an MSR. This appears to be the same on + * all boards. + */ +void cs5536_setup_extmsr(void) +{ + struct msr msr; + + /* Forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM. */ + msr.hi = msr.lo = 0x00000000; + +#if CS5536_GLINK_PORT_NUM <= 4 + msr.lo = CS5536_DEV_NUM << + (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8); +#else + msr.hi = CS5536_DEV_NUM << + (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8); +#endif + + wrmsr(GLPCI_ExtMSR, msr); +} + +/** + * Setup PCI IDSEL for CS5536. There is a Magic Register that must be + * written so that the chip appears at the expected place in the PCI tree. + */ +void cs5536_setup_idsel(void) +{ + /* Write IDSEL to the write once register at address 0x0000. */ + outl(0x1 << (CS5536_DEV_NUM + 10), 0); +} + +/** + * Magic Bits for undocumented register. You don't need to see those papers. + * These are not the bits you're looking for. You can go about your business. + * Move along, move along. + */ +void cs5536_usb_swapsif(void) +{ + struct msr msr; + + msr = rdmsr(USB1_SB_GLD_MSR_CAP + 0x5); + + /* USB Serial short detect bit. */ + if (msr.hi & 0x10) { + /* We need to preserve bits 32,33,35 and not clear any BIST + * error, but clear the SERSHRT error bit. + */ + msr.hi &= 0xFFFFFFFB; + wrmsr(USB1_SB_GLD_MSR_CAP + 0x5, msr); + } +} + +/** + * Set up I/O bases for SMBus, GPIO, MFGPT, ACPI, and PM. + * + * These can be changed by Linux later. We set some initial value so that + * the resources are there as needed. The values are hardcoded because, + * this early in the process, fancy allocation can do more harm than good. + */ +void cs5536_setup_iobase(void) +{ + struct msr msr; + + /* Setup LBAR for SMBus controller. */ + msr.hi = 0x0000f001; + msr.lo = SMBUS_IO_BASE; + wrmsr(MDD_LBAR_SMB, msr); + + /* Setup LBAR for GPIO. */ + msr.hi = 0x0000f001; + msr.lo = GPIO_IO_BASE; + wrmsr(MDD_LBAR_GPIO, msr); + + /* Setup LBAR for MFGPT. */ + msr.hi = 0x0000f001; + msr.lo = MFGPT_IO_BASE; + wrmsr(MDD_LBAR_MFGPT, msr); + + /* Setup LBAR for ACPI. */ + msr.hi = 0x0000f001; + msr.lo = ACPI_IO_BASE; + wrmsr(MDD_LBAR_ACPI, msr); + + /* Setup LBAR for PM support. */ + msr.hi = 0x0000f001; + msr.lo = PMS_IO_BASE; + wrmsr(MDD_LBAR_PMS, msr); +} + +/** + * Power Button Setup. + * + * Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which + * controls all voltage rails except Vstandby & Vmem. We need to enable, + * OUT_AUX1 and OUTPUT_ENABLE in this order. + * + * If GPIO24 is not enabled then soft-off will not work. + */ +void cs5536_setup_power_button(void) +{ + outl(0x40020000, PMS_IO_BASE + 0x40); + outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT); + outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE); +} + +/** + * Set the various GPIOs. + * + * An unknown question at this point is how general this is to all mainboards. + * At the same time, many boards seem to follow this particular reference spec. + */ +void cs5536_setup_smbus_gpio(void) +{ + u32 val; + + /* Setup GPIO pins 14/15 for SDA/SCL. */ + val = GPIOL_15_SET | GPIOL_14_SET; + + /* Output Enable */ + outl(val, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); + + /* Output AUX1 */ + outl(val, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); + + /* Input Enable */ + outl(val, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); + + /* Input AUX1 */ + outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); +} + +/** + * Disable the internal UART. + * + * Different boards have different UARTs for COM1. + */ +void cs5536_disable_internal_uart(void) +{ + struct msr msr; + + /* The UARTs default to enabled. + * Disable and reset them and configure them later (SIO init). + */ + msr = rdmsr(MDD_UART1_CONF); + msr.lo = 1; // reset + wrmsr(MDD_UART1_CONF, msr); + msr.lo = 0; // disabled + wrmsr(MDD_UART1_CONF, msr); + + msr = rdmsr(MDD_UART2_CONF); + msr.lo = 1; // reset + wrmsr(MDD_UART2_CONF, msr); + msr.lo = 0; // disabled + wrmsr(MDD_UART2_CONF, msr); +} + +/** + * Set up the CS5536 CIS interface to CPU interface to match modes. + * + * The CIS is related to the interrupt system. It is important to match + * the southbridge and the CPU chips. At the same time, they always seem + * to use mode B. + */ +void cs5536_setup_cis_mode(void) +{ + struct msr msr; + + /* Setup CPU interface serial to mode B to match CPU. */ + msr = rdmsr(GLPCI_SB_CTRL); + msr.lo &= ~0x18; + msr.lo |= 0x10; + wrmsr(GLPCI_SB_CTRL, msr); +} + +/** + * Enable the on chip UART. + * + * See page 412 of the AMD Geode CS5536 Companion Device data book. + */ +void cs5536_setup_onchipuart(void) +{ + struct msr msr; + + /* Setup early for polling only mode. + * 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1. + * GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34 + * 2. Enable UART I/O space in MDD. + * MSR 0x51400014 bit 18:16 + * 3. Enable UART controller. + * MSR 0x5140003A bit 0, 1 + */ + + /* GPIO8 - UART1_TX */ + /* Set: Output Enable (0x4) */ + outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); + /* Set: OUTAUX1 Select (0x10) */ + outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); + + /* GPIO9 - UART1_RX */ + /* Set: Input Enable (0x20) */ + outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); + /* Set: INAUX1 Select (0x34) */ + outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); + + /* Set address to 0x3F8. */ + msr = rdmsr(MDD_LEG_IO); + msr.lo |= 0x7 << 16; + wrmsr(MDD_LEG_IO, msr); + + /* Bit 1 = DEVEN (device enable) + * Bit 4 = EN_BANKS (allow access to the upper banks) + */ + msr.lo = (1 << 4) | (1 << 1); + msr.hi = 0; + + /* Enable COM1. */ + wrmsr(MDD_UART1_CONF, msr); +} + +/** + * Board setup. + * + * Known to work on the AMD Norwich and DIGITIAL-LOGIC boards. + * + * The extmsr and cis_mode are common for sure. The RSTPLL check is mandatory. + * IDSEL of course is required, so the chip appears in PCI config space, + * and the swapsif covers a necessary chip fix. + * + * Finally, the iobase is needed for DRAM, the GPIOs are likely common to all + * boards, and the power button seems to be the same on all. At the same time, + * we may need to move GPIO and power button out as developments demand. + * + * Note we do NOT do any UART setup here -- this is done later by the + * mainboard setup, since UART usage is not universal. + * + * See also a comment from Marc Jones: + * http://www.linuxbios.org/pipermail/linuxbios/2007-June/021958.html + */ +void cs5536_stage1(void) +{ + struct msr msr; + + /* Note: you can't do prints in here in most cases, and we don't want + * to hang on serial, so they are commented out. + */ + cs5536_setup_extmsr(); + cs5536_setup_cis_mode(); + + msr = rdmsr(GLCP_SYS_RSTPLL); + if (msr.lo & (0x3f << 26)) { + /* PLL is already set and we are reboot from PLL reset. */ + return; + } + + cs5536_setup_idsel(); + cs5536_usb_swapsif(); + cs5536_setup_iobase(); + cs5536_setup_smbus_gpio(); + /* cs5536_enable_smbus(); -- Leave this out for now. */ + cs5536_setup_power_button(); +} Copied: LinuxBIOSv3/superio/winbond/w83627hf/stage1.c (from rev 405, LinuxBIOSv3/superio/winbond/w83627hf/w83627hf_early_serial.c) =================================================================== --- LinuxBIOSv3/superio/winbond/w83627hf/stage1.c (rev 0) +++ LinuxBIOSv3/superio/winbond/w83627hf/stage1.c 2007-06-29 00:09:24 UTC (rev 407) @@ -0,0 +1,33 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright 2007 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <io.h> +#include <device/pnp.h> +#include "w83627hf.h" + +void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase) +{ + rawpnp_enter_ext_func_mode(dev); + rawpnp_set_logical_device(dev,serial); + rawpnp_set_enable(dev, 0); + rawpnp_set_iobase(dev, PNP_IDX_IO0, iobase); + rawpnp_set_enable(dev, 1); + rawpnp_exit_ext_func_mode(dev); +} Deleted: LinuxBIOSv3/superio/winbond/w83627hf/w83627hf_early_serial.c =================================================================== --- LinuxBIOSv3/superio/winbond/w83627hf/w83627hf_early_serial.c 2007-06-28 23:59:40 UTC (rev 406) +++ LinuxBIOSv3/superio/winbond/w83627hf/w83627hf_early_serial.c 2007-06-29 00:09:24 UTC (rev 407) @@ -1,33 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright 2007 Ronald G. Minnich <rminnich(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <io.h> -#include <device/pnp.h> -#include "w83627hf.h" - -void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase) -{ - rawpnp_enter_ext_func_mode(dev); - rawpnp_set_logical_device(dev,serial); - rawpnp_set_enable(dev, 0); - rawpnp_set_iobase(dev, PNP_IDX_IO0, iobase); - rawpnp_set_enable(dev, 1); - rawpnp_exit_ext_func_mode(dev); -}

1 0

[LinuxBIOS] r406 - in LinuxBIOSv3: arch/x86 arch/x86/geodelx mainboard/adl/msm800sev
by svn＠openbios.org 29 Jun '07

29 Jun '07

Author: rminnich Date: 2007-06-29 01:59:40 +0200 (Fri, 29 Jun 2007) New Revision: 406 Added: LinuxBIOSv3/arch/x86/geodelx/early_init.c LinuxBIOSv3/mainboard/adl/msm800sev/early_init.c Modified: LinuxBIOSv3/arch/x86/Makefile LinuxBIOSv3/arch/x86/cachemain.c LinuxBIOSv3/arch/x86/geodelx/geodelx.c LinuxBIOSv3/mainboard/adl/msm800sev/Makefile LinuxBIOSv3/mainboard/adl/msm800sev/initram.c Log: These are changes we are making so that serial startup can be done in stage 1. This is part of a general change in startup due to the move from V2 to V3. The LX is complex and in this case much work must be done, we don't expect all platforms to be this way. We will probably be changined these names from eary_* to stage1.c to make it easier for people to know what's going on. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: LinuxBIOSv3/arch/x86/Makefile =================================================================== --- LinuxBIOSv3/arch/x86/Makefile 2007-06-28 20:09:41 UTC (rev 405) +++ LinuxBIOSv3/arch/x86/Makefile 2007-06-28 23:59:40 UTC (rev 406) @@ -92,7 +92,8 @@ STAGE0_OBJ := $(patsubst %,$(obj)/lib/%,$(STAGE0_LIB_OBJ)) \ $(patsubst %,$(obj)/arch/x86/%,$(STAGE0_ARCH_X86_OBJ)) \ - $(patsubst %,$(obj)/arch/x86/%,$(STAGE0_CAR_OBJ)) + $(patsubst %,$(obj)/arch/x86/%,$(STAGE0_CAR_OBJ)) \ + $(STAGE0_MAINBOARD_OBJ) $(obj)/stage0.init: $(STAGE0_OBJ) $(Q)# We need to be careful. If stage0.o gets bigger than Modified: LinuxBIOSv3/arch/x86/cachemain.c =================================================================== --- LinuxBIOSv3/arch/x86/cachemain.c 2007-06-28 20:09:41 UTC (rev 405) +++ LinuxBIOSv3/arch/x86/cachemain.c 2007-06-28 23:59:40 UTC (rev 406) @@ -27,9 +27,9 @@ /* these prototypes should go into headers */ void uart_init(void); -void console_init(void); void die(const char *msg); int find_file(struct mem_file *archive, char *filename, struct mem_file *result); +void early_init(void); // Is this value correct? #define DCACHE_RAM_SIZE 0x8000 @@ -46,14 +46,6 @@ post_code(0xf0); } -static void enable_superio(void) -{ - // nothing yet - beep_short(); // FIXME - post_code(0xf1); - beep_long(); // FIXME -} - static void enable_rom(void) { // nothing here yet @@ -90,7 +82,7 @@ // We have cache as ram running and can start executing code in C. // - enable_superio(); + early_init(); // uart_init(); // initialize serial port Added: LinuxBIOSv3/arch/x86/geodelx/early_init.c =================================================================== --- LinuxBIOSv3/arch/x86/geodelx/early_init.c (rev 0) +++ LinuxBIOSv3/arch/x86/geodelx/early_init.c 2007-06-28 23:59:40 UTC (rev 406) @@ -0,0 +1,71 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa(a)artecdesign.ee> + * Copyright (C) 2006 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd_geodelx.h> +#include <spd.h> + +/** + * geodelx_msr_init Set up Geode LX registers for sane behaviour. Set + * all low memory (under 1MB) to write back. Do some setup for cache + * as ram as well. + */ +void geodelx_msr_init(void) +{ + struct msr msr; + /* Setup access to the cache for under 1MB. */ + msr.hi = 0x24fffc02; + msr.lo = 0x1000A000; /* 0-A0000 write back */ + wrmsr(CPU_RCONF_DEFAULT, msr); + + msr.hi = 0x0; /* write back */ + msr.lo = 0x0; + wrmsr(CPU_RCONF_A0_BF, msr); + wrmsr(CPU_RCONF_C0_DF, msr); + wrmsr(CPU_RCONF_E0_FF, msr); + + /* Setup access to the cache for under 640K. Note MC not setup yet. */ + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU0 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU0 + 0x21, msr); + + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU1 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU1 + 0x21, msr); + +} + Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c =================================================================== --- LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2007-06-28 20:09:41 UTC (rev 405) +++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2007-06-28 23:59:40 UTC (rev 406) @@ -39,45 +39,6 @@ * and it sucks. */ -/** - * geodelx_msr_init Set up Geode LX registers for sane behaviour. Set - * all low memory (under 1MB) to write back. Do some setup for cache - * as ram as well. - */ -void geodelx_msr_init(void) -{ - struct msr msr; - /* Setup access to the cache for under 1MB. */ - msr.hi = 0x24fffc02; - msr.lo = 0x1000A000; /* 0-A0000 write back */ - wrmsr(CPU_RCONF_DEFAULT, msr); - - msr.hi = 0x0; /* write back */ - msr.lo = 0x0; - wrmsr(CPU_RCONF_A0_BF, msr); - wrmsr(CPU_RCONF_C0_DF, msr); - wrmsr(CPU_RCONF_E0_FF, msr); - - /* Setup access to the cache for under 640K. Note MC not setup yet. */ - msr.hi = 0x20000000; - msr.lo = 0xfff80; - wrmsr(MSR_GLIU0 + 0x20, msr); - - msr.hi = 0x20000000; - msr.lo = 0x80fffe0; - wrmsr(MSR_GLIU0 + 0x21, msr); - - msr.hi = 0x20000000; - msr.lo = 0xfff80; - wrmsr(MSR_GLIU1 + 0x20, msr); - - msr.hi = 0x20000000; - msr.lo = 0x80fffe0; - wrmsr(MSR_GLIU1 + 0x21, msr); - -} - - /** * start_time1 Starts Timer 1 for port 61 use. FIXME try to figure * out what these values mean. @@ -97,6 +58,7 @@ start_timer1(); } + /* cpu bug management */ /** * Modified: LinuxBIOSv3/mainboard/adl/msm800sev/Makefile =================================================================== --- LinuxBIOSv3/mainboard/adl/msm800sev/Makefile 2007-06-28 20:09:41 UTC (rev 405) +++ LinuxBIOSv3/mainboard/adl/msm800sev/Makefile 2007-06-28 23:59:40 UTC (rev 406) @@ -19,6 +19,12 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +STAGE0_MAINBOARD_OBJ := $(obj)/superio/winbond/w83627hf/w83627hf_early_serial.o \ + $(obj)/device/pnp_raw.o \ + $(obj)/southbridge/amd/cs5536/cs5536_early_setup.o\ + $(obj)/arch/x86/geodelx/early_init.o \ + $(obj)/mainboard/$(MAINBOARDDIR)/early_init.o + $(obj)/linuxbios.vpd: $(Q)printf " BUILD DUMMY VPD\n" $(Q)dd if=/dev/zero of=$(obj)/linuxbios.vpd bs=256 count=1 $(SILENT) @@ -26,9 +32,6 @@ INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ $(obj)/northbridge/amd/geodelx/raminit.o \ $(obj)/southbridge/amd/cs5536/smbus_initram.o \ - $(obj)/southbridge/amd/cs5536/cs5536_early_setup.o\ - $(obj)/superio/winbond/w83627hf/w83627hf_early_serial.o\ - $(obj)/device/pnp_raw.o \ $(obj)/arch/x86/geodelx/geodelx.o $(obj)/linuxbios.initram: $(obj)/stage0.init $(obj)/stage0.o $(INITRAM_OBJ) Added: LinuxBIOSv3/mainboard/adl/msm800sev/early_init.c =================================================================== --- LinuxBIOSv3/mainboard/adl/msm800sev/early_init.c (rev 0) +++ LinuxBIOSv3/mainboard/adl/msm800sev/early_init.c 2007-06-28 23:59:40 UTC (rev 406) @@ -0,0 +1,54 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <post_code.h> +#include <device/device.h> +#include <device/pci.h> +#include <io.h> +#include <device/pnp.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd_geodelx.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <superio/winbond/w83627hf/w83627hf.h> + +#define SERIAL_DEV 0x30 + +int early_init(void) +{ + void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase); + post_code(POST_START_OF_MAIN); + + geodelx_msr_init(); + + cs5536_early_setup(); + + /* NOTE: must do this AFTER the early_setup! + * it is counting on some early MSR setup + * for cs5536 + */ + cs5536_disable_internal_uart(); + w83627hf_enable_serial(0x2e, 0x30, 0x3f8); + printk(BIOS_DEBUG, "Done %s\n", __FUNCTION__); +} Modified: LinuxBIOSv3/mainboard/adl/msm800sev/initram.c =================================================================== --- LinuxBIOSv3/mainboard/adl/msm800sev/initram.c 2007-06-28 20:09:41 UTC (rev 405) +++ LinuxBIOSv3/mainboard/adl/msm800sev/initram.c 2007-06-28 23:59:40 UTC (rev 406) @@ -32,10 +32,7 @@ #include <amd_geodelx.h> #include <southbridge/amd/cs5536/cs5536.h> #include <northbridge/amd/geodelx/raminit.h> -#include <superio/winbond/w83627hf/w83627hf.h> -#define SERIAL_DEV 0x30 - #define MANUALCONF 0 /* Do automatic strapped PLL config */ #define PLLMSRHI 0x00001490 /* manual settings for the PLL */ #define PLLMSRLO 0x02000030 @@ -45,22 +42,9 @@ int main(void) { void done_cache_as_ram_main(void); - void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase); post_code(POST_START_OF_MAIN); - system_preinit(); - geodelx_msr_init(); - cs5536_early_setup(); - - /* NOTE: must do this AFTER the early_setup! - * it is counting on some early MSR setup - * for cs5536 - */ - cs5536_disable_internal_uart(); - w83627hf_enable_serial(0x2e, 0x30, 0x3f8); - console_init(); - pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO); cpu_reg_init(0, DIMM0, DIMM1);

1 0

Re: [LinuxBIOS] r401 - in LinuxBIOSv3/northbridge: amd/geodelx intel/i440bxemulation
by Uwe Hermann 29 Jun '07

29 Jun '07

On Thu, Jun 28, 2007 at 07:12:37PM +0200, svn(a)openbios.org wrote: > +#include <types.h> > +#include <lib.h> > +#include <console.h> > +#include <post_code.h> > +#include <device/device.h> > +#include <device/pci.h> > +#include <string.h> > +#include <msr.h> > +#include <io.h> > +#include <cpu.h> > +#include <amd_geodelx.h> The list of includes we need in every file is getting pretty large slowly... Should we introduce a linuxbios.h file which includes all "core" headers such as types.h, string.h, io.h and others? This would reduce the number of includes a lot. (we should not put chipset- or mainboard-specific includes in linuxbios.h, of course) > + > +struct gliutable { > + unsigned long desc_name; > + unsigned short desc_type; > + unsigned long hi, lo; Should be u8, u16, u32 etc. as needed. > +struct msrinit { > + unsigned long msrnum; u8, u16 etc. > +extern int sizeram(void); [...] > +extern int sizeram(void); Listed twice, one must go (or rather both of them?) This should be in some header file. > +/** > + * Set the GLPCI registers for the memory hole. > + * Keeps all cache shadow descriptors sync'ed. > + * @param shadowhi the high 32 bits of the msr setting > + * @param shadowlo The low 32 bits of the msr setting > + */ > +static void set_shadowGLPCI(u32 shadowhi, u32 shadowlo) One of the many mixed-case function-/variable-names which need to be fixed. > + // Make sure all INVD instructions are treated as WBINVD. We do this > + // because we've found some programs which require this behavior. > + msr = rdmsr(CPU_DM_CONFIG0); > + msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET; > + wrmsr(CPU_DM_CONFIG0, msr); > + > + enable_cache(); > + __asm__("wbinvd\n"); We have a wbinvd() function in cpu.h now. > + __asm__ __volatile__("FINIT\n"); Should be a function in some header? Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

3 3

Re: [LinuxBIOS] r394 - in LinuxBIOSv3: mainboard mainboard/adl/msm800sev mainboard/amd/norwich mainboard/artecgroup mainboard/artecgroup/dbe61 mainboard/emulation/qemu-x86 util/dtc
by Marc Jones 29 Jun '07

29 Jun '07

Ron, A general comment about the dbe61. This doesn't look like it came from the code I checked in last week. You should look at the fake spd code in the dbe61 as well. I think it is the better way to do it since customers will have memory specs that look like SPD values. It is not easy to translate to Geode MC settings. Marc svn(a)openbios.org wrote: >Author: rminnich >Date: 2007-06-28 18:21:38 +0200 (Thu, 28 Jun 2007) >New Revision: 394 > >Added: > LinuxBIOSv3/mainboard/artecgroup/ > LinuxBIOSv3/mainboard/artecgroup/Kconfig > LinuxBIOSv3/mainboard/artecgroup/dbe61/ > LinuxBIOSv3/mainboard/artecgroup/dbe61/Kconfig > LinuxBIOSv3/mainboard/artecgroup/dbe61/Makefile > LinuxBIOSv3/mainboard/artecgroup/dbe61/cmos.layout > LinuxBIOSv3/mainboard/artecgroup/dbe61/dts > LinuxBIOSv3/mainboard/artecgroup/dbe61/initram.c > LinuxBIOSv3/mainboard/artecgroup/dbe61/irq_tables.c >Removed: > LinuxBIOSv3/mainboard/adl/msm800sev/mainboard.c > LinuxBIOSv3/mainboard/amd/norwich/mainboard.c > LinuxBIOSv3/mainboard/emulation/qemu-x86/mainboard.c >Modified: > LinuxBIOSv3/mainboard/Kconfig > LinuxBIOSv3/mainboard/adl/msm800sev/dts > LinuxBIOSv3/mainboard/amd/norwich/dts > LinuxBIOSv3/mainboard/emulation/qemu-x86/dts > LinuxBIOSv3/util/dtc/flattree.c >Log: >Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com >Acked-by: Stefan Reinauer <stepan(a)coresystems.de > >This patch adds artec dbe61 support, removes all mainboard.c, and > adds > the code to dtc so that it takes these properties from the top level > dts: > /{ > . > . > . > > mainboard-vendor = "AMD"; > mainboard-part-number = "Norwich"; > } > > statictree.h will have: > extern const char *mainboard_vendor, *mainboard_part_number; > > and statictree.c will have: > const char *mainboard_vendor = "AMD"; > const char *mainboard_part_number = "Norwich"; > > It is an error to NOT have the vendor and part number in the top > level dts. > > thanks > > ron > >Get rid of mainboard.c in all mainboard directories. >Modify dtc so that it creates declarations (in statictree.h) and >generates the char * >for mainboard name and part # (in statictree.c). > >Failure to set up a mainboard-vendor >OR mainboard-part-number property in the mainboard dts will get a >helpful and descriptive error message (tested). >This may be a first for the linuxbios config >tools. > >Add Georgi's patch for the bug in flattree.c; assign *cp = 0. > > > > >Modified: LinuxBIOSv3/mainboard/Kconfig >=================================================================== >--- LinuxBIOSv3/mainboard/Kconfig 2007-06-28 15:19:30 UTC (rev 393) >+++ LinuxBIOSv3/mainboard/Kconfig 2007-06-28 16:21:38 UTC (rev 394) >@@ -38,6 +38,12 @@ > Select this option for various systems from > Advanced Micro Devices, Inc > >+config VENDOR_ARTECGROUP >+ bool "Artec Group" >+ help >+ Select this option for various systems from >+ the Artec Group >+ > config VENDOR_EMULATION > bool "Emulated systems" > help >@@ -48,6 +54,7 @@ > source "mainboard/emulation/Kconfig" > source "mainboard/adl/Kconfig" > source "mainboard/amd/Kconfig" >+source "mainboard/artecgroup/Kconfig" > > choice > prompt "ROM chip size" > >Modified: LinuxBIOSv3/mainboard/adl/msm800sev/dts >=================================================================== >--- LinuxBIOSv3/mainboard/adl/msm800sev/dts 2007-06-28 15:19:30 UTC (rev 393) >+++ LinuxBIOSv3/mainboard/adl/msm800sev/dts 2007-06-28 16:21:38 UTC (rev 394) >@@ -22,6 +22,8 @@ > > /{ > >+ mainboard-vendor = "Advanced Digital Logic"; >+ mainboard-part-number = "MSM800SEV"; > cpus { > enabled; > }; > >Deleted: LinuxBIOSv3/mainboard/adl/msm800sev/mainboard.c >=================================================================== >--- LinuxBIOSv3/mainboard/adl/msm800sev/mainboard.c 2007-06-28 15:19:30 UTC (rev 393) >+++ LinuxBIOSv3/mainboard/adl/msm800sev/mainboard.c 2007-06-28 16:21:38 UTC (rev 394) >@@ -1,24 +0,0 @@ >-/* >- * This file is part of the LinuxBIOS project. >- * >- * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> >- * Copyright (C) 2007 coresystems GmbH >- * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) >- * >- * This program is free software; you can redistribute it and/or modify >- * it under the terms of the GNU General Public License as published by >- * the Free Software Foundation; either version 2 of the License, or >- * (at your option) any later version. >- * >- * This program is distributed in the hope that it will be useful, >- * but WITHOUT ANY WARRANTY; without even the implied warranty of >- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >- * GNU General Public License for more details. >- * >- * You should have received a copy of the GNU General Public License >- * along with this program; if not, write to the Free Software >- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA >- */ >- >-const char *mainboard_vendor = "Advanced Digital Logic"; >-const char *mainboard_part_number = "MSM800SEV"; > >Modified: LinuxBIOSv3/mainboard/amd/norwich/dts >=================================================================== >--- LinuxBIOSv3/mainboard/amd/norwich/dts 2007-06-28 15:19:30 UTC (rev 393) >+++ LinuxBIOSv3/mainboard/amd/norwich/dts 2007-06-28 16:21:38 UTC (rev 394) >@@ -19,7 +19,8 @@ > */ > /{ > enabled; >- >+ mainboard-vendor = "AMD"; >+ mainboard-part-number = "Norwich"; > cpus { > enabled; > }; > >Deleted: LinuxBIOSv3/mainboard/amd/norwich/mainboard.c >=================================================================== >--- LinuxBIOSv3/mainboard/amd/norwich/mainboard.c 2007-06-28 15:19:30 UTC (rev 393) >+++ LinuxBIOSv3/mainboard/amd/norwich/mainboard.c 2007-06-28 16:21:38 UTC (rev 394) >@@ -1,24 +0,0 @@ >-/* >- * This file is part of the LinuxBIOS project. >- * >- * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> >- * Copyright (C) 2007 coresystems GmbH >- * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) >- * >- * This program is free software; you can redistribute it and/or modify >- * it under the terms of the GNU General Public License as published by >- * the Free Software Foundation; either version 2 of the License, or >- * (at your option) any later version. >- * >- * This program is distributed in the hope that it will be useful, >- * but WITHOUT ANY WARRANTY; without even the implied warranty of >- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >- * GNU General Public License for more details. >- * >- * You should have received a copy of the GNU General Public License >- * along with this program; if not, write to the Free Software >- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA >- */ >- >-const char *mainboard_vendor = "AMD"; >-const char *mainboard_part_number = "Norwich"; > >Added: LinuxBIOSv3/mainboard/artecgroup/Kconfig >=================================================================== >--- LinuxBIOSv3/mainboard/artecgroup/Kconfig (rev 0) >+++ LinuxBIOSv3/mainboard/artecgroup/Kconfig 2007-06-28 16:21:38 UTC (rev 394) >@@ -0,0 +1,38 @@ >+## >+## This file is part of the LinuxBIOS project. >+## >+## Copyright (C) 2007 coresystems GmbH >+## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) >+## >+## This program is free software; you can redistribute it and/or modify >+## it under the terms of the GNU General Public License as published by >+## the Free Software Foundation; either version 2 of the License, or >+## (at your option) any later version. >+## >+## This program is distributed in the hope that it will be useful, >+## but WITHOUT ANY WARRANTY; without even the implied warranty of >+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >+## GNU General Public License for more details. >+## >+## You should have received a copy of the GNU General Public License >+## along with this program; if not, write to the Free Software >+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA >+## >+ >+choice >+ prompt "Mainboard model" >+ depends on VENDOR_ARTECGROUP >+ >+config BOARD_ARTECGROUP_DBE61 >+ bool "dbe61" >+ select ARCH_X86 >+ select CPU_AMD_GEODELX >+ select OPTION_TABLE >+ select NORTHBRIDGE_AMD_GEODELX >+ select SOUTHBRIDGE_AMD_CS5536 >+ help >+ Artec Group DBE61, also known as Linutop >+endchoice >+ >+source "mainboard/artecgroup/dbe61/Kconfig" >+ > >Added: LinuxBIOSv3/mainboard/artecgroup/dbe61/Kconfig >=================================================================== >--- LinuxBIOSv3/mainboard/artecgroup/dbe61/Kconfig (rev 0) >+++ LinuxBIOSv3/mainboard/artecgroup/dbe61/Kconfig 2007-06-28 16:21:38 UTC (rev 394) >@@ -0,0 +1,45 @@ >+## >+## This file is part of the LinuxBIOS project. >+## >+## Copyright (C) 2007 coresystems GmbH >+## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) >+## >+## This program is free software; you can redistribute it and/or modify >+## it under the terms of the GNU General Public License as published by >+## the Free Software Foundation; either version 2 of the License, or >+## (at your option) any later version. >+## >+## This program is distributed in the hope that it will be useful, >+## but WITHOUT ANY WARRANTY; without even the implied warranty of >+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >+## GNU General Public License for more details. >+## >+## You should have received a copy of the GNU General Public License >+## along with this program; if not, write to the Free Software >+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA >+## >+ >+config MAINBOARD_NAME >+ string >+ default artecgroup/dbe61 >+ depends BOARD_ARTECGROUP_DBE61 >+ help >+ This is the default mainboard name. >+ >+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID >+ hex >+ default 0x1022 >+ depends BOARD_ARTECGROUP_DBE61 >+ help >+ Mainboard specific PCI subsystem vendor ID. >+ >+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID >+ hex >+ default 0x2323 >+ depends BOARD_ARTECGROUP_DBE61 >+ help >+ Mainboard specific PCI subsystem device ID. >+ >+ >+ >+ > >Added: LinuxBIOSv3/mainboard/artecgroup/dbe61/Makefile >=================================================================== >--- LinuxBIOSv3/mainboard/artecgroup/dbe61/Makefile (rev 0) >+++ LinuxBIOSv3/mainboard/artecgroup/dbe61/Makefile 2007-06-28 16:21:38 UTC (rev 394) >@@ -0,0 +1,76 @@ >+## >+## This file is part of the LinuxBIOS project. >+## >+## Copyright (C) 2006-2007 coresystems GmbH >+## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) >+## >+## This program is free software; you can redistribute it and/or modify >+## it under the terms of the GNU General Public License as published by >+## the Free Software Foundation; either version 2 of the License, or >+## (at your option) any later version. >+## >+## This program is distributed in the hope that it will be useful, >+## but WITHOUT ANY WARRANTY; without even the implied warranty of >+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >+## GNU General Public License for more details. >+## >+## You should have received a copy of the GNU General Public License >+## along with this program; if not, write to the Free Software >+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA >+## >+ >+$(obj)/linuxbios.vpd: >+ $(Q)printf " BUILD DUMMY VPD\n" >+ $(Q)dd if=/dev/zero of=$(obj)/linuxbios.vpd bs=256 count=1 $(SILENT) >+ >+INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ >+ $(obj)/southbridge/amd/cs5536/cs5536_early_setup.o\ >+ $(obj)/arch/x86/geodelx/geodelx.o >+ >+$(obj)/linuxbios.initram: $(obj)/stage0.init $(obj)/stage0.o $(INITRAM_OBJ) >+ $(Q)# initram links against stage0 >+ $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" >+ $(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x80000 $(INITRAM_OBJ) \ >+ --entry=main -o $(obj)/linuxbios.initram.o >+ $(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@))\n" >+ $(Q)$(OBJCOPY) -O binary $(obj)/linuxbios.initram.o \ >+ $(obj)/linuxbios.initram >+ >+# >+# Miscellaneous important targets. >+# >+ >+$(obj)/mainboard/$(MAINBOARDDIR)/mainboard.o: $(obj)/mainboard/$(MAINBOARDDIR)/statictree.o >+ >+$(obj)/mainboard/$(MAINBOARDDIR)/statictree.o: $(obj)/mainboard/$(MAINBOARDDIR)/statictree.c $(obj)/statictree.h >+ $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" >+ $(Q)$(CC) $(INITCFLAGS) $(LINUXBIOSINCLUDE) -c -o $@ $< >+ >+$(obj)/mainboard/$(MAINBOARDDIR)/statictree.c: $(src)/mainboard/$(MAINBOARDDIR)/dts $(obj)/util/dtc/dtc >+ $(Q)printf " DTC $(subst $(shell pwd)/,,$(@))\n" >+ $(Q)$(obj)/util/dtc/dtc -O lb mainboard/$(MAINBOARDDIR)/dts > $@ >+ >+$(obj)/statictree.h: $(src)/mainboard/$(MAINBOARDDIR)/dts $(obj)/util/dtc/dtc >+ $(Q)printf " DTC $(subst $(shell pwd)/,,$(@))\n" >+ $(Q)$(obj)/util/dtc/dtc -O lbh mainboard/$(MAINBOARDDIR)/dts > $@ >+ >+$(obj)/mainboard/$(MAINBOARDDIR)/option_table.c: $(obj)/util/options/build_opt_tbl $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout >+ $(Q)printf " OPTIONS $(subst $(shell pwd)/,,$(@))\n" >+ $(Q)mkdir -p $(obj)/mainboard/$(MAINBOARDDIR) >+ $(Q)$(obj)/util/options/build_opt_tbl -b \ >+ --config $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout \ >+ --option $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c >+ >+$(obj)/option_table: $(obj)/mainboard/$(MAINBOARDDIR)/option_table.o >+ $(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@))\n" >+ $(Q)$(OBJCOPY) -O binary $< $@ >+ >+STAGE2_MAINBOARD_OBJ = mainboard.o >+ >+STAGE2_CHIPSET_OBJ = $(obj)/arch/x86/geodelx/cpu.o >+ >+$(obj)/mainboard/$(MAINBOARDDIR)/%.o: $(src)/mainboard/$(MAINBOARDDIR)/%.c >+ $(Q)mkdir -p $(obj)/mainboard/$(MAINBOARDDIR) >+ $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" >+ $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ >+ > >Added: LinuxBIOSv3/mainboard/artecgroup/dbe61/cmos.layout >=================================================================== >--- LinuxBIOSv3/mainboard/artecgroup/dbe61/cmos.layout (rev 0) >+++ LinuxBIOSv3/mainboard/artecgroup/dbe61/cmos.layout 2007-06-28 16:21:38 UTC (rev 394) >@@ -0,0 +1,74 @@ >+entries >+ >+#start-bit length config config-ID name >+#0 8 r 0 seconds >+#8 8 r 0 alarm_seconds >+#16 8 r 0 minutes >+#24 8 r 0 alarm_minutes >+#32 8 r 0 hours >+#40 8 r 0 alarm_hours >+#48 8 r 0 day_of_week >+#56 8 r 0 day_of_month >+#64 8 r 0 month >+#72 8 r 0 year >+#80 4 r 0 rate_select >+#84 3 r 0 REF_Clock >+#87 1 r 0 UIP >+#88 1 r 0 auto_switch_DST >+#89 1 r 0 24_hour_mode >+#90 1 r 0 binary_values_enable >+#91 1 r 0 square-wave_out_enable >+#92 1 r 0 update_finished_enable >+#93 1 r 0 alarm_interrupt_enable >+#94 1 r 0 periodic_interrupt_enable >+#95 1 r 0 disable_clock_updates >+#96 288 r 0 temporary_filler >+0 384 r 0 reserved_memory >+384 1 e 4 boot_option >+385 1 e 4 last_boot >+386 1 e 1 ECC_memory >+388 4 r 0 reboot_bits >+392 3 e 5 baud_rate >+400 1 e 1 power_on_after_fail >+412 4 e 6 debug_level >+416 4 e 7 boot_first >+420 4 e 7 boot_second >+424 4 e 7 boot_third >+428 4 h 0 boot_index >+432 8 h 0 boot_countdown >+1008 16 h 0 check_sum >+ >+enumerations >+ >+#ID value text >+1 0 Disable >+1 1 Enable >+2 0 Enable >+2 1 Disable >+4 0 Fallback >+4 1 Normal >+5 0 115200 >+5 1 57600 >+5 2 38400 >+5 3 19200 >+5 4 9600 >+5 5 4800 >+5 6 2400 >+5 7 1200 >+6 6 Notice >+6 7 Info >+6 8 Debug >+6 9 Spew >+7 0 Network >+7 1 HDD >+7 2 Floppy >+7 8 Fallback_Network >+7 9 Fallback_HDD >+7 10 Fallback_Floppy >+#7 3 ROM >+ >+checksums >+ >+checksum 392 1007 1008 >+ >+ > >Added: LinuxBIOSv3/mainboard/artecgroup/dbe61/dts >=================================================================== >--- LinuxBIOSv3/mainboard/artecgroup/dbe61/dts (rev 0) >+++ LinuxBIOSv3/mainboard/artecgroup/dbe61/dts 2007-06-28 16:21:38 UTC (rev 394) >@@ -0,0 +1,98 @@ >+/* >+ * This file is part of the LinuxBIOS project. >+ * >+ * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> >+ * >+ * This program is free software; you can redistribute it and/or modify >+ * it under the terms of the GNU General Public License as published by >+ * the Free Software Foundation; either version 2 of the License, or >+ * (at your option) any later version. >+ * >+ * This program is distributed in the hope that it will be useful, >+ * but WITHOUT ANY WARRANTY; without even the implied warranty of >+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >+ * GNU General Public License for more details. >+ * >+ * You should have received a copy of the GNU General Public License >+ * along with this program; if not, write to the Free Software >+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA >+ */ >+/* leave this in until we know how to do it in dts */ >+/* >+ chip southbridge/amd/cs5536_lx >+ register "enable_ide_nand_flash" = "0" >+ >+ register "isa_irq" = "0" >+ #register "flash_irq" = "14" >+ >+ ## IDE IRQ >+ register "enable_ide_irq" = "0" >+ >+ register "audio_irq" = "5" >+ register "usb_irq" = "7" >+ >+ register "uart0_irq" = "0" >+ register "uart1_irq" = "4" >+ >+ ## PCI INTA ... INTD and their GPIO pins >+ ## int==0: disable >+ register "pci_int[0]" = "0" >+ register "pci_int[1]" = "10" >+ register "pci_int[2]" = "0" >+ register "pci_int[3]" = "0" >+ register "pci_int_pin[0]" = "0" >+ register "pci_int_pin[1]" = "7" >+ register "pci_int_pin[2]" = "0" >+ register "pci_int_pin[3]" = "0" >+ >+ >+ # Keyboard Emulation Logic IRQs >+ # Enable keyboard IRQ2 >+ register "enable_kel_keyb_irq" = "0" >+ # Enable mouse IRQ12 >+ register "enable_kel_mouse_irq" = "0" >+ # Configure KEL Emulation IRQ, 0 to disable >+ register "kel_emul_irq" = "0" >+ >+ device pci f.0 on end # ISA Bridge >+ device pci f.1 on end # Flash controller >+ device pci f.2 off end # IDE controller >+ device pci f.3 on end # Audio >+ device pci f.4 on end # OHCI >+ device pci f.5 on end # EHCI >+ device pci f.6 off end # UDC controller >+ device pci f.7 off end # OTG controller >+ end >+# chip drivers/pci/rtl8139 >+## device pci d.0 on end # Realtek LAN >+# register "nic_irq" = "10" >+# end >+ end >+end >+ >+ >+*/ >+/{ >+ mainboard-vendor = "Artec Group"; >+ mainboard-part-number = "DBE61"; >+ enabled; >+ >+ cpus { >+ enabled; >+ }; >+ domain0 { >+ enabled; >+ pcidomain = "0"; >+ device0,0 { >+ enabled; >+ pcipath = "1,0"; >+ }; >+ southbridge{ >+ /config/("southbridge/amd/cs5536"); >+ pcipath = "1,1"; >+ enabled; >+ }; >+ >+ }; >+ >+}; > >Added: LinuxBIOSv3/mainboard/artecgroup/dbe61/initram.c >=================================================================== >--- LinuxBIOSv3/mainboard/artecgroup/dbe61/initram.c (rev 0) >+++ LinuxBIOSv3/mainboard/artecgroup/dbe61/initram.c 2007-06-28 16:21:38 UTC (rev 394) >@@ -0,0 +1,137 @@ >+/* >+ * This file is part of the LinuxBIOS project. >+ * >+ * Copyright (C) 2007 Advanced Micro Devices, Inc. >+ * >+ * This program is free software; you can redistribute it and/or modify >+ * it under the terms of the GNU General Public License as published by >+ * the Free Software Foundation; either version 2 of the License, or >+ * (at your option) any later version. >+ * >+ * This program is distributed in the hope that it will be useful, >+ * but WITHOUT ANY WARRANTY; without even the implied warranty of >+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >+ * GNU General Public License for more details. >+ * >+ * You should have received a copy of the GNU General Public License >+ * along with this program; if not, write to the Free Software >+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA >+ */ >+ >+#include <types.h> >+#include <lib.h> >+#include <console.h> >+#include <post_code.h> >+#include <device/device.h> >+#include <device/pci.h> >+#include <string.h> >+#include <msr.h> >+#include <io.h> >+#include <amd_geodelx.h> >+#include <southbridge/amd/cs5536/cs5536.h> >+#include <northbridge/amd/geodelx/raminit.h> >+ >+#define MANUALCONF 0 /* Do automatic strapped PLL config */ >+#define PLLMSRHI 0x00001490 /* manual settings for the PLL */ >+#define PLLMSRLO 0x02000030 >+#define DIVIL_LBAR_GPIO 0x5140000c >+#define DIMM0 ((u8) 0xA0) >+#define DIMM1 ((u8) 0xA2) >+ >+/* this is an incredibly mainboard-specific number that has no appropriate place >+ * outside this file. >+ */ >+#define GPIO_BASE 0x6100 >+ >+static void init_gpio(void) >+{ >+ msr_t msr; >+ printk(BIOS_DEBUG, "Initializing GPIO module...\n"); >+ >+ // initialize the GPIO LBAR >+ msr.lo = GPIO_BASE; >+ msr.hi = 0x0000f001; >+ wrmsr(DIVIL_LBAR_GPIO, msr); >+ msr = rdmsr(DIVIL_LBAR_GPIO); >+ printk(BIOS_DEBUG, "DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo); >+} >+ >+static void sdram_hardwire(void) >+{ >+ /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) * >+ * component Banks (byte 17) * module banks, side (byte 5) * >+ * width in bits (byte 6,7) >+ * = Density per side (byte 31) * number of sides (byte 5) */ >+ /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */ >+ msr_t msr; >+ >+ msr.hi = 0x10075012; >+ msr.lo = 0x00000040; >+ >+ wrmsr(MC_CF07_DATA, msr); //GX3 >+ >+ /* timing and mode ... */ >+ >+ //msr = rdmsr(0x20000019); >+ >+ /* per standard bios settings */ >+/* >+ msr.hi = 0x18000108; >+ msr.lo = >+ (6<<28) | // cas_lat >+ (10<<24)| // ref2act >+ (7<<20)| // act2pre >+ (3<<16)| // pre2act >+ (3<<12)| // act2cmd >+ (2<<8)| // act2act >+ (2<<6)| // dplwr >+ (2<<4)| // dplrd >+ (3); // dal >+ * the msr value reported by quanta is very, very different. >+ * we will go with that value for now. >+ * >+ //msr.lo = 0x286332a3; >+*/ >+ //wrmsr(0x20000019, msr); //GX3 >+ >+} >+ >+/* CPU and GLIU mult/div */ >+#define PLLMSRhi 0x0000039C >+/* Hold Count - how long we will sit in reset */ >+#define PLLMSRlo 0x00DE0000 >+ >+static void dbe61_msr_init(void) >+{ >+ __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); >+ __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); >+ >+ __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); >+ __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); >+} >+ >+int main(void) >+{ >+ post_code(POST_START_OF_MAIN); >+ >+ system_preinit(); >+ dbe61_msr_init(); >+ >+ cs5536_early_setup(); >+ >+ /* NOTE: must do this AFTER the early_setup! >+ * it is counting on some early MSR setup >+ * for cs5536. >+ */ >+ cs5536_setup_onchipuart(); >+ >+ pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO); >+ >+ cpu_reg_init(0, DIMM0, DIMM1); >+ >+ sdram_hardwire(); >+ /* Check low memory */ >+ /*ram_check(0x00000000, 640*1024); */ >+ init_gpio(); >+ return 0; >+} > >Added: LinuxBIOSv3/mainboard/artecgroup/dbe61/irq_tables.c >=================================================================== >--- LinuxBIOSv3/mainboard/artecgroup/dbe61/irq_tables.c (rev 0) >+++ LinuxBIOSv3/mainboard/artecgroup/dbe61/irq_tables.c 2007-06-28 16:21:38 UTC (rev 394) >@@ -0,0 +1,60 @@ >+/* This file was generated by getpir.c, do not modify! >+ (but if you do, please run checkpir on it to verify) >+ * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up >+ * >+ * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM >+*/ >+ >+#include <arch/pirq_routing.h> >+ >+#define ID_SLOT_PCI_NET 1 // ThinCan ethernet >+#define ID_SLOT_PCI_RSVD1 2 // reserved entry 1 >+#define ID_SLOT_PCI_RSVD3 3 // reserved entry 2 >+#define ID_SLOT_PCI_RSVD2 4 // reserved entry 3 >+#define ID_EMBED_PCI 0xff // onboard PCI device >+ >+// CS5535 PCI INT[A-D] Interrupt Routing lines. >+#define NO_CONNECT 0 // not used >+#define CS_PCI_INTA 1 // PCI INTA >+#define CS_PCI_INTB 2 // PCI INTB >+#define CS_PCI_INTC 3 // PCI INTC >+#define CS_PCI_INTD 4 // PCI INTD >+ >+// IRQ bitmap reference line FEDCBA9876543210 >+// 0000110000100000b >+#define PCI_IRQ 0xc20 // PCI allowed IRQs here >+ >+const struct irq_routing_table intel_irq_routing_table = >+{ >+ PIRQ_SIGNATURE, /* u32 signature */ >+ PIRQ_VERSION, /* u16 version */ >+ 32+16*6, /* there can be total 2 devices on the bus */ >+ 0x00, /* Where the interrupt router lies (bus) */ >+ (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ >+ 0x0800, /* IRQs devoted exclusively to PCI usage */ >+ 0x1022, /* Vendor */ >+ 0x208f, /* Device */ >+ 0x00000000, /* Crap (miniport) */ >+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ >+ 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ >+ { >+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ >+ // Geode GX3 Host Bridge and VGA Graphics >+ {0, 0x01<<3, {{CS_PCI_INTA, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}}, ID_EMBED_PCI, 0x0}, >+ // Realtek RTL8100/8139 Network Controller >+ {0, 0x0d<<3, {{CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}}, ID_SLOT_PCI_NET, 0x0}, >+ // Reserved for future extensions >+ {0, 0x0c<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_SLOT_PCI_RSVD1, 0x0}, >+ // Geode CS5535/CS5536 IO Companion: USB controllers, IDE, Audio. >+ {0, 0x0f<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_EMBED_PCI, 0x0}, >+ // Reserved for future extensions >+ {0, 0x0e<<3, {{CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}}, ID_SLOT_PCI_RSVD2, 0x0}, >+ // Reserved for future extensions >+ {0, 0x0b<<3, {{CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}}, ID_SLOT_PCI_RSVD3, 0x0} >+ } >+}; >+ >+unsigned long write_pirq_routing_table(unsigned long addr) >+{ >+ return copy_pirq_routing_table(addr); >+} > >Modified: LinuxBIOSv3/mainboard/emulation/qemu-x86/dts >=================================================================== >--- LinuxBIOSv3/mainboard/emulation/qemu-x86/dts 2007-06-28 15:19:30 UTC (rev 393) >+++ LinuxBIOSv3/mainboard/emulation/qemu-x86/dts 2007-06-28 16:21:38 UTC (rev 394) >@@ -18,6 +18,8 @@ > * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > */ > /{ >+ mainboard-vendor = "Emulation"; >+ mainboard-part-number = "QEMU x86"; > enabled; > constructor = "qemuvga_constructors"; > cpus { > >Deleted: LinuxBIOSv3/mainboard/emulation/qemu-x86/mainboard.c >=================================================================== >--- LinuxBIOSv3/mainboard/emulation/qemu-x86/mainboard.c 2007-06-28 15:19:30 UTC (rev 393) >+++ LinuxBIOSv3/mainboard/emulation/qemu-x86/mainboard.c 2007-06-28 16:21:38 UTC (rev 394) >@@ -1,24 +0,0 @@ >-/* >- * This file is part of the LinuxBIOS project. >- * >- * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> >- * Copyright (C) 2007 coresystems GmbH >- * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) >- * >- * This program is free software; you can redistribute it and/or modify >- * it under the terms of the GNU General Public License as published by >- * the Free Software Foundation; either version 2 of the License, or >- * (at your option) any later version. >- * >- * This program is distributed in the hope that it will be useful, >- * but WITHOUT ANY WARRANTY; without even the implied warranty of >- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >- * GNU General Public License for more details. >- * >- * You should have received a copy of the GNU General Public License >- * along with this program; if not, write to the Free Software >- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA >- */ >- >-const char *mainboard_vendor = "Emulation"; >-const char *mainboard_part_number = "QEMU x86"; > >Modified: LinuxBIOSv3/util/dtc/flattree.c >=================================================================== >--- LinuxBIOSv3/util/dtc/flattree.c 2007-06-28 15:19:30 UTC (rev 393) >+++ LinuxBIOSv3/util/dtc/flattree.c 2007-06-28 16:21:38 UTC (rev 394) >@@ -112,6 +112,7 @@ > else > *cp = *src; > } >+ *cp = 0; > cp = ret; > if (suffix) > strcat(cp, suffix); >@@ -1254,6 +1255,7 @@ > > void dt_to_linuxbios(FILE *f, struct boot_info *bi, int version, int boot_cpuid_phys) > { >+ struct property *prop; > struct version_info *vi = NULL; > int i; > struct data strbuf = empty_data; >@@ -1261,6 +1263,7 @@ > extern char *code; > struct node *next; > extern struct node *first_node; >+ int found_mainboard_vendor = 0, found_mainboard_partnumber = 0; > > labeltree(bi->dt); > >@@ -1283,6 +1286,30 @@ > for(next = first_node; next; next = next->next) > fprintf(f, "struct device dev_%s;\n", next->label); > >+ /* special for the root. Emit the names for the mainboard vendor and part # */ >+ for_each_property(bi->dt, prop) { >+ if (streq(prop->name, "mainboard-vendor")){ >+ found_mainboard_vendor = 1; >+ fprintf(f, "const char *mainboard_vendor = \"%s\";\n", prop->val.val); >+ } >+ if (streq(prop->name, "mainboard-part-number")){ >+ found_mainboard_partnumber = 1; >+ fprintf(f, "const char *mainboard_part_number = \"%s\";\n", prop->val.val); >+ } >+ } >+ >+ if (! found_mainboard_vendor){ >+ die("There is no mainboard-vendor property in the root. Please add one." >+ "(and make sure there is a mainboard-part-number property too"); >+ } >+ >+ if (! found_mainboard_partnumber){ >+ die("There is no mainboard-part-number property in the root. " >+ "Please add one." >+ "(and make sure there is a mainboard-vendor property too"); >+ } >+ >+ > /* emit the code, if any */ > if (code) > fprintf(f, "%s\n", code); >@@ -1323,6 +1350,7 @@ > fix_next(bi->dt); > /* emit any includes that we need -- TODO: ONLY ONCE PER TYPE*/ > fprintf(f, "#include <device/device.h>\n#include <device/pci.h>\n"); >+ fprintf(f, "extern const char *mainboard_vendor, *mainboard_part_number;\n"); > flatten_tree_emit_includes(bi->dt, &linuxbios_emitter, f, &strbuf, vi); > > flatten_tree_emit_structdecls(bi->dt, &linuxbios_emitter, f, &strbuf, vi); > > > >

1 0

Re: [LinuxBIOS] r367 - in LinuxBIOSv3: . include/arch/x86
by Stefan Reinauer 28 Jun '07

28 Jun '07

* svn(a)openbios.org <svn(a)openbios.org> [070626 15:46]: > /* > - * This program is free software; you can redistribute it and/or modify > - * it under the terms of the GNU General Public License as published by > - * the Free Software Foundation; either version 2 of the License, or > - * (at your option) any later version. > - * > - * This program is distributed in the hope that it will be useful, > - * but WITHOUT ANY WARRANTY; without even the implied warranty of > - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > - * GNU General Public License for more details. > - * > - * You should have received a copy of the GNU General Public License > - * along with this program; if not, write to the Free Software > - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA Nack, please dont remove license headers. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/

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[LinuxBIOS] r405 - in LinuxBIOSv3: device include/device
by svn＠openbios.org 28 Jun '07

28 Jun '07

Author: stepan Date: 2007-06-28 22:09:41 +0200 (Thu, 28 Jun 2007) New Revision: 405 Modified: LinuxBIOSv3/device/device.c LinuxBIOSv3/include/device/device.h Log: Make dtsname a static part of the device structure. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: LinuxBIOSv3/device/device.c =================================================================== --- LinuxBIOSv3/device/device.c 2007-06-28 18:30:55 UTC (rev 404) +++ LinuxBIOSv3/device/device.c 2007-06-28 20:09:41 UTC (rev 405) @@ -221,10 +221,6 @@ last_dev_p = &dev->next; /* Give the device a name. */ - dev->dtsname = malloc(32); - if (dev->dtsname == NULL) { - die("DEV: out of memory.\n"); - } sprintf(dev->dtsname, "dynamic %s", dev_path(dev)); // spin_unlock(&dev_lock); Modified: LinuxBIOSv3/include/device/device.h =================================================================== --- LinuxBIOSv3/include/device/device.h 2007-06-28 18:30:55 UTC (rev 404) +++ LinuxBIOSv3/include/device/device.h 2007-06-28 20:09:41 UTC (rev 405) @@ -169,6 +169,7 @@ #define MAX_RESOURCES 12 #define MAX_LINKS 8 +#define MAX_DTSNAME_SIZE 64 /* * There is one device structure for each slot-number/function-number * combination: @@ -181,7 +182,7 @@ struct device * next; /* chain of all devices */ struct device_path path; - char * dtsname; /* the name from the dts */ + char dtsname[MAX_DTSNAME_SIZE]; /* the name from the dts */ unsigned vendor; unsigned device; unsigned int class; /* 3 bytes: (base,sub,prog-if) */

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coreboot June 2007