Author: rminnich
Date: 2007-06-29 17:21:38 +0200 (Fri, 29 Jun 2007)
New Revision: 414
Added:
LinuxBIOSv3/mainboard/amd/norwich/stage1.c
LinuxBIOSv3/mainboard/artecgroup/dbe61/stage1.c
LinuxBIOSv3/mainboard/emulation/qemu-x86/stage1.c
Modified:
LinuxBIOSv3/mainboard/amd/norwich/Makefile
LinuxBIOSv3/mainboard/amd/norwich/initram.c
LinuxBIOSv3/mainboard/artecgroup/dbe61/Makefile
LinuxBIOSv3/mainboard/artecgroup/dbe61/initram.c
LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile
Log:
This completes the creation of a stage1 for each mainboard, and renames
all the early_*
stuff to stage1. All targets build and qemu boots.
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
Acked-by: Stefan Reinauer <stepan(a)coresystems.de>
Modified: LinuxBIOSv3/mainboard/amd/norwich/Makefile
===================================================================
--- LinuxBIOSv3/mainboard/amd/norwich/Makefile 2007-06-29 14:36:03 UTC (rev 413)
+++ LinuxBIOSv3/mainboard/amd/norwich/Makefile 2007-06-29 15:21:38 UTC (rev 414)
@@ -18,6 +18,10 @@
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+STAGE0_MAINBOARD_OBJ :=\
+ $(obj)/southbridge/amd/cs5536/stage1.o\
+ $(obj)/arch/x86/geodelx/stage1.o \
+ $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
$(obj)/linuxbios.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
@@ -26,8 +30,6 @@
INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \
$(obj)/northbridge/amd/geodelx/raminit.o \
$(obj)/southbridge/amd/cs5536/smbus_initram.o \
- $(obj)/southbridge/amd/cs5536/cs5536_early_setup.o\
- $(obj)/device/pnp_raw.o \
$(obj)/arch/x86/geodelx/geodelx.o
$(obj)/linuxbios.initram: $(obj)/stage0.init $(obj)/stage0.o $(INITRAM_OBJ)
Modified: LinuxBIOSv3/mainboard/amd/norwich/initram.c
===================================================================
--- LinuxBIOSv3/mainboard/amd/norwich/initram.c 2007-06-29 14:36:03 UTC (rev 413)
+++ LinuxBIOSv3/mainboard/amd/norwich/initram.c 2007-06-29 15:21:38 UTC (rev 414)
@@ -28,7 +28,6 @@
#include <msr.h>
#include <io.h>
#include <amd_geodelx.h>
-#include <southbridge/amd/cs5536/cs5536.h>
#include <northbridge/amd/geodelx/raminit.h>
#define MANUALCONF 0 /* Do automatic strapped PLL config */
@@ -64,18 +63,7 @@
post_code(POST_START_OF_MAIN);
system_preinit();
- geodelx_msr_init();
- cs5536_early_setup();
-
- /* NOTE: must do this AFTER the early_setup!
- * it is counting on some early MSR setup
- * for cs5536.
- */
- /* We do this early for debug.
- * real setup should done in chipset init via config.lb
- */
- cs5536_setup_onchipuart();
mb_gpio_init();
pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
Added: LinuxBIOSv3/mainboard/amd/norwich/stage1.c
===================================================================
--- LinuxBIOSv3/mainboard/amd/norwich/stage1.c (rev 0)
+++ LinuxBIOSv3/mainboard/amd/norwich/stage1.c 2007-06-29 15:21:38 UTC (rev 414)
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <post_code.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <msr.h>
+#include <io.h>
+#include <amd_geodelx.h>
+#include <southbridge/amd/cs5536/cs5536.h>
+
+int hardware_stage1(void)
+{
+ post_code(POST_START_OF_MAIN);
+ geodelx_msr_init();
+
+ cs5536_stage1();
+
+ /* NOTE: must do this AFTER the early_setup!
+ * it is counting on some early MSR setup
+ * for cs5536.
+ */
+ /* We do this early for debug.
+ * real setup should done in chipset init via config.lb
+ */
+ cs5536_setup_onchipuart();
+}
Modified: LinuxBIOSv3/mainboard/artecgroup/dbe61/Makefile
===================================================================
--- LinuxBIOSv3/mainboard/artecgroup/dbe61/Makefile 2007-06-29 14:36:03 UTC (rev 413)
+++ LinuxBIOSv3/mainboard/artecgroup/dbe61/Makefile 2007-06-29 15:21:38 UTC (rev 414)
@@ -18,13 +18,16 @@
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+STAGE0_MAINBOARD_OBJ := \
+ $(obj)/southbridge/amd/cs5536/stage1.o\
+ $(obj)/arch/x86/geodelx/stage1.o \
+ $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
$(obj)/linuxbios.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
$(Q)dd if=/dev/zero of=$(obj)/linuxbios.vpd bs=256 count=1 $(SILENT)
INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \
- $(obj)/southbridge/amd/cs5536/cs5536_early_setup.o\
$(obj)/arch/x86/geodelx/geodelx.o
$(obj)/linuxbios.initram: $(obj)/stage0.init $(obj)/stage0.o $(INITRAM_OBJ)
Modified: LinuxBIOSv3/mainboard/artecgroup/dbe61/initram.c
===================================================================
--- LinuxBIOSv3/mainboard/artecgroup/dbe61/initram.c 2007-06-29 14:36:03 UTC (rev 413)
+++ LinuxBIOSv3/mainboard/artecgroup/dbe61/initram.c 2007-06-29 15:21:38 UTC (rev 414)
@@ -129,16 +129,7 @@
post_code(POST_START_OF_MAIN);
system_preinit();
- dbe61_msr_init();
- cs5536_early_setup();
-
- /* NOTE: must do this AFTER the early_setup!
- * it is counting on some early MSR setup
- * for cs5536.
- */
- cs5536_setup_onchipuart();
-
pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
cpu_reg_init(0, DIMM0, DIMM1);
Added: LinuxBIOSv3/mainboard/artecgroup/dbe61/stage1.c
===================================================================
--- LinuxBIOSv3/mainboard/artecgroup/dbe61/stage1.c (rev 0)
+++ LinuxBIOSv3/mainboard/artecgroup/dbe61/stage1.c 2007-06-29 15:21:38 UTC (rev 414)
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <post_code.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <msr.h>
+#include <io.h>
+#include <amd_geodelx.h>
+#include <southbridge/amd/cs5536/cs5536.h>
+#include <northbridge/amd/geodelx/raminit.h>
+
+struct wmsr {
+ u32 reg;
+ struct msr msr;
+} dbe61_msr[] = {
+ {.reg = 0x10000020, {.lo = 0xfff80, .hi = 0x20000000}},
+ {.reg = 0x10000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
+ {.reg = 0x40000020, {.lo = 0xfff80, .hi = 0x20000000}},
+ {.reg = 0x40000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
+};
+
+static void dbe61_msr_init(void)
+{
+ int i;
+ for(i = 0; i < sizeof(dbe61_msr)/sizeof(dbe61_msr[0]); i++)
+ wrmsr(dbe61_msr[i].reg, dbe61_msr[i].msr);
+}
+
+int hardware_stage1(void)
+{
+ post_code(POST_START_OF_MAIN);
+
+ dbe61_msr_init();
+
+ cs5536_stage1();
+
+ /* NOTE: must do this AFTER the early_setup!
+ * it is counting on some early MSR setup
+ * for cs5536.
+ */
+ cs5536_setup_onchipuart();
+}
Modified: LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile
===================================================================
--- LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile 2007-06-29 14:36:03 UTC (rev 413)
+++ LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile 2007-06-29 15:21:38 UTC (rev 414)
@@ -19,6 +19,9 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+
+STAGE0_MAINBOARD_OBJ :=\
+ $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
#
# VPD or SIP ROM or ... how does NVIDIA call it?
# Some space to cope with dirty southbridge tricks.
@@ -35,12 +38,12 @@
# The initram file is always uncompressed. It belongs into the mainboard
# directory and is built from what was auto.c in v2.
#
+INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o
-$(obj)/linuxbios.initram: $(obj)/stage0.init $(obj)/stage0.o $(obj)/mainboard/$(MAINBOARDDIR)/initram.o
+$(obj)/linuxbios.initram: $(obj)/stage0.init $(obj)/stage0.o $(INITRAM_OBJ)
$(Q)# initram links against stage0
$(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n"
- $(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x80000 \
- $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \
+ $(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x80000 $(INITRAM_OBJ) \
--entry=main -o $(obj)/linuxbios.initram.o
$(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(OBJCOPY) -O binary $(obj)/linuxbios.initram.o \
Added: LinuxBIOSv3/mainboard/emulation/qemu-x86/stage1.c
===================================================================
--- LinuxBIOSv3/mainboard/emulation/qemu-x86/stage1.c (rev 0)
+++ LinuxBIOSv3/mainboard/emulation/qemu-x86/stage1.c 2007-06-29 15:21:38 UTC (rev 414)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* no printk allowed until hardware is ready; hardware is ready */
+/**
+ * start up hardware needed for stage1
+ */
+void hardware_stage1(void)
+{
+}
Author: rminnich
Date: 2007-06-29 16:20:02 +0200 (Fri, 29 Jun 2007)
New Revision: 412
Added:
LinuxBIOSv3/arch/x86/stage1.c
Removed:
LinuxBIOSv3/arch/x86/cachemain.c
Modified:
LinuxBIOSv3/arch/x86/Makefile
Log:
mv cachemain.c to stage1.c, so that people can tell when it runs.
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
Acked-by: Stefan Reinauer <stepan(a)coresystems.de>
Modified: LinuxBIOSv3/arch/x86/Makefile
===================================================================
--- LinuxBIOSv3/arch/x86/Makefile 2007-06-29 13:28:33 UTC (rev 411)
+++ LinuxBIOSv3/arch/x86/Makefile 2007-06-29 14:20:02 UTC (rev 412)
@@ -76,7 +76,7 @@
STAGE0_LIB_OBJ = uart8250.o mem.o elfboot.o lar.o delay.o vtxprintf.o \
vsprintf.o console.o
-STAGE0_ARCH_X86_OBJ = cachemain.o serial.o archelfboot.o speaker.o \
+STAGE0_ARCH_X86_OBJ = stage1.o serial.o archelfboot.o speaker.o \
udelay_io.o mc146818rtc.o
ifeq ($(CONFIG_CPU_I586),y)
Deleted: LinuxBIOSv3/arch/x86/cachemain.c
===================================================================
--- LinuxBIOSv3/arch/x86/cachemain.c 2007-06-29 13:28:33 UTC (rev 411)
+++ LinuxBIOSv3/arch/x86/cachemain.c 2007-06-29 14:20:02 UTC (rev 412)
@@ -1,233 +0,0 @@
-/*
- * This file is part of the LinuxBIOS project.
- *
- * Copyright (C) 2007 Stefan Reinauer <stepan(a)coresystems.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <types.h>
-#include <io.h>
-#include <console.h>
-#include <lar.h>
-#include <tables.h>
-#include <lib.h>
-#include <mc146818rtc.h>
-
-/* these prototypes should go into headers */
-void uart_init(void);
-void die(const char *msg);
-int find_file(struct mem_file *archive, char *filename, struct mem_file *result);
-void hardware_stage1(void);
-
-// Is this value correct?
-#define DCACHE_RAM_SIZE 0x8000
-
-
-void post_code(u8 value)
-{
- outb(value, 0x80);
-}
-
-static void stop_ap(void)
-{
- // nothing yet
- post_code(0xf0);
-}
-
-static void enable_rom(void)
-{
- // nothing here yet
- post_code(0xf2);
-}
-
-void stage1_main(u32 bist)
-{
- int ret;
- struct mem_file archive, result;
- int elfboot_mem(struct lb_memory *mem, void *where, int size);
-
- /* we can't statically init this hack. */
- unsigned char faker[64];
- struct lb_memory *mem = (struct lb_memory*) faker;
-
- mem->tag = LB_TAG_MEMORY;
- mem->size = 28;
- mem->map[0].start.lo = mem->map[0].start.hi = 0;
- mem->map[0].size.lo = (32*1024*1024);
- mem->map[0].size.hi = 0;
- mem->map[0].type = LB_MEM_RAM;
-
-
- post_code(0x02);
-
- // before we do anything, we want to stop if we dont run
- // on the bootstrap processor.
- if (bist==0) {
- // stop secondaries
- stop_ap();
- }
-
- // We have cache as ram running and can start executing code in C.
- //
-
- hardware_stage1();
-
- //
- uart_init(); // initialize serial port
- console_init(); // print banner
-
- if (bist!=0) {
- printk(BIOS_INFO, "BIST FAILED: %08x", bist);
- die("");
- }
-
- // enable rom
- enable_rom();
-
- // location and size of image.
-
- // FIXME this should be defined in the VPD area
- // but NOT IN THE CODE.
-
- archive.len=(CONFIG_LINUXBIOS_ROMSIZE_KB-16)*1024;
- archive.start=(void *)(0UL-(CONFIG_LINUXBIOS_ROMSIZE_KB*1024));
-
- // FIXME check integrity
-
-
- // find first initram
- if (last_boot_normal()) {
- printk(BIOS_DEBUG, "Choosing normal boot.\n");
- ret = run_file(&archive, "normal/initram", (void *)(512*1024)); //CONFIG_CARBASE;
- } else {
- printk(BIOS_DEBUG, "Choosing fallback boot.\n");
- ret = run_file(&archive, "fallback/initram", (void *)(512*1024)); //CONFIG_CARBASE;
- }
-
- if (ret)
- die("Failed RAM init code\n");
-
- printk(BIOS_INFO, "Done RAM init code\n");
- /* this is nasty. And, it has to be done this way. Sorry! */
- /* we have to turn off CAR, and do some other things, and it has to be done
- * inline -- you can't call a function
- */
-
- __asm__ volatile (
- /*
- FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
- It is only needed if we want to go back
- */
-
- /* We don't need cache as ram for now on */
- /* disable cache */
- "movl %cr0, %eax\n\t"
- "orl $(0x1<<30),%eax\n\t"
- "movl %eax, %cr0\n\t"
-
- /* clear sth */
- "movl $0x269, %ecx\n\t" /* fix4k_c8000*/
- "xorl %edx, %edx\n\t"
- "xorl %eax, %eax\n\t"
- "wrmsr\n\t"
-#if DCACHE_RAM_SIZE > 0x8000
- "movl $0x268, %ecx\n\t" /* fix4k_c0000*/
- "wrmsr\n\t"
-#endif
-
- /* Set the default memory type and disable fixed and enable variable MTRRs */
- "movl $0x2ff, %ecx\n\t"
-// "movl $MTRRdefType_MSR, %ecx\n\t"
- "xorl %edx, %edx\n\t"
- /* Enable Variable and Disable Fixed MTRRs */
- "movl $0x00000800, %eax\n\t"
- "wrmsr\n\t"
-
-#if defined(CLEAR_FIRST_1M_RAM)
- /* enable caching for first 1M using variable mtrr */
- "movl $0x200, %ecx\n\t"
- "xorl %edx, %edx\n\t"
- "movl $(0 | 1), %eax\n\t"
-// "movl $(0 | MTRR_TYPE_WRCOMB), %eax\n\t"
- "wrmsr\n\t"
-
- "movl $0x201, %ecx\n\t"
- "movl $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/
- "movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
- "wrmsr\n\t"
-#endif
-
- /* enable cache */
- "movl %cr0, %eax\n\t"
- "andl $0x9fffffff,%eax\n\t"
- "movl %eax, %cr0\n\t"
-#if defined(CLEAR_FIRST_1M_RAM)
- /* clear the first 1M */
- "movl $0x0, %edi\n\t"
- "cld\n\t"
- "movl $(0x100000>>2), %ecx\n\t"
- "xorl %eax, %eax\n\t"
- "rep stosl\n\t"
-
- /* disable cache */
- "movl %cr0, %eax\n\t"
- "orl $(0x1<<30),%eax\n\t"
- "movl %eax, %cr0\n\t"
-
- /* enable caching for first 1M using variable mtrr */
- "movl $0x200, %ecx\n\t"
- "xorl %edx, %edx\n\t"
- "movl $(0 | 6), %eax\n\t"
-// "movl $(0 | MTRR_TYPE_WRBACK), %eax\n\t"
- "wrmsr\n\t"
-
- "movl $0x201, %ecx\n\t"
- "movl $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/
- "movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
- "wrmsr\n\t"
-
- /* enable cache */
- "movl %cr0, %eax\n\t"
- "andl $0x9fffffff,%eax\n\t"
- "movl %eax, %cr0\n\t"
- "invd\n\t"
-
- /*
- FIXME: I hope we don't need to change esp and ebp value here, so we can restore value from mmx sse back
- But the problem is the range is some io related, So don't go back
- */
-#endif
- );
-
- ret = run_file(&archive, "normal/stage2", (void *)0x1000);
- if (ret)
- die("FATAL: Failed in stage2 code.");
-
- printk(BIOS_DEBUG, "Stage2 code done.\n");
-
- ret = find_file(&archive, "normal/payload", &result);
- if (ret) {
- printk(BIOS_WARNING, "No such file '%s'.\n", "normal/payload");
- die("FATAL: No payload found.\n");
- }
-
- ret = elfboot_mem(mem, result.start, result.len);
-
- printk(BIOS_DEBUG, "elfboot_mem returns %d\n", ret);
-
- die ("FATAL: Last stage returned to LinuxBIOS.\n");
-}
-
-
Copied: LinuxBIOSv3/arch/x86/stage1.c (from rev 409, LinuxBIOSv3/arch/x86/cachemain.c)
===================================================================
--- LinuxBIOSv3/arch/x86/stage1.c (rev 0)
+++ LinuxBIOSv3/arch/x86/stage1.c 2007-06-29 14:20:02 UTC (rev 412)
@@ -0,0 +1,233 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Stefan Reinauer <stepan(a)coresystems.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <io.h>
+#include <console.h>
+#include <lar.h>
+#include <tables.h>
+#include <lib.h>
+#include <mc146818rtc.h>
+
+/* these prototypes should go into headers */
+void uart_init(void);
+void die(const char *msg);
+int find_file(struct mem_file *archive, char *filename, struct mem_file *result);
+void hardware_stage1(void);
+
+// Is this value correct?
+#define DCACHE_RAM_SIZE 0x8000
+
+
+void post_code(u8 value)
+{
+ outb(value, 0x80);
+}
+
+static void stop_ap(void)
+{
+ // nothing yet
+ post_code(0xf0);
+}
+
+static void enable_rom(void)
+{
+ // nothing here yet
+ post_code(0xf2);
+}
+
+void stage1_main(u32 bist)
+{
+ int ret;
+ struct mem_file archive, result;
+ int elfboot_mem(struct lb_memory *mem, void *where, int size);
+
+ /* we can't statically init this hack. */
+ unsigned char faker[64];
+ struct lb_memory *mem = (struct lb_memory*) faker;
+
+ mem->tag = LB_TAG_MEMORY;
+ mem->size = 28;
+ mem->map[0].start.lo = mem->map[0].start.hi = 0;
+ mem->map[0].size.lo = (32*1024*1024);
+ mem->map[0].size.hi = 0;
+ mem->map[0].type = LB_MEM_RAM;
+
+
+ post_code(0x02);
+
+ // before we do anything, we want to stop if we dont run
+ // on the bootstrap processor.
+ if (bist==0) {
+ // stop secondaries
+ stop_ap();
+ }
+
+ // We have cache as ram running and can start executing code in C.
+ //
+
+ hardware_stage1();
+
+ //
+ uart_init(); // initialize serial port
+ console_init(); // print banner
+
+ if (bist!=0) {
+ printk(BIOS_INFO, "BIST FAILED: %08x", bist);
+ die("");
+ }
+
+ // enable rom
+ enable_rom();
+
+ // location and size of image.
+
+ // FIXME this should be defined in the VPD area
+ // but NOT IN THE CODE.
+
+ archive.len=(CONFIG_LINUXBIOS_ROMSIZE_KB-16)*1024;
+ archive.start=(void *)(0UL-(CONFIG_LINUXBIOS_ROMSIZE_KB*1024));
+
+ // FIXME check integrity
+
+
+ // find first initram
+ if (last_boot_normal()) {
+ printk(BIOS_DEBUG, "Choosing normal boot.\n");
+ ret = run_file(&archive, "normal/initram", (void *)(512*1024)); //CONFIG_CARBASE;
+ } else {
+ printk(BIOS_DEBUG, "Choosing fallback boot.\n");
+ ret = run_file(&archive, "fallback/initram", (void *)(512*1024)); //CONFIG_CARBASE;
+ }
+
+ if (ret)
+ die("Failed RAM init code\n");
+
+ printk(BIOS_INFO, "Done RAM init code\n");
+ /* this is nasty. And, it has to be done this way. Sorry! */
+ /* we have to turn off CAR, and do some other things, and it has to be done
+ * inline -- you can't call a function
+ */
+
+ __asm__ volatile (
+ /*
+ FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
+ It is only needed if we want to go back
+ */
+
+ /* We don't need cache as ram for now on */
+ /* disable cache */
+ "movl %cr0, %eax\n\t"
+ "orl $(0x1<<30),%eax\n\t"
+ "movl %eax, %cr0\n\t"
+
+ /* clear sth */
+ "movl $0x269, %ecx\n\t" /* fix4k_c8000*/
+ "xorl %edx, %edx\n\t"
+ "xorl %eax, %eax\n\t"
+ "wrmsr\n\t"
+#if DCACHE_RAM_SIZE > 0x8000
+ "movl $0x268, %ecx\n\t" /* fix4k_c0000*/
+ "wrmsr\n\t"
+#endif
+
+ /* Set the default memory type and disable fixed and enable variable MTRRs */
+ "movl $0x2ff, %ecx\n\t"
+// "movl $MTRRdefType_MSR, %ecx\n\t"
+ "xorl %edx, %edx\n\t"
+ /* Enable Variable and Disable Fixed MTRRs */
+ "movl $0x00000800, %eax\n\t"
+ "wrmsr\n\t"
+
+#if defined(CLEAR_FIRST_1M_RAM)
+ /* enable caching for first 1M using variable mtrr */
+ "movl $0x200, %ecx\n\t"
+ "xorl %edx, %edx\n\t"
+ "movl $(0 | 1), %eax\n\t"
+// "movl $(0 | MTRR_TYPE_WRCOMB), %eax\n\t"
+ "wrmsr\n\t"
+
+ "movl $0x201, %ecx\n\t"
+ "movl $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/
+ "movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
+ "wrmsr\n\t"
+#endif
+
+ /* enable cache */
+ "movl %cr0, %eax\n\t"
+ "andl $0x9fffffff,%eax\n\t"
+ "movl %eax, %cr0\n\t"
+#if defined(CLEAR_FIRST_1M_RAM)
+ /* clear the first 1M */
+ "movl $0x0, %edi\n\t"
+ "cld\n\t"
+ "movl $(0x100000>>2), %ecx\n\t"
+ "xorl %eax, %eax\n\t"
+ "rep stosl\n\t"
+
+ /* disable cache */
+ "movl %cr0, %eax\n\t"
+ "orl $(0x1<<30),%eax\n\t"
+ "movl %eax, %cr0\n\t"
+
+ /* enable caching for first 1M using variable mtrr */
+ "movl $0x200, %ecx\n\t"
+ "xorl %edx, %edx\n\t"
+ "movl $(0 | 6), %eax\n\t"
+// "movl $(0 | MTRR_TYPE_WRBACK), %eax\n\t"
+ "wrmsr\n\t"
+
+ "movl $0x201, %ecx\n\t"
+ "movl $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/
+ "movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
+ "wrmsr\n\t"
+
+ /* enable cache */
+ "movl %cr0, %eax\n\t"
+ "andl $0x9fffffff,%eax\n\t"
+ "movl %eax, %cr0\n\t"
+ "invd\n\t"
+
+ /*
+ FIXME: I hope we don't need to change esp and ebp value here, so we can restore value from mmx sse back
+ But the problem is the range is some io related, So don't go back
+ */
+#endif
+ );
+
+ ret = run_file(&archive, "normal/stage2", (void *)0x1000);
+ if (ret)
+ die("FATAL: Failed in stage2 code.");
+
+ printk(BIOS_DEBUG, "Stage2 code done.\n");
+
+ ret = find_file(&archive, "normal/payload", &result);
+ if (ret) {
+ printk(BIOS_WARNING, "No such file '%s'.\n", "normal/payload");
+ die("FATAL: No payload found.\n");
+ }
+
+ ret = elfboot_mem(mem, result.start, result.len);
+
+ printk(BIOS_DEBUG, "elfboot_mem returns %d\n", ret);
+
+ die ("FATAL: Last stage returned to LinuxBIOS.\n");
+}
+
+
Author: uwe
Date: 2007-06-29 15:28:33 +0200 (Fri, 29 Jun 2007)
New Revision: 411
Modified:
LinuxBIOSv3/arch/x86/Kconfig
LinuxBIOSv3/device/Kconfig
LinuxBIOSv3/lib/Kconfig
LinuxBIOSv3/mainboard/Kconfig
LinuxBIOSv3/mainboard/adl/Kconfig
LinuxBIOSv3/mainboard/adl/msm800sev/Kconfig
LinuxBIOSv3/mainboard/amd/Kconfig
LinuxBIOSv3/mainboard/amd/norwich/Kconfig
LinuxBIOSv3/mainboard/artecgroup/Kconfig
LinuxBIOSv3/mainboard/artecgroup/dbe61/Kconfig
LinuxBIOSv3/northbridge/intel/i440bxemulation/Kconfig
Log:
Various Kconfig file fixes (trivial).
Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de>
Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de>
Modified: LinuxBIOSv3/arch/x86/Kconfig
===================================================================
--- LinuxBIOSv3/arch/x86/Kconfig 2007-06-29 12:40:13 UTC (rev 410)
+++ LinuxBIOSv3/arch/x86/Kconfig 2007-06-29 13:28:33 UTC (rev 411)
@@ -55,4 +55,3 @@
a battery backed up real time clock with CMOS NVRAM.
It is usually set in mainboard/*/Kconfig.
-
Modified: LinuxBIOSv3/device/Kconfig
===================================================================
--- LinuxBIOSv3/device/Kconfig 2007-06-29 12:40:13 UTC (rev 410)
+++ LinuxBIOSv3/device/Kconfig 2007-06-29 13:28:33 UTC (rev 411)
@@ -33,7 +33,7 @@
default PCI_OPTION_ROM_RUN_VM86
help
Execute PCI/AGP option ROMs if available. You can choose to
- execute PCI option ROMs natively (32bit x86 system required),
+ execute PCI option ROMs natively (32bit x86 system required),
in an emulator (x86emu), or ignore option ROM execution.
@@ -41,9 +41,9 @@
bool "x86emu"
select PCI_OPTION_ROM_RUN
help
- If you choose this option, the x86 instruction set emulator
+ If you choose this option, the x86 instruction set emulator
x86emu is used to execute 16bit legacy BIOS option ROMs.
-
+
x86emu is slow, big and safe. All 16bit x86 code is executed
in an encapsulated environment where it can not break out.
@@ -56,7 +56,7 @@
If you choose this option, the virtual x86 mode "vm86" is used
to execute 16bit legacy BIOS option ROMs.
- vm86 is very small, fast, and probably a little less safe than
+ vm86 is very small, fast, and probably a little less safe than
x86emu, since it runs option ROMs on the real hardware instead
of an emulator.
@@ -65,12 +65,11 @@
help
Do not execute PCI option ROMs at all.
- If you choose this option, VGA plugin cards will not be
- initialized.
+ If you choose this option, VGA plugin cards will not be initialized.
endchoice
-# This should probably become a CMOS option
+# TODO: This should probably become a CMOS option.
config MULTIPLE_VGA_INIT
bool "Initialize all VGA cards"
depends PCI_OPTION_ROM_RUN
Modified: LinuxBIOSv3/lib/Kconfig
===================================================================
--- LinuxBIOSv3/lib/Kconfig 2007-06-29 12:40:13 UTC (rev 410)
+++ LinuxBIOSv3/lib/Kconfig 2007-06-29 13:28:33 UTC (rev 411)
@@ -3,7 +3,7 @@
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH)
-## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de>
+## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -208,7 +208,7 @@
* 8086:268c Intel 631xESB/632xESB/3100
* 8086:27cc Intel ICH7
* 8086:2836 Intel ICH8
- * 8086:283a Intel ICH8
+ * 8086:283a Intel ICH8
See http://linuxbios.org/EHCI_Debug_Port for an up-to-date list.
@@ -220,7 +220,7 @@
depends EXPERT && (CONSOLE_SERIAL || CONSOLE_USB)
default n
help
- When you enable this option, LinuxBIOS will prefix each line of
+ When you enable this option, LinuxBIOS will prefix each line of
console output with '(LB)'.
endmenu
Modified: LinuxBIOSv3/mainboard/Kconfig
===================================================================
--- LinuxBIOSv3/mainboard/Kconfig 2007-06-29 12:40:13 UTC (rev 410)
+++ LinuxBIOSv3/mainboard/Kconfig 2007-06-29 13:28:33 UTC (rev 411)
@@ -29,20 +29,18 @@
config VENDOR_ADL
bool "Advanced Digital Logic"
help
- Select this option for various systems from
- Advanced Digital Logic
+ Select this option for various systems from Advanced Digital Logic.
config VENDOR_AMD
bool "AMD"
help
Select this option for various systems from
- Advanced Micro Devices, Inc
+ Advanced Micro Devices, Inc.
config VENDOR_ARTECGROUP
bool "Artec Group"
help
- Select this option for various systems from
- the Artec Group
+ Select this option for various systems from the Artec Group.
config VENDOR_EMULATION
bool "Emulated systems"
@@ -51,10 +49,10 @@
endchoice
-source "mainboard/emulation/Kconfig"
source "mainboard/adl/Kconfig"
source "mainboard/amd/Kconfig"
source "mainboard/artecgroup/Kconfig"
+source "mainboard/emulation/Kconfig"
choice
prompt "ROM chip size"
Modified: LinuxBIOSv3/mainboard/adl/Kconfig
===================================================================
--- LinuxBIOSv3/mainboard/adl/Kconfig 2007-06-29 12:40:13 UTC (rev 410)
+++ LinuxBIOSv3/mainboard/adl/Kconfig 2007-06-29 13:28:33 UTC (rev 411)
@@ -24,7 +24,7 @@
depends on VENDOR_ADL
config BOARD_ADL_MSM800SEV
- bool "msm800sev"
+ bool "MSM800SEV"
select ARCH_X86
select CPU_AMD_GEODELX
select OPTION_TABLE
@@ -32,7 +32,8 @@
select SOUTHBRIDGE_AMD_CS5536
select SUPERIO_WINBOND_W83627HF
help
- ADL MSM800SEV board
+ Advanced Digital Logic MSM800SEV mainboard.
+
endchoice
source "mainboard/adl/msm800sev/Kconfig"
Modified: LinuxBIOSv3/mainboard/adl/msm800sev/Kconfig
===================================================================
--- LinuxBIOSv3/mainboard/adl/msm800sev/Kconfig 2007-06-29 12:40:13 UTC (rev 410)
+++ LinuxBIOSv3/mainboard/adl/msm800sev/Kconfig 2007-06-29 13:28:33 UTC (rev 411)
@@ -24,22 +24,21 @@
default adl/msm800sev
depends BOARD_ADL_MSM800SEV
help
- This is the name for the ADL MSM800SEV
+ This is the name for the Advanced Digital Logic MSM800SEV mainboard.
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
+ # TODO: Fix the PCI ID.
default 0x1022
depends BOARD_ADL_MSM800SEV
help
- Mainboard specific PCI subsystem vendor ID -- it's wrong.
+ Mainboard specific PCI subsystem vendor ID.
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
+ # TODO: Fix the PCI ID.
default 0x2323
- depends ADL_MSM800SEV
+ depends BOARD_ADL_MSM800SEV
help
- Mainboard specific PCI subsystem vendor ID -- it's wrong.
+ Mainboard specific PCI subsystem vendor ID.
-
-
-
Modified: LinuxBIOSv3/mainboard/amd/Kconfig
===================================================================
--- LinuxBIOSv3/mainboard/amd/Kconfig 2007-06-29 12:40:13 UTC (rev 410)
+++ LinuxBIOSv3/mainboard/amd/Kconfig 2007-06-29 13:28:33 UTC (rev 411)
@@ -31,7 +31,8 @@
select NORTHBRIDGE_AMD_GEODELX
select SOUTHBRIDGE_AMD_CS5536
help
- AMD Norwich Geode LX Development board
+ AMD Norwich Geode LX development board.
+
endchoice
source "mainboard/amd/norwich/Kconfig"
Modified: LinuxBIOSv3/mainboard/amd/norwich/Kconfig
===================================================================
--- LinuxBIOSv3/mainboard/amd/norwich/Kconfig 2007-06-29 12:40:13 UTC (rev 410)
+++ LinuxBIOSv3/mainboard/amd/norwich/Kconfig 2007-06-29 13:28:33 UTC (rev 411)
@@ -28,6 +28,7 @@
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
+ # TODO: Fix PCI ID.
default 0x1022
depends BOARD_AMD_NORWICH
help
@@ -35,11 +36,9 @@
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
+ # TODO: Fix PCI ID.
default 0x2323
depends BOARD_AMD_NORWICH
help
Mainboard specific PCI subsystem device ID.
-
-
-
Modified: LinuxBIOSv3/mainboard/artecgroup/Kconfig
===================================================================
--- LinuxBIOSv3/mainboard/artecgroup/Kconfig 2007-06-29 12:40:13 UTC (rev 410)
+++ LinuxBIOSv3/mainboard/artecgroup/Kconfig 2007-06-29 13:28:33 UTC (rev 411)
@@ -24,14 +24,15 @@
depends on VENDOR_ARTECGROUP
config BOARD_ARTECGROUP_DBE61
- bool "dbe61"
+ bool "DBE61"
select ARCH_X86
select CPU_AMD_GEODELX
select OPTION_TABLE
select NORTHBRIDGE_AMD_GEODELX
select SOUTHBRIDGE_AMD_CS5536
help
- Artec Group DBE61, also known as Linutop
+ Artec Group DBE61, also known as ThinCan and Linutop.
+
endchoice
source "mainboard/artecgroup/dbe61/Kconfig"
Modified: LinuxBIOSv3/mainboard/artecgroup/dbe61/Kconfig
===================================================================
--- LinuxBIOSv3/mainboard/artecgroup/dbe61/Kconfig 2007-06-29 12:40:13 UTC (rev 410)
+++ LinuxBIOSv3/mainboard/artecgroup/dbe61/Kconfig 2007-06-29 13:28:33 UTC (rev 411)
@@ -28,6 +28,7 @@
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
+ # TODO: Fix PCI ID.
default 0x1022
depends BOARD_ARTECGROUP_DBE61
help
@@ -35,11 +36,9 @@
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
+ # TODO: Fix PCI ID.
default 0x2323
depends BOARD_ARTECGROUP_DBE61
help
Mainboard specific PCI subsystem device ID.
-
-
-
Modified: LinuxBIOSv3/northbridge/intel/i440bxemulation/Kconfig
===================================================================
--- LinuxBIOSv3/northbridge/intel/i440bxemulation/Kconfig 2007-06-29 12:40:13 UTC (rev 410)
+++ LinuxBIOSv3/northbridge/intel/i440bxemulation/Kconfig 2007-06-29 13:28:33 UTC (rev 411)
@@ -1,23 +1,23 @@
-##
+##
## This file is part of the LinuxBIOS project.
-##
+##
## Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com>
## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de>
-##
+##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
-##
+##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
-##
+##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
+##
config NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE
int
Hi all,
I have read cs5536 databook carefully, but still puzzled about how
the pci configure space of various functions show up?
Is it the config in southbridge/amd/cs5536/cs5536.c makes it?
/* Master Configuration Register for Bus Masters.*/
struct msrinit SB_MASTER_CONF_TABLE[] = {
{USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}},
{ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000}},
{AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}},
{MDD_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00000f000}},
{0, {0, 0}}
};
Songmao
On Thu, Jun 28, 2007 at 06:21:38PM +0200, svn(a)openbios.org wrote:
> mainboard-vendor = "AMD";
> mainboard-part-number = "Norwich";
Wouldn't
mainboard-name = "Norwich";
make more sense? It's not really a part number, it's a name.
> }
>
> statictree.h will have:
> extern const char *mainboard_vendor, *mainboard_part_number;
>
> and statictree.c will have:
> const char *mainboard_vendor = "AMD";
> const char *mainboard_part_number = "Norwich";
>
> It is an error to NOT have the vendor and part number in the top
> level dts.
Great! Needs to be documentated somewhere, though.
> Modified: LinuxBIOSv3/mainboard/Kconfig
> ===================================================================
> --- LinuxBIOSv3/mainboard/Kconfig 2007-06-28 15:19:30 UTC (rev 393)
> +++ LinuxBIOSv3/mainboard/Kconfig 2007-06-28 16:21:38 UTC (rev 394)
> @@ -38,6 +38,12 @@
> Select this option for various systems from
> Advanced Micro Devices, Inc
>
> +config VENDOR_ARTECGROUP
> + bool "Artec Group"
> + help
> + Select this option for various systems from
> + the Artec Group
Cosmetic:
Should end with a full stop, as every other sentence, and please write
it into one line (it won't exceed 79 characters, I think).
> +choice
> + prompt "Mainboard model"
> + depends on VENDOR_ARTECGROUP
> +
> +config BOARD_ARTECGROUP_DBE61
> + bool "dbe61"
Should be "DBE61" as it's the user-visible name in menuconfig.
> +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
> + hex
> + default 0x1022
> + depends BOARD_ARTECGROUP_DBE61
> + help
> + Mainboard specific PCI subsystem vendor ID.
> +
> +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
> + hex
> + default 0x2323
> + depends BOARD_ARTECGROUP_DBE61
> + help
> + Mainboard specific PCI subsystem device ID.
Are the subsystem IDs correct for this board or copy+pasted?
> +$(obj)/linuxbios.vpd:
> + $(Q)printf " BUILD DUMMY VPD\n"
> + $(Q)dd if=/dev/zero of=$(obj)/linuxbios.vpd bs=256 count=1 $(SILENT)
> +
Mainboard-specific? If not it should be in some common Makefile, not in
every single mainboard Makefile.
> Added: LinuxBIOSv3/mainboard/artecgroup/dbe61/cmos.layout
> ===================================================================
> --- LinuxBIOSv3/mainboard/artecgroup/dbe61/cmos.layout (rev 0)
> +++ LinuxBIOSv3/mainboard/artecgroup/dbe61/cmos.layout 2007-06-28 16:21:38 UTC (rev 394)
Missing license header.
> + msr.lo =
> + (6<<28) | // cas_lat
> + (10<<24)| // ref2act
> + (7<<20)| // act2pre
> + (3<<16)| // pre2act
> + (3<<12)| // act2cmd
> + (2<<8)| // act2act
> + (2<<6)| // dplwr
> + (2<<4)| // dplrd
> + (3); // dal
Maybe make the hardcoded values defines which have the name of the
comments to the right?
> Added: LinuxBIOSv3/mainboard/artecgroup/dbe61/irq_tables.c
> ===================================================================
> --- LinuxBIOSv3/mainboard/artecgroup/dbe61/irq_tables.c (rev 0)
> +++ LinuxBIOSv3/mainboard/artecgroup/dbe61/irq_tables.c 2007-06-28 16:21:38 UTC (rev 394)
Missing license header.
> @@ -0,0 +1,60 @@
> +/* This file was generated by getpir.c, do not modify!
> + (but if you do, please run checkpir on it to verify)
> + * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
> + *
> + * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
> +*/
Can we drop this? A link to the documentation should be in the wiki, not
every single file. As far as I understand the getpir output is not
reliable anyway, so we should drop the above note (also from getpir output).
> +
> +#include <arch/pirq_routing.h>
> +
> +#define ID_SLOT_PCI_NET 1 // ThinCan ethernet
> +#define ID_SLOT_PCI_RSVD1 2 // reserved entry 1
> +#define ID_SLOT_PCI_RSVD3 3 // reserved entry 2
> +#define ID_SLOT_PCI_RSVD2 4 // reserved entry 3
> +#define ID_EMBED_PCI 0xff // onboard PCI device
> +
> +// CS5535 PCI INT[A-D] Interrupt Routing lines.
> +#define NO_CONNECT 0 // not used
> +#define CS_PCI_INTA 1 // PCI INTA
> +#define CS_PCI_INTB 2 // PCI INTB
> +#define CS_PCI_INTC 3 // PCI INTC
> +#define CS_PCI_INTD 4 // PCI INTD
> +
> +// IRQ bitmap reference line FEDCBA9876543210
> +// 0000110000100000b
> +#define PCI_IRQ 0xc20 // PCI allowed IRQs here
> +
> +const struct irq_routing_table intel_irq_routing_table =
> +{
> + PIRQ_SIGNATURE, /* u32 signature */
> + PIRQ_VERSION, /* u16 version */
> + 32+16*6, /* there can be total 2 devices on the bus */
^ ^
One of them is wrong (2 or 6)
> + /* special for the root. Emit the names for the mainboard vendor and part # */
> + for_each_property(bi->dt, prop) {
> + if (streq(prop->name, "mainboard-vendor")){
> + found_mainboard_vendor = 1;
> + fprintf(f, "const char *mainboard_vendor = \"%s\";\n", prop->val.val);
> + }
> + if (streq(prop->name, "mainboard-part-number")){
> + found_mainboard_partnumber = 1;
> + fprintf(f, "const char *mainboard_part_number = \"%s\";\n", prop->val.val);
> + }
> + }
> +
> + if (! found_mainboard_vendor){
^^^
Drop the spaces.
> + die("There is no mainboard-vendor property in the root. Please add one."
> + "(and make sure there is a mainboard-part-number property too");
> + }
> +
> + if (! found_mainboard_partnumber){
Ditto
> + die("There is no mainboard-part-number property in the root. "
> + "Please add one."
> + "(and make sure there is a mainboard-vendor property too");
> + }
> +
> +
> /* emit the code, if any */
> if (code)
> fprintf(f, "%s\n", code);
> @@ -1323,6 +1350,7 @@
> fix_next(bi->dt);
> /* emit any includes that we need -- TODO: ONLY ONCE PER TYPE*/
> fprintf(f, "#include <device/device.h>\n#include <device/pci.h>\n");
> + fprintf(f, "extern const char *mainboard_vendor, *mainboard_part_number;\n");
> flatten_tree_emit_includes(bi->dt, &linuxbios_emitter, f, &strbuf, vi);
>
> flatten_tree_emit_structdecls(bi->dt, &linuxbios_emitter, f, &strbuf, vi);
Uwe.
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