coreboot June 2007

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[LinuxBIOS] r2710 - trunk/LinuxBIOSv2/targets/tyan/s1846
by svn＠openbios.org 04 Jun '07

04 Jun '07

Author: uwe Date: 2007-06-04 01:19:19 +0200 (Mon, 04 Jun 2007) New Revision: 2710 Modified: trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb Log: Switch the Tyan S1846 to a fallback-only boot per default to allow bigger payloads (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb =================================================================== --- trunk/LinuxBIOSv2/… [View More]

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[LinuxBIOS] r2709 - trunk/LinuxBIOSv2/src/mainboard/tyan/s1846
by svn＠openbios.org 03 Jun '07

03 Jun '07

Author: uwe Date: 2007-06-03 23:57:55 +0200 (Sun, 03 Jun 2007) New Revision: 2709 Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb Log: Tyan S1846: Minor fixes in static device tree (trivial): - Linux booted with the proprietary BIOS reports 2e.f as PS/2 mouse in the output of 'lspnp -v'. - The floppy on 2e.f was a typo, should have been 2e.e from the beginning. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> … [View More]

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[LinuxBIOS] [PATCH] Tyan S1846: Device tree fixes
by Uwe Hermann 03 Jun '07

03 Jun '07

The static device tree of the Tyan S1846 was, um... totally bogus. I'm using the ide0_enble/ide1_enable variables now to enable IDE. Hm, what happens if those variables are not set at all in a Confib.lb file of some mainboard? Do they default to zero? Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] r2708 - trunk/LinuxBIOSv2/src/mainboard/tyan/s1846
by svn＠openbios.org 03 Jun '07

03 Jun '07

Author: uwe Date: 2007-06-03 22:39:47 +0200 (Sun, 03 Jun 2007) New Revision: 2708 Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb Log: Fix the static device tree of the Tyan S1846. Especially the Super I/O part was incorrect. Also, add ide0_enable/ide1_enable variables, and enable both the primary and secondary IDE interface per default. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/… [View More]LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb 2007-06-03 16:57:27 UTC (rev 2707) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb 2007-06-03 20:39:47 UTC (rev 2708) @@ -125,38 +125,46 @@ dir /pc80 config chip.h -# TODO. -chip northbridge/intel/i440bx # Northbridge - device pci_domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 off end # PCI bridge TODO: AGP bridge? - # device pci 7.0 on end # ISA bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge ??? - chip superio/nsc/pc87309 # Super I/O - device pnp 2e.0 on end # Floppy - device pnp 2e.1 on end # Parallel port - device pnp 2e.2 on end # Com2 - device pnp 2e.3 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 on end # Power mgmt. - device pnp 2e.5 on end # Mouse - device pnp 2e.6 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 # ??? - end - end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI - end - end - end - chip cpu/intel/slot_2 - end +chip northbridge/intel/i440bx # Northbridge + device pci_domain 0 on + device pci 0.0 on end # Host bridge + device pci 1.0 on end # AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/nsc/pc87309 # Super I/O + device pnp 2e.5 on # Keyboard + Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.b on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.c on # Com2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.d on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.f on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end + chip cpu/intel/slot_2 # CPU + end end [View Less]

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[LinuxBIOS] which motherboard would be the better choice
by Mike Dilworth 03 Jun '07

03 Jun '07

hi all I am soon to buy a new motherboard and I have narrowed my choice down to 2. I am very interested in the LinuxBios project and am eager to "have a go". My question is whihc of these two motherbords would be better to use for LinuxBios: MS-7327 K9AGM2-FIH http://global.msi.com.tw/index.php?func=proddesc&maincat_no=1&cat2_no=&cat3… or the Abit AN-M2HD http://www.abit.com.tw/page/uk/motherboard/motherboard_detail.php?pMODEL_NA… as you can tell I need the HDMI feature. … [View More]

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[LinuxBIOS] [PATCH] Lower 440BX RAM init delays
by Uwe Hermann 03 Jun '07

03 Jun '07

See patch. Tested on Tyan S1846, works fine. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] r2707 - trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb
by svn＠openbios.org 03 Jun '07

03 Jun '07

Author: uwe Date: 2007-06-03 18:57:27 +0200 (Sun, 03 Jun 2007) New Revision: 2707 Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_ide.c trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_smbus.c Log: Intel 82371EB: Some code simplifications (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe … [View More]Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h 2007-06-02 23:55:17 UTC (rev 2706) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h 2007-06-03 16:57:27 UTC (rev 2707) @@ -26,7 +26,6 @@ void i82371eb_enable(device_t dev); #endif -#define PCICMD 0x04 /* PCI Command Register */ #define XBCS 0x4e /* X-Bus Chip Select register */ /* SMBus */ Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c 2007-06-02 23:55:17 UTC (rev 2706) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c 2007-06-03 16:57:27 UTC (rev 2707) @@ -49,9 +49,9 @@ pci_write_config8(dev, SMBHSTCFG, reg8); /* Enable access to the SMBus I/O space. */ - reg16 = pci_read_config16(dev, PCICMD); + reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 |= IOSE; - pci_write_config16(dev, PCICMD, reg16); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Clear any lingering errors, so the transaction will run. */ outb(inb(SMBUS_IO_BASE + SMBHST_STATUS), SMBUS_IO_BASE + SMBHST_STATUS); Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_ide.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_ide.c 2007-06-02 23:55:17 UTC (rev 2706) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_ide.c 2007-06-03 16:57:27 UTC (rev 2707) @@ -35,10 +35,8 @@ static void ide_init(struct device *dev) { uint16_t reg; - struct southbridge_intel_i82371eb_config *conf; + struct southbridge_intel_i82371eb_config *conf = dev->chip_info; - conf = dev->chip_info; - /* Enable/disable the primary IDE interface. */ reg = pci_read_config16(dev, IDETIM_PRI); if (conf->ide0_enable) { @@ -62,18 +60,13 @@ pci_write_config16(dev, IDETIM_SEC, reg); } -/* There are no subsystem IDs on the Intel 82371EB. */ -static struct pci_operations lops_pci = { - // .set_subsystem = 0, -}; - static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ide_init, .scan_bus = 0, - .ops_pci = &lops_pci, + .ops_pci = 0, /* No subsystem IDs on 82371EB! */ }; static struct pci_driver ide_driver __pci_driver = { Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_smbus.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_smbus.c 2007-06-02 23:55:17 UTC (rev 2706) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_smbus.c 2007-06-03 16:57:27 UTC (rev 2707) @@ -27,11 +27,6 @@ static struct smbus_bus_operations lops_smbus_bus = { }; -/* There are no subsystem IDs on the Intel 82371EB. */ -static struct pci_operations lops_pci = { - // .set_subsystem = 0, -}; - static struct device_operations smbus_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -39,7 +34,7 @@ .init = 0, .scan_bus = scan_static_bus, // .enable = i82371eb_enable, // TODO: Needed? - .ops_pci = &lops_pci, + .ops_pci = 0, /* No subsystem IDs on 82371EB! */ .ops_smbus_bus = &lops_smbus_bus, }; [View Less]

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[LinuxBIOS] new target iei juki-511p/rocky-512
by Nikolay Petukhov 03 Jun '07

03 Jun '07

Hi, Here's a one patch for IEI JUKI-511P and IEI ROCKY-512 half-size boards. This boards are little difference, that's why it has one patch. Linux with patchs from Juergen Beisert (http://www.linuxbios.org/pipermail/linuxbios/2007-May/020932.html) boots and work fine(ide, usb, ethernet, serial, keyboard and sound work normally). Problems: Filo load bzImage only from ide0. Video don't work, no any monitor output. JUKI-511P – PCISA half–size board: Specification: CPU: Geode GX1 300Mhz System … [View More]

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[LinuxBIOS] r2706 - trunk/LinuxBIOSv2/src/southbridge/amd/cs5536
by svn＠openbios.org 03 Jun '07

03 Jun '07

Author: uwe Date: 2007-06-03 01:55:17 +0200 (Sun, 03 Jun 2007) New Revision: 2706 Modified: trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c Log: The UART disable code was causing a hang and was worked around with a return that skipped the disable code. This patch removes the return and fixes the UART disable code. The problem was that the disable code was ORing bits into the Legacy_IO MSR causing issues with the LPC SIOs init code that would manifest as a hang because the IO would … [View More]

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[LinuxBIOS] [PATCH] v3: Kconfig payload options and README improvements
by Uwe Hermann 03 Jun '07

03 Jun '07

Hi, here's a patch for v3 which reworks the payload selection in 'make menuconfig'. After the patch there are two simple options you can use: - Payload file You specify a path and filename for the payload. Default: payload.elf in the current directory. _How_ you create this payload does not matter; manual building, using a pre-built image from somewhere, using buildrom or lbdistro to create one etc. etc. - No payload This will create an "empty" image without any … [View More]

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coreboot June 2007