coreboot February 2007

coreboot@coreboot.org

68 participants
169 discussions

[LinuxBIOS] ASUS P4R8L
by Erwan Velu 01 Mar '07

01 Mar '07

Hey folks, I attended a linuxbios presentation at FOSDEM 2007. Thanks for the presentation, it give me the opportunity to join your project. I follow this project since a while - I started playing with cluster in 2001. So I'd like to make linuxbios working on my Asus Pundit-R. I asked during the presentation "How to Start when you want to make a new system supported by LinuxBios" I was answered "Please provide us a lspci". Here come my lspci ;) 00:00.0 Host bridge: ATI Technologies Inc Radeon 9100 IGP Host Bridge (rev 02) 00:01.0 PCI bridge: ATI Technologies Inc Radeon 9100 IGP AGP Bridge 00:13.0 USB Controller: ATI Technologies Inc OHCI USB Controller #1 (rev 01) 00:13.1 USB Controller: ATI Technologies Inc OHCI USB Controller #2 (rev 01) 00:13.2 USB Controller: ATI Technologies Inc EHCI USB Controller (rev 01) 00:14.0 SMBus: ATI Technologies Inc ATI SMBus (rev 1a) 00:14.1 IDE interface: ATI Technologies Inc ATI Dual Channel Bus Master PCI IDE Controller 00:14.3 ISA bridge: ATI Technologies Inc Unknown device 434c 00:14.4 PCI bridge: ATI Technologies Inc Unknown device 4342 00:14.5 Multimedia audio controller: ATI Technologies Inc IXP150 AC'97 Audio Controller (rev 01) 01:05.0 VGA compatible controller: ATI Technologies Inc Radeon 9100 IGP 02:08.0 Ethernet controller: 3Com Corporation 3Com 3C920B-EMB-WNM Integrated Fast Ethernet Controller (rev 40) 02:09.0 Ethernet controller: 3Com Corporation 3c905C-TX/TX-M [Tornado] (rev 78) 02:0a.0 FireWire (IEEE 1394): VIA Technologies, Inc. IEEE 1394 Host Controller (rev 80) 02:0c.0 CardBus bridge: ENE Technology Inc CB-710/2/4 Cardbus Controller (rev 02) 02:0c.1 FLASH memory: ENE Technology Inc CB710 Memory Card Reader Controller 02:0e.0 Ethernet controller: Atheros Communications, Inc. AR5212 802.11abg NIC (rev 01) lspci -n: 00:00.0 0600: 1002:5833 (rev 02) 00:01.0 0604: 1002:5838 00:13.0 0c03: 1002:4347 (rev 01) 00:13.1 0c03: 1002:4348 (rev 01) 00:13.2 0c03: 1002:4345 (rev 01) 00:14.0 0c05: 1002:4353 (rev 1a) 00:14.1 0101: 1002:4349 00:14.3 0601: 1002:434c 00:14.4 0604: 1002:4342 00:14.5 0401: 1002:4341 (rev 01) 01:05.0 0300: 1002:5834 02:08.0 0200: 10b7:9202 (rev 40) 02:09.0 0200: 10b7:9200 (rev 78) 02:0a.0 0c00: 1106:3044 (rev 80) 02:0c.0 0607: 1524:1411 (rev 02) 02:0c.1 0501: 1524:0510 02:0e.0 0200: 168c:0013 (rev 01) Regarding the website, this ATI northbridge is not supported. I have a basic knowledge about the way it works, how can I help making this system working ? DMI says this is a P4R8L motherboard from ASUS. Regards,

2 4

Re: [LinuxBIOS] [PATCH] Support for Winbond W83627EHG Super I/O
by Lu, Yinghai 01 Mar '07

01 Mar '07

USB DEBUG port support. YH -----Original Message----- From: linuxbios-bounces(a)linuxbios.org [mailto:linuxbios-bounces@linuxbios.org] On Behalf Of Stefan Reinauer Sent: Saturday, February 03, 2007 7:31 AM To: Uwe Hermann Cc: linuxbios(a)linuxbios.org Subject: Re: [LinuxBIOS] [PATCH] Support for Winbond W83627EHG Super I/O Uwe Hermann wrote: > Add support for the Winbond W83627EHG Super I/O. > > Signed-off-by: Yinghai Lu <yinghai.lu(a)amd.com> > Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> applied. > This is from Yinghai's huge patch. I added missing license headers > (Yinghai please complain if any of them is incorrect!), fixed some > coding style issues and added a few comments. What's still missing from Yinghai's patch now? -- coresystems GmbH * Brahmsstr. 16 * D-79104 Freiburg i. Br. Tel.: +49 761 7668825 * Fax: +49 761 7664613 Email: info(a)coresystems.de * http://www.coresystems.de/ -- linuxbios mailing list linuxbios(a)linuxbios.org http://www.openbios.org/mailman/listinfo/linuxbios

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[LinuxBIOS] Xvesa on LinuxBIOS
by Alan Carvalho de Assis 01 Mar '07

01 Mar '07

Hi Ron, 2007/2/26, ron minnich <rminnich(a)gmail.com>: > Alan, this is an interesting idea. yes, I think it is a good idea too although some friends said me it is a crazy idea :) >I wonder how I would replicate your > setup in order to try to replicate your problem? A way to you replicate this problem is: start LinuxBIOS with video support (from original VGA ROM BIOS), then run kdrive (Xvesa) or even try to start XFree with Driver "vesa" in Device Section of XF86Config or xorg.conf. I am using Tyan s2850 with onboard ATI Rage XL. > I am not sure why > this is happening, UNLESS ... does Xvesa make some assumptions about > the location of tables or information it uses to start up? What does > Xvesa do? The only VESA stuff I know about (in plan 9) might be > dependent on a fixed BIOS location for some things. > The Xvesa assuption is just to find the interrupt vector pointing to some area inside the 0xC000 segment, but I don't figure out it. I am not an X server and kdrive expert, maybe Keith Packard can answer it. Finally I get sucess to start X11 inside LinuxBIOS, I make a work around just "hard coding" the right segment and offset in vm86.c. After I will record a video and place in youtube to others people see it. I hope we can create something like the Phoenix BIOS to read email and browser web. > ron > Best regards, Alan

5 7

Re: [LinuxBIOS] LinuxBIOS and VMWare
by Joe Pub 28 Feb '07

28 Feb '07

Part of my trouble is that when I enable VGA I don't get a boot log, nothing happens, via serial or vga. Config.lb for MB is below, and config.lb for target follows. ------------------ MB config.lb -------------------------- ## ## Compute the location and size of where this firmware image ## (linuxBIOS plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) else default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) default ROM_SECTION_OFFSET = 0 end ## ## Compute the start location and size size of ## The linuxBIOS bootloader. ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) ## ## Compute where this copy of linuxBIOS will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## ## Compute a range of ROM that can cached to speed up linuxBIOS, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE ## default XIP_ROM_SIZE=65536 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) ## ## Set all of the defaults for an x86 architecture ## arch i386 end ## ## Build the objects we have code for in this directory. ## driver mainboard.o if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E depends "$(MAINBOARD)/failover.c ./romcc" action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" end makerule ./failover.inc depends "$(MAINBOARD)/failover.c ./romcc" action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" end makerule ./auto.E depends "$(MAINBOARD)/auto.c option_table.h ./romcc" action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end makerule ./auto.inc depends "$(MAINBOARD)/auto.c option_table.h ./romcc" action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where linuxBIOS is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else mainboardinit cpu/x86/32bit/reset32.inc ldscript /cpu/x86/32bit/reset32.lds end ### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc ## ## Include an id string (For safe flashing) ## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end ### ### O.k. We aren't just an intermediary anymore! ### ## ## Setup RAM ## mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit ./auto.inc mainboardinit arch/i386/llshell/llshell.inc mainboardinit cpu/x86/mmx/disable_mmx.inc ## ## Include the secondary Configuration files ## dir /pc80 config chip.h chip northbridge/intel/i440bx device pci_domain 0 on device pci 0.0 on end # host bridge device pci 1.0 on end # PCI bridge device pci 10.0 on end # SCSI storage controller device pci 11.0 on end # Ethernet controller device pci 12.0 on end # Audio controller device pci f.0 on # VGA controller chip drivers/pci/onboard device pci f.0 on end register "rom_address" = "0xfff80000" end end device pci 7.0 on # ISA bridge end end chip cpu/intel/socket_PGA370 end end -------------------------------------------------- ----------------- config.lb target --------------- # Config file for asus wkst55 board # This will make a target directory of ./wkst55 target wkst55 mainboard vmware/wkst55 option ROM_SIZE=(512*1024)-(32*1024) romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x10000 option LINUXBIOS_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebi payload /etc/hosts end romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 option LINUXBIOS_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebia payload /etc/hosts end buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" ----------------------------------------------------------------------- Regards, Ceri ------------------------------ *From:* Lu, Yinghai [mailto:yinghai.lu@amd.com] *Sent:* 28 February 2007 17:27 *To:* Joe Pub; linuxbios(a)linuxbios.org *Subject:* RE: [LinuxBIOS] LinuxBIOS and VMWare Boot log and your MB Config.lb? YH ------------------------------ *From:* linuxbios-bounces(a)linuxbios.org [mailto: linuxbios-bounces(a)linuxbios.org] *On Behalf Of *Joe Pub *Sent:* Wednesday, February 28, 2007 9:07 AM *To:* linuxbios(a)linuxbios.org *Subject:* [LinuxBIOS] LinuxBIOS and VMWare Hi There, Has anyone had any success with VMWare. I have partially implemented the PC87360 SIO chip which has give me serial and I can boot LinuxBIOS up to the elf payload stage. I'm trying to get the VMWare VGA to work at no avail. Has anyone else has success with this. I have added default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 to the Optionslb file and adjusted the size of the ROM image by -32KB (sizeof VGA BIOS for VMWare) and also added device pci f.0 on # VGA controller chip drivers/pci/onboard device pci f.0 on end register "rom_address" = "0xfff80000" end end to the Config.lb <http://config.lb/>. When I start VMWare with this image though it does nothing but sit there with no VGA. I have even enabled serial logging back on using CONFIG_CONSOLE_SERIAL8250 but still continue to use CONFIG_PCI_ROM_RUN but nothing then even gets written to the serial port. When does the VGA BIOS rom get called, at what stage? Regards, Joe ______________________________________________________________________ This email has been scanned by the MessageLabs Email Security System. For more information please visit http://www.messagelabs.com/email ______________________________________________________________________

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[LinuxBIOS] r2564 build service
by LinuxBIOS information 28 Feb '07

28 Feb '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "stepan" checked in revision 2564 to the LinuxBIOS source repository and caused the following changes: Change Log: Add support for the Gigabyte m57sli-s4 board to flashrom. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of gigabyte:m57sli is still broken Configuration of msi:ms9282 is still broken Compilation of nvidia:l1_2pvv is still broken Compilation of supermicro:h8dmr is still broken Compilation of tyan:s2912 is still broken If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system

1 0

[LinuxBIOS] [PATCH] gigabyte m57sli-s4 support for flashrom
by Ward Vandewege 28 Feb '07

28 Feb '07

Add support for the Gigabyte m57sli-s4 board to flashrom. Signed-off-by: Ward Vandewege <ward(a)gnu.org> --- Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

3 4

[LinuxBIOS] r2564 - trunk/LinuxBIOSv2/util/flashrom
by svn＠openbios.org 28 Feb '07

28 Feb '07

Author: stepan Date: 2007-02-28 22:50:15 +0100 (Wed, 28 Feb 2007) New Revision: 2564 Modified: trunk/LinuxBIOSv2/util/flashrom/flash_enable.c Log: Add support for the Gigabyte m57sli-s4 board to flashrom. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/util/flashrom/flash_enable.c =================================================================== --- trunk/LinuxBIOSv2/util/flashrom/flash_enable.c 2007-02-28 11:17:02 UTC (rev 2563) +++ trunk/LinuxBIOSv2/util/flashrom/flash_enable.c 2007-02-28 21:50:15 UTC (rev 2564) @@ -463,6 +463,7 @@ {0x10de, 0x0262, "NVidia MCP51", enable_flash_ck804}, {0x10de, 0x0263, "NVidia MCP51", enable_flash_ck804}, + {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, // Gigabyte m57sli-s4 {0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, // LPC {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, // Pro

1 0

[LinuxBIOS] [PATCH] Improve ITE IT8716F support.
by Uwe Hermann 28 Feb '07

28 Feb '07

Improve ITE IT8716F support. Signed-off-by: Yinghai Lu <yinghai.lu(a)amd.com> Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> --- This is yet another part of Yinghai's huge patch. I merged and adapted the code, some minor, mostly cosmetic, changes here and there. Some more things are still missing from the huge patch... Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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Re: [LinuxBIOS] LinuxBIOS and VMWare
by Joe Pub 28 Feb '07

28 Feb '07

Ops, typed the wrong super IO chip. I meant I have partially implemented the NSC PC87338, not he PC87360. Regards, Joe

1 0

[LinuxBIOS] LinuxBIOS and VMWare
by Joe Pub 28 Feb '07

28 Feb '07

Hi There, Has anyone had any success with VMWare. I have partially implemented the PC87360 SIO chip which has give me serial and I can boot LinuxBIOS up to the elf payload stage. I'm trying to get the VMWare VGA to work at no avail. Has anyone else has success with this. I have added default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 to the Optionslb file and adjusted the size of the ROM image by -32KB (sizeof VGA BIOS for VMWare) and also added device pci f.0 on # VGA controller chip drivers/pci/onboard device pci f.0 on end register "rom_address" = "0xfff80000" end end to the Config.lb. When I start VMWare with this image though it does nothing but sit there with no VGA. I have even enabled serial logging back on using CONFIG_CONSOLE_SERIAL8250 but still continue to use CONFIG_PCI_ROM_RUN but nothing then even gets written to the serial port. When does the VGA BIOS rom get called, at what stage? Regards, Joe

2 1

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coreboot February 2007