coreboot February 2007

coreboot@coreboot.org

68 participants
169 discussions

[LinuxBIOS] dmidecode and lspci outputs
by Johan Palmqvist 15 Feb '07

15 Feb '07

Here is a zipped attachment with dmidecode, lspci -v, -n and -t output of the following boards: ABit BX6 1.0 ASUS A7V133-C ASUS A7V333 ASUS A7V600 ASUS A7V600-X ASUS K8N ASUS TX97-X ASUS TX97-XE Compaq Presario 4118EA IBM eServer xSeries 220 MSI MS-6119 I can get output from a few more if needed.

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Re: [LinuxBIOS] HT interrupts
by Segher Boessenkool 15 Feb '07

15 Feb '07

> Sorry to spam again but I couldn't figure out this on my own. > Questions: You again replied to an unrelated message instead of starting a new thread too, sigh. > 1. Does LinuxBIOS actually program the HT interrupt definition > registers > based on the interrupt capability and mobo config, or does Linux do > this? Or > is it up to the driver? LinuxBIOS has to do at least some of the configuration. It probably does it all, I didn't check. Linux will at runtime change some settings. Unrelated device drivers do not touch any of this. > 2. What's the recommended way of doing HT interrupt that will work > with both > APIC and 8259? EOI seems to be APIC only (can be turned off in the > interrupt request) and I guess I can't rely on EOI to always be there? I have no idea what your question is. You *have* to do EOI on level triggered interrupts and you *have* to refrain from using it on edge triggered interrupts, or things will go (horribly and/or subtly) wrong. > 3. EOI in a way acts as flow control. So without EOI is it possible > that I > can flood the PIC/APIC with too many interrupt packets? No, only one interrupt packet is sent from the HT APIC over the HT bus; and only one packet (the EOI packet) is sent back. > I suppose the > credit based flow control in HT can take care of this... That doesn't prevent flooding, it just prevents losing packets. Segher

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Re: [LinuxBIOS] HT interrupts
by yhlu 14 Feb '07

14 Feb '07

Eric already added HT int support to Linux kernel from 2.6.19. you could use HT-MSI if you OS doesn't support HT irq directly. YH On 2/14/07, Perry Wang <peilien(a)yahoo.com> wrote: > Hi, > > Sorry to spam again but I couldn't figure out this on my own. Questions: > > 1. Does LinuxBIOS actually program the HT interrupt definition registers > based on the interrupt capability and mobo config, or does Linux do this? Or > is it up to the driver? > > 2. What's the recommended way of doing HT interrupt that will work with both > APIC and 8259? EOI seems to be APIC only (can be turned off in the > interrupt request) and I guess I can't rely on EOI to always be there? > > 3. EOI in a way acts as flow control. So without EOI is it possible that I > can flood the PIC/APIC with too many interrupt packets? I suppose the > credit based flow control in HT can take care of this... > > Thanks again > Perry > > > > -- > linuxbios mailing list > linuxbios(a)linuxbios.org > http://www.openbios.org/mailman/listinfo/linuxbios >

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Re: [LinuxBIOS] Question about PCI Config Space byte rd/wr in HT
by Segher Boessenkool 14 Feb '07

14 Feb '07

[Don't reply to an unrelated post, please start a new thread instead]. > If software tries to do a byte rd/wr access to PCI config access, say > in > linux or BIOS, how would it show up on the HT bus? As a byte access to config space -- what else? Read the HT specification (from hypertransport.org) if you need to know the details. > I'm assuming that config space access is initiated through the > southbridge. It's done on the CPU chip (it detects accesses to legacy I/O address 0xfc8/0xcfc). > Anyone know if an HT device will ever have to expect byte access to its > config space? Yes, some people know. Yes, they have to expect (and allow) byte accesses. Segher

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[LinuxBIOS] is this motherboard supported? VIA EPIA-SP13000
by Pablo Sosa 14 Feb '07

14 Feb '07

Hi there, Hope this is the right forum to ask. I was checking the list of supported motherboards in order to try linuxbios, I could find I can buy one of this motherboards which are similar but not the same to VIA that are mentioned on the page, i.e. VIA EPIA-SP13000 Motherboard, Socket 370Specs according to the vendor are: Specifications: - Processor: VIA C3/ VIA Eden EBGA processor - Chipset: VIA CN400 North Bridge; VIA VT8237 South Bridge - System Memory: 1x DDR266/333/400 DIMM socket supports up to 1GB memory size - VGA: Integrated VIA UniChromePro AGP graphics with MPEG-2 decoder /MPEG-4 Accelerator - Expansion Slots: 1 PCI - Onboard IDE: 2x UltraDMA 133/100 Connector - Onboard Serial ATA: 2 SATA Connectors - Onboard LAN: VIA VT6103 10/100 Base-T Ethernet PHY - Onboard Audio: VIA VT1617A 6channel AC' 97 codec - Onboard TV Out: VIA VT1623 TV Encoder - Onboard 1394: VIA VT6307S IEEE 1394 Firewire On the link that's on the supported motherboards page appears, http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…, and the specs from the manufacturer are: VIA EPIA MII. Chipset VIA CLE266 North Bridge VIA VT8235M South Bridge The North/South bridges in the manufacturer page, are different to the ones in the list of compatible motherboards. specs on the motherboard page are: VIA EPIA-MII VIA VT8623 VIA VT8235, Ricoh RL5C476 VIA VT1211 VIA C3, VIA EDEN Socket 370 OK So I'm a bit confused and wouldn't like to buy something that's unable to support linuxbios, I'll appreciate if someone can help me, or give me some advice Cheers, Pablo Sosa ____________________________________________________________________________________ Cheap talk? Check out Yahoo! Messenger's low PC-to-Phone call rates. http://voice.yahoo.com

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[LinuxBIOS] dmidecode + lspci output.
by Jonas Lihnell 14 Feb '07

14 Feb '07

# dmidecode 2.8 SMBIOS 2.3 present. 25 structures occupying 645 bytes. Table at 0x000F0800. Handle 0x0000, DMI type 1, 25 bytes System Information Manufacturer: Product Name: Version: Serial Number: UUID: Not Present Wake-up Type: Power Switch Handle 0x0001, DMI type 2, 8 bytes Base Board Information Manufacturer: Product Name: CN700-8237R Version: Serial Number: Handle 0x0002, DMI type 3, 17 bytes Chassis Information Manufacturer: Type: Desktop Lock: Not Present Version: Serial Number: Asset Tag: Boot-up State: Unknown Power Supply State: Unknown Thermal State: Unknown Security Status: Unknown OEM Information: 0x00000000 Handle 0x0003, DMI type 4, 35 bytes Processor Information Socket Designation: NanoBGA2 Type: Central Processor Family: Other Manufacturer: VIA ID: A9 06 00 00 FF BB C9 A7 Version: VIA Eden Voltage: 0.8 V External Clock: 100 MHz Max Speed: 2000 MHz Current Speed: 1200 MHz Status: Populated, Enabled Upgrade: None L1 Cache Handle: 0x0006 L2 Cache Handle: 0x0007 L3 Cache Handle: Not Provided Serial Number: Asset Tag: Part Number: Handle 0x0004, DMI type 5, 18 bytes Memory Controller Information Error Detecting Method: None Error Correcting Capabilities: None Supported Interleave: Eight-way Interleave Current Interleave: Four-way Interleave Maximum Memory Module Size: 1024 MB Maximum Total Memory Size: 1024 MB Supported Speeds: 70 ns 60 ns Supported Memory Types: DIMM SDRAM Memory Module Voltage: 2.9 V Associated Memory Slots: 1 0x0005 Enabled Error Correcting Capabilities: None Handle 0x0005, DMI type 6, 12 bytes Memory Module Information Socket Designation: A0 Bank Connections: 0 Current Speed: 37 ns Type: Other Installed Size: 512 MB (Single-bank Connection) Enabled Size: 512 MB (Single-bank Connection) Error Status: OK Handle 0x0006, DMI type 7, 19 bytes Cache Information Socket Designation: Internal Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Write Back Location: Internal Installed Size: 32 KB Maximum Size: 32 KB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Unknown System Type: Unknown Associativity: 4-way Set-associative Handle 0x0007, DMI type 7, 19 bytes Cache Information Socket Designation: Internal Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Write Back Location: External Installed Size: 0 KB Maximum Size: 0 KB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Unknown System Type: Unknown Associativity: Unknown Handle 0x0008, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: PRIMARY IDE Internal Connector Type: On Board IDE External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0009, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: SECONDARY IDE Internal Connector Type: On Board IDE External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x000A, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: FDD Internal Connector Type: On Board Floppy External Reference Designator: Not Specified External Connector Type: None Port Type: 8251 FIFO Compatible Handle 0x000B, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: COM1 Internal Connector Type: 9 Pin Dual Inline (pin 10 cut) External Reference Designator: External Connector Type: DB-9 male Port Type: Serial Port 16450 Compatible Handle 0x000C, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: COM2 Internal Connector Type: 9 Pin Dual Inline (pin 10 cut) External Reference Designator: External Connector Type: DB-9 male Port Type: Serial Port 16450 Compatible Handle 0x000D, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: LPT1 Internal Connector Type: DB-25 female External Reference Designator: External Connector Type: DB-25 female Port Type: Parallel Port ECP/EPP Handle 0x000E, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Keyboard Internal Connector Type: PS/2 External Reference Designator: External Connector Type: PS/2 Port Type: Keyboard Port Handle 0x000F, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: PS/2 Mouse Internal Connector Type: PS/2 External Reference Designator: External Connector Type: PS/2 Port Type: Mouse Port Handle 0x0010, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: USB0 External Connector Type: Other Port Type: USB Handle 0x0011, DMI type 9, 13 bytes System Slot Information Designation: PCI0 Type: 32-bit PCI Current Usage: Available Length: Long ID: 1 Characteristics: 5.0 V is provided PME signal is supported Handle 0x0012, DMI type 13, 22 bytes BIOS Language Information Installable Languages: 3 n|US|iso8859-1 r|CA|iso8859-1 a|JP|unicode Currently Installed Language: n|US|iso8859-1 Handle 0x0013, DMI type 16, 15 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 512 MB Error Information Handle: Not Provided Number Of Devices: 1 Handle 0x0014, DMI type 17, 27 bytes Memory Device Array Handle: 0x0013 Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: 512 MB Form Factor: DIMM Set: None Locator: A0 Bank Locator: Bank0/1 Type: Unknown Type Detail: None Speed: Unknown Manufacturer: None Serial Number: None Asset Tag: None Part Number: None Handle 0x0015, DMI type 19, 15 bytes Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x0001FFFFFFF Range Size: 512 MB Physical Array Handle: 0x0013 Partition Width: 0 Handle 0x0016, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x0001FFFFFFF Range Size: 512 MB Physical Device Handle: 0x0014 Memory Array Mapped Address Handle: 0x0015 Partition Row Position: 1 Handle 0x0017, DMI type 32, 11 bytes System Boot Information Status: No errors detected Handle 0x0018, DMI type 127, 4 bytes End Of Table MiniNix roze # lspci -n 00:00.0 0600: 1106:0314 00:00.1 0600: 1106:1314 00:00.2 0600: 1106:2314 00:00.3 0600: 1106:3208 00:00.4 0600: 1106:4314 00:00.7 0600: 1106:7314 00:01.0 0604: 1106:b198 00:0d.0 0c00: 1106:3044 (rev 80) 00:0e.0 0200: 1106:3119 (rev 11) 00:0f.0 0104: 1106:3149 (rev 80) 00:0f.1 0101: 1106:0571 (rev 06) 00:10.0 0c03: 1106:3038 (rev 81) 00:10.1 0c03: 1106:3038 (rev 81) 00:10.2 0c03: 1106:3038 (rev 81) 00:10.4 0c03: 1106:3104 (rev 86) 00:11.0 0601: 1106:3227 00:11.5 0401: 1106:3059 (rev 60) 01:00.0 0300: 1106:3344 (rev 01) MiniNix roze # lspci -v 00:00.0 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge Subsystem: VIA Technologies, Inc. Unknown device aa08 Flags: bus master, 66MHz, medium devsel, latency 8 Memory at f0000000 (32-bit, prefetchable) [size=64M] Capabilities: [80] AGP version 3.5 Capabilities: [50] Power Management version 2 00:00.1 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge Flags: bus master, medium devsel, latency 0 00:00.2 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge Flags: bus master, medium devsel, latency 0 00:00.3 Host bridge: VIA Technologies, Inc. PT890 Host Bridge Flags: bus master, medium devsel, latency 0 00:00.4 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge Flags: bus master, medium devsel, latency 0 00:00.7 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge Flags: bus master, medium devsel, latency 0 00:01.0 PCI bridge: VIA Technologies, Inc. VT8237 PCI Bridge (prog-if 00 [Normal decode]) Flags: bus master, 66MHz, medium devsel, latency 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000b000-0000bfff Memory behind bridge: fb000000-fcffffff Prefetchable memory behind bridge: f4000000-f7ffffff Capabilities: [70] Power Management version 2 00:0d.0 FireWire (IEEE 1394): VIA Technologies, Inc. IEEE 1394 Host Controller (rev 80) (prog-if 10 [OHCI]) Subsystem: VIA Technologies, Inc. IEEE 1394 Host Controller Flags: bus master, stepping, medium devsel, latency 32, IRQ 17 Memory at fdfff000 (32-bit, non-prefetchable) [size=2K] I/O ports at fc00 [size=128] Capabilities: [50] Power Management version 2 00:0e.0 Ethernet controller: VIA Technologies, Inc. VT6120/VT6121/VT6122 Gigabit Ethernet Adapter (rev 11) Subsystem: VIA Technologies, Inc. Unknown device 0110 Flags: bus master, 66MHz, medium devsel, latency 32, IRQ 18 I/O ports at f800 [size=256] Memory at fdffe000 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 00:0f.0 RAID bus controller: VIA Technologies, Inc. VIA VT6420 SATA RAID Controller (rev 80) Subsystem: VIA Technologies, Inc. VIA VT6420 SATA RAID Controller Flags: bus master, medium devsel, latency 32, IRQ 16 I/O ports at f400 [size=8] I/O ports at f000 [size=4] I/O ports at ec00 [size=8] I/O ports at e800 [size=4] I/O ports at e400 [size=16] I/O ports at e000 [size=256] Capabilities: [c0] Power Management version 2 00:0f.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06) (prog-if 8a [Master SecP PriP]) Subsystem: VIA Technologies, Inc. VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE Flags: bus master, medium devsel, latency 32, IRQ 16 [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [size=8] [virtual] Memory at 000003f0 (type 3, non-prefetchable) [size=1] [virtual] Memory at 00000170 (32-bit, non-prefetchable) [size=8] [virtual] Memory at 00000370 (type 3, non-prefetchable) [size=1] I/O ports at dc00 [size=16] Capabilities: [c0] Power Management version 2 00:10.0 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 81) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller Flags: bus master, medium devsel, latency 32, IRQ 19 I/O ports at d800 [size=32] Capabilities: [80] Power Management version 2 00:10.1 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 81) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller Flags: bus master, medium devsel, latency 32, IRQ 19 I/O ports at d400 [size=32] Capabilities: [80] Power Management version 2 00:10.2 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 81) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller Flags: bus master, medium devsel, latency 32, IRQ 19 I/O ports at d000 [size=32] Capabilities: [80] Power Management version 2 00:10.4 USB Controller: VIA Technologies, Inc. USB 2.0 (rev 86) (prog-if 20 [EHCI]) Subsystem: VIA Technologies, Inc. USB 2.0 Flags: bus master, medium devsel, latency 32, IRQ 19 Memory at fdffd000 (32-bit, non-prefetchable) [size=256] Capabilities: [80] Power Management version 2 00:11.0 ISA bridge: VIA Technologies, Inc. VT8237 ISA bridge [KT600/K8T800/K8T890 South] Subsystem: VIA Technologies, Inc. Unknown device aa08 Flags: bus master, stepping, medium devsel, latency 0 Capabilities: [c0] Power Management version 2 00:11.5 Multimedia audio controller: VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio Controller (rev 60) Subsystem: VIA Technologies, Inc. Unknown device aa08 Flags: medium devsel, IRQ 20 I/O ports at c800 [size=256] Capabilities: [c0] Power Management version 2 01:00.0 VGA compatible controller: VIA Technologies, Inc. UniChrome Pro IGP (rev 01) (prog-if 00 [VGA]) Subsystem: VIA Technologies, Inc. UniChrome Pro IGP Flags: bus master, 66MHz, medium devsel, latency 32, IRQ 21 Memory at f4000000 (32-bit, prefetchable) [size=64M] Memory at fb000000 (32-bit, non-prefetchable) [size=16M] [virtual] Expansion ROM at fc000000 [disabled] [size=64K] Capabilities: [60] Power Management version 2 Capabilities: [70] AGP version 3.0 MiniNix roze # lspci -t -[0000:00]-+-00.0 +-00.1 +-00.2 +-00.3 +-00.4 +-00.7 +-01.0-[0000:01]----00.0 +-0d.0 +-0e.0 +-0f.0 +-0f.1 +-10.0 +-10.1 +-10.2 +-10.4 +-11.0 \-11.5

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[LinuxBIOS] Hardware Info from me...
by Andreas Treppe 13 Feb '07

13 Feb '07

The included files ar in plain text... Hope this is useful info

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[LinuxBIOS] [PATCH] MSI ms9282 LinuxBIOS support
by bxshi＠msik.com.cn 13 Feb '07

13 Feb '07

Dear all, This patch is for MSI K9ND Master Series (ms9282) LinuxBIOS support. Thanks very much for Yinghai's great work for MCP55. Sign-off-by: Bingxun Shi <bingxunshi(a)gmail.com> Description for 9282 Cpu : AMD socket F Memory: DDR2 16 DIMMS Chipset: nVidia MCP55 Detailed information , http://cweb.msi.com.tw/program/products/server/svr/pro_svr_detail.php?UID=6… Index: src/mainboard/msi/ms9282/Config.lb =================================================================== --- src/mainboard/msi/ms9282/Config.lb (revision 0) +++ src/mainboard/msi/ms9282/Config.lb (revision 0) @@ -0,0 +1,418 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2006 AMD +## Written by Yinghai Lu <yinghailu(a)gmail.com> for AMD. +## +## Copyright (C) 2006 MSI +## Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default CONFIG_ROM_PAYLOAD = 1 + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +arch i386 end + + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +#dir /drivers/ati/ragexl +#needed by irq_tables and mptable and acpi_tables +object get_bus_conf.o + + +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE object irq_tables.o end +#object reset.o + +if USE_DCACHE_RAM + +if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +end + +else + +makerule ./auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" +end + +end +else + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + + +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds +end + +mainboardinit cpu/x86/32bit/entry32.inc + +if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end +end + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +if USE_DCACHE_RAM +else +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc +end + +## +## Include an id string (For safe flashing) +## +mainboardinit southbridge/nvidia/mcp55/id.inc +ldscript /southbridge/nvidia/mcp55/id.lds + +## +## ROMSTRAP table for MCP55 +## +if USE_FALLBACK_IMAGE + mainboardinit southbridge/nvidia/mcp55/romstrap.inc + ldscript /southbridge/nvidia/mcp55/romstrap.lds +end + +if USE_DCACHE_RAM +## +## Setup Cache-As-Ram +## +mainboardinit cpu/amd/car/cache_as_ram.inc +end + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE +if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds +else + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +if USE_DCACHE_RAM + +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc +end + +else +# ROMCC +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit cpu/x86/sse/enable_sse.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/sse/disable_sse.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +end + +## +## Include the secondary Configuration files +## +if CONFIG_CHIP_NAME + config chip.h +end + + +# sample config for msi/ms9282 +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F + device apic 0 on end + end + end + + device pci_domain 0 on + chip northbridge/amd/amdk8 #mc0 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/mcp55 + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SERIAL_FALSH + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO2_GPIO3_GPIO4_GPIO5 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/i2c/i2cmux2 # pca9554 smbus mux + device i2c 70 on #0 pca9554 1 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 0-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 57 on end + end + end + device i2c 70 on #0 pca9554 2 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 0-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 57 on end + end + end + end + end + device pci 1.1 on # SM 1 + chip drivers/i2c/i2cmux2 # pca9554 smbus mux + device i2c 72 on #pca9554 channle1 + chip drivers/i2c/adm1027 #HWM ADT7476 1 + device i2c 2e on end + end + end + device i2c 72 on #pca9545 channel 2 + chip drivers/i2c/adm1027 #HWM ADT7463 + device i2c 2e on end + end + end + device i2c 72 on end #pca9545 channel 3 + device i2c 72 on #pca9545 channel 4 + chip drivers/i2c/adm1027 #HWM ADT7476 2 + device i2c 2e on end + end + end + end + end + + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on #P2P + chip drivers/pci/onboard + device pci 4.0 on end + register "rom_address" = "0xfff80000" + end + end # P2P + device pci 7.0 on end # reserve + device pci 8.0 on end # MAC0 + device pci 9.0 on end # MAC1 + device pci a.0 on + device pci 0.0 on + chip drivers/pci/onboard + device pci 4.0 on end #pci_E lan1 + device pci 4.1 on end #pci_E lan2 + end + end + end # 0x376 + device pci b.0 on end # PCI E 0x374 + device pci c.0 on end + device pci d.0 on #SAS + chip drivers/pci/onboard + device pci 0.0 on end + end + end # PCI E 1 0x378 + device pci e.0 on end # PCI E 0 0x375 + device pci f.0 on end #PCI E 0x377 pci_E slot + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end + end # device pci 18.0 + device pci 18.0 on end # Link 1 + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #mc0 + + end # pci_domain + +# chip drivers/generic/debug +# device pnp 0.0 off end +# device pnp 0.1 off end +# device pnp 0.2 off end +# device pnp 0.3 off end +# device pnp 0.4 off end +# device pnp 0.5 on end +# end +end # root_complex Index: src/mainboard/msi/ms9282/mptable.c =================================================================== --- src/mainboard/msi/ms9282/mptable.c (revision 0) +++ src/mainboard/msi/ms9282/mptable.c (revision 0) @@ -0,0 +1,171 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * Copyright (C) 2006 MSI + * Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> + +#include <cpu/amd/amdk8_sysconf.h> + +#include "mb_sysconf.h" + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "MSI "; + static const char productid[12] = "MS9282 "; + struct mp_config_table *mc; + struct mb_sysconf_t *m; + unsigned sbdn; + + int i,j; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + get_bus_conf(); + sbdn = sysconf.sbdn; + m = sysconf.mb; + +/*Bus: Bus ID Type*/ + /* define bus and isa numbers */ + for(j= 0; j < 256 ; j++) { + if(m->bus_type[j]) + smp_write_bus(mc, j, "PCI "); + } + smp_write_bus(mc, m->bus_isa, "ISA "); + +/*I/O APICs: APIC ID Version State Address*/ + { + device_t dev; + struct resource *res; + uint32_t dword; + + dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_1); + if (res) { + smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base); + } + + dword = 0x43c6c643; + pci_write_config32(dev, 0x7c, dword); + + dword = 0x81001a00; + pci_write_config32(dev, 0x80, dword); + + dword = 0xd00002d2; + pci_write_config32(dev, 0x84, dword); + + } + + + } + + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_mcp55, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_mcp55, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_mcp55, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_mcp55, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_mcp55, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_mcp55, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_mcp55, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf); + +//SMBUS + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); + +//USB1.1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 + +//USB2.0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23 + +//SATA1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20 + +//SATA2 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23 + +//SATA3 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21 + +//NIC1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 +//NIC2 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 + + for(j=7; j>=2; j--) { + if(!m->bus_mcp55[j]) continue; + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + } + } + + for(j=0; j<1; j++) + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); + } + +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} Index: src/mainboard/msi/ms9282/irq_tables.c =================================================================== --- src/mainboard/msi/ms9282/irq_tables.c (revision 0) +++ src/mainboard/msi/ms9282/irq_tables.c (revision 0) @@ -0,0 +1,130 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * Copyright (C) 2006 MSI + * Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +#include <cpu/amd/amdk8_sysconf.h> +#include "mb_sysconf.h" + +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, + uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, + uint8_t slot, uint8_t rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + unsigned slot_num; + uint8_t *v; + struct mb_sysconf_t *m; + unsigned sbdn; + + uint8_t sum=0; + int i; + + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + sbdn = sysconf.sbdn; + m = sysconf.mb; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk_info("Writing IRQ routing tables to 0x%x...", addr); + + pirq = (void *)(addr); + v = (uint8_t *)(addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = m->bus_mcp55[0]; + pirq->rtr_devfn = ((sbdn+6)<<3)|0; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x10de; + pirq->rtr_device = 0x0370; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *) ( &pirq->checksum + 1); + slot_num = 0; +//pci bridge + write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + + for(i=1; i< sysconf.hc_possible_num; i++) { + if(!(sysconf.pci1234[i] & 0x1) ) continue; + unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; + unsigned devn = sysconf.hcdn[i] & 0xff; + + write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + } + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk_info("done.\n"); + + return (unsigned long) pirq_info; + +} Index: src/mainboard/msi/ms9282/resourcemap.c =================================================================== --- src/mainboard/msi/ms9282/resourcemap.c (revision 0) +++ src/mainboard/msi/ms9282/resourcemap.c (revision 0) @@ -0,0 +1,299 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2003 Stefan Reinauer <stepan(a)coresystems.de> + * + * Copyright (C) 2006 AMD + * Written by Yinghai Lu <yinghailu(a)gmail.com> for AMD. + * + * Copyright (C) 2006 MSI + * Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * MSI ms9282 needs a different resource map + * + */ + +static void setup_ms9282_resource_map(void) +{ + static const unsigned int register_values[] = { +#if 1 + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, +#endif +#if 1 + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, +// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, +// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, +#endif +#if 1 + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, + PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, +#endif + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration region i + */ +#if 1 +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, +// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, + PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, +#endif + + }; + + int max; + max = sizeof(register_values)/sizeof(register_values[0]); + setup_resource_map(register_values, max); +} + Index: src/mainboard/msi/ms9282/Options.lb =================================================================== --- src/mainboard/msi/ms9282/Options.lb (revision 0) +++ src/mainboard/msi/ms9282/Options.lb (revision 0) @@ -0,0 +1,309 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2006 AMD +## Written by Yinghai Lu <yinghailu(a)gmail.com> for AMD. +## +## Copyright (C) 2006 MSI +## Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses IRQ_SLOT_COUNT +uses HAVE_OPTION_TABLE +uses CONFIG_MAX_CPUS +uses CONFIG_MAX_PHYSICAL_CPUS +uses CONFIG_LOGICAL_CPUS +uses CONFIG_IOAPIC +uses CONFIG_SMP +uses FALLBACK_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD +uses CONFIG_ROM_PAYLOAD_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses STACK_SIZE +uses HEAP_SIZE +uses USE_OPTION_TABLE +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses MAINBOARD +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses LINUXBIOS_EXTRA_VERSION +uses _RAMBASE +uses CONFIG_GDB_STUB +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_SERIAL8250 +uses HAVE_INIT_TIMER +uses CONFIG_GDB_STUB +uses CONFIG_CHIP_NAME +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +#bx_b001- uses K8_HW_MEM_HOLE_SIZEK +uses K8_HT_FREQ_1G_SUPPORT + +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE +uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_USE_INIT + +uses ENABLE_APIC_EXT_ID +uses APIC_ID_OFFSET +uses LIFT_BSP_APIC_ID + +uses HT_CHAIN_UNITID_BASE +uses HT_CHAIN_END_UNITID_BASE +#bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +#bx_b005+ +uses SB_HT_CHAIN_ON_BUS0 + +## ROM_SIZE is the size of boot ROM that this board will use. +#512K bytes +default ROM_SIZE=524288 + +#1M bytes +#bx- default ROM_SIZE=1048576 + +## +## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## +#default FALLBACK_SIZE=131072 +#256K +default FALLBACK_SIZE=0x40000 + +### +### Build options +### + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=11 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default HAVE_MP_TABLE=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=1 + +## +## Move the default LinuxBIOS cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=4 +default CONFIG_MAX_PHYSICAL_CPUS=2 +default CONFIG_LOGICAL_CPUS=1 + +#CHIP_NAME ? +#default CONFIG_CHIP_NAME=1 + +#1G memory hole +#bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000 + +#Opteron K8 1G HT Support +default K8_HT_FREQ_1G_SUPPORT=1 + +##HT Unit ID offset, default is 1, the typical one +default HT_CHAIN_UNITID_BASE=0x0 + +##real SB Unit ID, default is 0x20, mean dont touch it at last +#default HT_CHAIN_END_UNITID_BASE=0x0 + +#make the SB HT chain on bus 0, default is not (0) +#bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2 + +##bx_b005+ make the SB HT chain on bus 0 +default SB_HT_CHAIN_ON_BUS0=1 + +##only offset for SB chain?, default is yes(1) +default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 + +#VGA +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xcc000 +default DCACHE_RAM_SIZE=0x4000 +default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_INIT=0 + +default ENABLE_APIC_EXT_ID=1 +default APIC_ID_OFFSET=0x10 +default LIFT_BSP_APIC_ID=0 + + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default MAINBOARD_PART_NUMBER="ms9282" +default MAINBOARD_VENDOR="MSI" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE + +## +## LinuxBIOS C code runs at this location in RAM +## +default _RAMBASE=0x00004000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_PAYLOAD = 1 + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +## +## Select power on after power fail setting +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +### End Options.lb +end Index: src/mainboard/msi/ms9282/failover.c =================================================================== --- src/mainboard/msi/ms9282/failover.c (revision 0) +++ src/mainboard/msi/ms9282/failover.c (revision 0) @@ -0,0 +1,114 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * Copyright (C) 2006 MSI + * Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "pc80/mc146818rtc_early.c" + +#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "northbridge/amd/amdk8/reset_test.c" + +static void sio_setup(void) +{ + + unsigned value; + uint32_t dword; + uint8_t byte; + + byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword |= (1<<0); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); + + +} + +#if CONFIG_LOGICAL_CPUS==1 +#include "cpu/amd/dualcore/dualcore_id.c" +#endif + +static unsigned long main(unsigned long bist) +{ + /* Make cerain my local apic is useable */ + enable_lapic(); + + /* Is this a cpu only reset? */ + if (early_mtrr_init_detected()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto fallback_image; + } + } + + /* Is this a secondary cpu? */ + if (!boot_cpu()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto fallback_image; + } + } + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the mcp55 */ + mcp55_enable_rom(); + + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal()) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} Index: src/mainboard/msi/ms9282/mb_sysconf.h =================================================================== --- src/mainboard/msi/ms9282/mb_sysconf.h (revision 0) +++ src/mainboard/msi/ms9282/mb_sysconf.h (revision 0) @@ -0,0 +1,38 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * Copyright (C) 2006 MSI + * Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MB_SYSCONF_H + +#define MB_SYSCONF_H + +struct mb_sysconf_t { + unsigned char bus_isa; + unsigned char bus_mcp55[8]; //1 + unsigned apicid_mcp55; + unsigned bus_type[256]; + +}; + +#endif + Index: src/mainboard/msi/ms9282/chip.h =================================================================== --- src/mainboard/msi/ms9282/chip.h (revision 0) +++ src/mainboard/msi/ms9282/chip.h (revision 0) @@ -0,0 +1,27 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 MSI + * Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_msi_ms9282_ops; + +struct mainboard_msi_ms9282_config { + int fixup_scsi; + int fixup_vga; +}; Index: src/mainboard/msi/ms9282/cmos.layout =================================================================== --- src/mainboard/msi/ms9282/cmos.layout (revision 0) +++ src/mainboard/msi/ms9282/cmos.layout (revision 0) @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 dual_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + Index: src/mainboard/msi/ms9282/mainboard.c =================================================================== --- src/mainboard/msi/ms9282/mainboard.c (revision 0) +++ src/mainboard/msi/ms9282/mainboard.c (revision 0) @@ -0,0 +1,33 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 MSI + * Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "chip.h" + +#if CONFIG_CHIP_NAME == 1 +struct chip_operations mainboard_tyan_ms9282_ops = { + CHIP_NAME("MSI ms9282 mainboard") +}; +#endif Index: src/mainboard/msi/ms9282/get_bus_conf.c =================================================================== --- src/mainboard/msi/ms9282/get_bus_conf.c (revision 0) +++ src/mainboard/msi/ms9282/get_bus_conf.c (revision 0) @@ -0,0 +1,168 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * Copyright (C) 2006 MSI + * Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#if CONFIG_LOGICAL_CPUS==1 +#include <cpu/amd/dualcore.h> +#endif + +#include <cpu/amd/amdk8_sysconf.h> + +#include "mb_sysconf.h" + +// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +struct mb_sysconf_t mb_sysconf; + +unsigned pci1234x[] = +{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, + 0x0000ff0, + 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 +}; +unsigned hcdnx[] = +{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + 0x20202020, + 0x20202020, + 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +}; + + +extern void get_sblk_pci1234(void); + +static unsigned get_bus_conf_done = 0; + +static unsigned get_hcid(unsigned i) +{ + unsigned id = 0; + + unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; + + unsigned devn = sysconf.hcdn[i] & 0xff; + + device_t dev; + + dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); + + switch (dev->device) { + case 0x0369: //IO55 + id = 4; + break; + } + + // we may need more way to find out hcid: subsystem id? GPIO read ? + + // we need use id for 1. bus num, 2. mptable, 3. acpi table + + return id; +} + +void get_bus_conf(void) +{ + + unsigned apicid_base; + struct mb_sysconf_t *m; + + device_t dev; + int i, j; + + if(get_bus_conf_done==1) return; //do it only once + + get_bus_conf_done = 1; + + sysconf.mb = &mb_sysconf; + + m = sysconf.mb; + memset(m, 0, sizeof(struct mb_sysconf_t)); + + sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + for(i=0;i<sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_sblk_pci1234(); + + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + + m->bus_type[0] = 1; //pci + + m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff; + + /* MCP55 */ + dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0)); + if (dev) { + m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); + } + + for(i=2; i<8;i++) { + dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); + if (dev) { + m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 ); + } + } + + for(i=0; i< sysconf.hc_possible_num; i++) { + if(!(sysconf.pci1234[i] & 0x1) ) continue; + + unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; + unsigned busn_max = (sysconf.pci1234[i] >> 24) & 0xff; + for (j = busn; j <= busn_max; j++) + m->bus_type[j] = 1; + if(m->bus_isa <= busn_max) + m->bus_isa = busn_max + 1; + printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa); + } + + + +/*I/O APICs: APIC ID Version State Address*/ +#if CONFIG_LOGICAL_CPUS==1 + apicid_base = get_apicid_base(1); +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#endif + m->apicid_mcp55 = apicid_base+0; + +} Index: src/mainboard/msi/ms9282/cache_as_ram_auto.c =================================================================== --- src/mainboard/msi/ms9282/cache_as_ram_auto.c (revision 0) +++ src/mainboard/msi/ms9282/cache_as_ram_auto.c (revision 0) @@ -0,0 +1,296 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * Copyright (C) 2006 MSI + * Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 +#define __ROMCC__ + +#define RAMINIT_SYSINFO 1 +#define CACHE_AS_RAM_ADDRESS_DEBUG 0 + +#define SET_NB_CFG_54 1 + +//used by raminit +#define QRANK_DIMM_SUPPORT 1 + +//used by init_cpus and fidvid +#define K8_SET_FIDVID 1 +//if we want to wait for core1 done before DQS training, set it to 0 +#define K8_SET_FIDVID_CORE0_ONLY 1 + +#define DEBUG_SMBUS 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" + +#include <cpu/amd/model_fxx_rev.h> +#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" + +#if CONFIG_USE_INIT == 0 + #include "lib/memcpy.c" +#endif + +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" + +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" + +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC) + +#include <device/pci_ids.h> +#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" +static void memreset_setup(void) +{ +} + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ +#define SMBUS_SWITCH1 0x70 +#define SMBUS_SWITCH2 0x72 + unsigned device=(ctrl->channel0[0])>>8; + smbus_send_byte(SMBUS_SWITCH1, device); + smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); +} + +#if 0 +static inline void change_i2c_mux(unsigned device) +{ +#define SMBUS_SWITCH1 0x70 +#define SMBUS_SWITHC2 0x72 + smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); + smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); +} +#endif + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +//#define K8_4RANK_DIMM_SUPPORT 1 + +#include "northbridge/amd/amdk8/amdk8_f.h" +#include "northbridge/amd/amdk8/raminit_f.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "sdram/generic_sdram.c" + + /* msi does not want the default */ +#include "resourcemap.c" +#include "cpu/amd/dualcore/dualcore.c" + +#define MCP55_NUM 1 +#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" +//set GPIO to input mode +#define MCP55_MB_SETUP \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \ + +#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" + +#include "cpu/amd/car/copy_and_run.c" + +#include "cpu/amd/car/post_cache_as_ram.c" + +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" + +#if USE_FALLBACK_IMAGE == 1 + +#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" + + +static void sio_setup(void) +{ + + unsigned value; + uint32_t dword; + uint8_t byte; + + byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword |= (1<<0); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); + + +} +void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) +{ + unsigned last_boot_normal_x = last_boot_normal(); + + /* Is this a cpu only reset? or Is this a secondary cpu? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal_x) { + goto normal_image; + } else { + goto fallback_image; + } + } + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the mcp55 */ + mcp55_enable_rom(); + + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal_x) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist), "b"(cpu_init_detectedx) /* inputs */ + ); + + fallback_image: + ; +} +#endif + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx); + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + +#if USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); +#endif + real_main(bist, cpu_init_detectedx); + +} + +//CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1. +#define RC0 (2<<8) +#define RC1 (1<<8) + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr [] = { + RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6, + RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6, + RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7, +#endif + }; + + unsigned bsp_apicid = 0; + int needs_reset; + struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + char *p ; + + if (bist == 0) { + //init_cpus(cpu_init_detectedx); + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + } + + w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + setup_ms9282_resource_map(); + + setup_coherent_ht_domain(); + + wait_all_core0_started(); + +#if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched + start_other_cores(); + //wait_all_other_cores_started(bsp_apicid); +#endif + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + + needs_reset = optimize_link_coherent_ht(); + + needs_reset |= optimize_link_incoherent_ht(sysinfo); + + needs_reset |= mcp55_early_setup_x(); + + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } + + //It's the time to set ctrl now; + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + +#if 0 + int i; + for(i=4;i<8;i++) { + change_i2c_mux(i); + dump_smbus_registers(); + } +#endif + + memreset_setup(); + + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + + post_cache_as_ram(); + +} Index: targets/msi/ms9282/Config.lb =================================================================== --- targets/msi/ms9282/Config.lb (revision 0) +++ targets/msi/ms9282/Config.lb (revision 0) @@ -0,0 +1,91 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2006 MSI +## Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target ms9282 +mainboard msi/ms9282 + +romimage "normal" +# 48K for SCSI FW +# option ROM_SIZE = 475136 + option ROM_SIZE = 512*1024-36*1024 +# option ROM_SIZE = 524288 +# 48K for SCSI FW and 48K for ATI ROM +# option ROM_SIZE = 425984 +# 64K for Etherboot +# option ROM_SIZE = 458752 + option USE_FALLBACK_IMAGE=0 +# option ROM_IMAGE_SIZE=0x13800 +# option ROM_IMAGE_SIZE=0x18800 + option ROM_IMAGE_SIZE=0x20000 +# option ROM_IMAGE_SIZE=0x15800 + option XIP_ROM_SIZE=0x40000 + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" +# payload ../../../payloads/tg3--ide_disk.zelf +# payload ../../../payloads/filo.elf +# payload ../../../payloads/filo_mem.elf +# payload ../../../payloads/filo.zelf +# payload ../../../payloads/tg3--filo_hda2.zelf +# payload ../../../payloads/tg3.zelf +# payload ../../../../payloads/tg3_vga.zelf +# payload /filo.elf + payload /tg3--filo.elf +# payload /payload +# payload ../../../../payloads/e1000_vga.zelf +# payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf +# payload ../../../payloads/tg3_com2.zelf +# payload ../../../payloads/e1000--filo.zelf +# payload ../../../payloads/tg3--e1000--filo.zelf +# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf +# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf +# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 +# option ROM_IMAGE_SIZE=0x13800 +# option ROM_IMAGE_SIZE=0x19800 + option ROM_IMAGE_SIZE=0x20000 +# option ROM_IMAGE_SIZE=0x15800 + option XIP_ROM_SIZE=0x40000 + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" +# payload ../../../payloads/tg3--ide_disk.zelf +# payload ../../../payloads/filo.elf +# payload ../../../payloads/filo_mem.elf +# payload ../../../payloads/filo.zelf +# payload ../../../payloads/tg3--filo_hda2.zelf +# payload ../../../payloads/tg3.zelf +# payload ../../../../payloads/tg3_vga.zelf +# payload ../../../../payloads/memtest +# payload ../../../../payloads/e1000_vga.zelf +# payload ../../../../payloads/filo_hda.zelf +# payload /filo.elf + payload /tg3--filo.elf +# payload /payload +# payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf +# payload ../../../payloads/tg3_com2.zelf +# payload ../../../payloads/e1000--filo.zelf +# payload ../../../payloads/tg3--e1000--filo.zelf +# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf +# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf +# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf +end + +buildrom ./ms9282.lxb ROM_SIZE "normal" "fallback" *****CONFIDENTIAL INFORMATION***** This email is intended only for the use of the person or entity to whom it is addressed and contains information that may be subject to and/or may be restricted from disclosure by contract or applicable law. If you are not the intended recipient of this email, be advised that any disclosure, copy, distribution or use of the contents of this message is strictly prohibited. If you are not the intended recipient of this email, please notify the sender that you have received this in error by replying to this message. Then, please delete it from your system. Thank you.

6 8

Re: [LinuxBIOS] A (likely rather stupid) question on Via docs
by Corey Osgood 11 Feb '07

11 Feb '07

ron minnich wrote: > On 2/11/07, Corey Osgood <corey_osgood(a)verizon.net> wrote: >> Hi all, >> So, I'm working on the vt694x and getting rather frustrated, and so I >> popped open the docs from rom.by, and this caught my eye: >> >> | 1.0 | 9/8/99 | Final document release with "NDA Required" removed |DH| >> >> Does this mean that there shouldn't be any issue with using these docs? >> That would make life so much easier. > > how did you get them? How did rom.by get them? I honestly don't know how rom.by got them, I found them through a heck of a lot of searching. rom.by is mainly a site for people who hack original bioses, it went under for a while due to lack of interest but is now back up. I've looked through a few of the other via ones, and some are watermarked as "Confidential - NDA Required", but they're also very early versions (0.1, etc) of the datasheets. They're all listed here: http://www.rom.by/doki.htm. > on the face of it, however, that comment would seem to mean that there > is no issue. Thanks for the clarification, that was my thought too, but I didn't want to submit any code and get burned at the stake later on for using anything that might create legal issues. The other watermarked docs seem to confirm that this is a public document, just not widely available. -Corey PS: Forgot to send this to the mailing list, oops

1 0

[LinuxBIOS] A (likely rather stupid) question on Via docs
by Corey Osgood 11 Feb '07

11 Feb '07

Hi all, So, I'm working on the vt694x and getting rather frustrated, and so I popped open the docs from rom.by, and this caught my eye: | 1.0 | 9/8/99 | Final document release with “NDA Required” removed |DH| Does this mean that there shouldn't be any issue with using these docs? That would make life so much easier. -Corey

1 0

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coreboot February 2007