coreboot November 2007

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[LinuxBIOS] r2960 build service
by LinuxBIOS information 13 Nov '07

13 Nov '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2960 to the LinuxBIOS source repository and caused the following changes: Change Log: Various small fixes to make the Tyan S1846 match the format of the other supported 440BX boards. Fix up totally b0rked static device tree in Config.lb. Drop useless and duplicated failover.c, use global one. Make CPU init actually work (result: massive speed-up). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of agami:aruma is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2960&device=aruma&vendor=… Compilation of amd:serengeti_cheetah is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2960&device=serengeti_che… Compilation of asus:a8v-e_se is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2960&device=a8v-e_se&vend… Compilation of iwill:dk8_htx is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2960&device=dk8_htx&vendo… Compilation of tyan:s1846 has been broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2960&device=s1846&vendor=… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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[LinuxBIOS] r2965 - in trunk/LinuxBIOSv2/src: mainboard/asus/a8v-e_se southbridge/via/vt8237r
by svn＠openbios.org 13 Nov '07

13 Nov '07

Author: uwe Date: 2007-11-13 16:40:21 +0100 (Tue, 13 Nov 2007) New Revision: 2965 Modified: trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_lpc.c Log: Add support for FID/VID changes messages. Upon incoming SMAF message from CPU (C3 or FID/VID change), the SB will assert SLP# which is connected to LDTSTOP_L on K8 CPUs. Question is for how long. Imho for 100us. Which is more than plenty (2us required) I will try to justify this once I know what bios to set in SB. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c 2007-11-13 15:26:56 UTC (rev 2964) +++ trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c 2007-11-13 15:40:21 UTC (rev 2965) @@ -309,6 +309,10 @@ #endif init_timer(); ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_lpc.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2007-11-13 15:26:56 UTC (rev 2964) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2007-11-13 15:40:21 UTC (rev 2965) @@ -222,6 +222,13 @@ /* SCI is generated for RTC/pwrBtn/slpBtn. */ outw(0x001, VT8237R_ACPI_IO_BASE + 0x04); + + /* FIXME: Intel needs more bit set for C2/C3. */ + + /* Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. + */ + outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); } static void vt8237r_init(struct device *dev)

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[LinuxBIOS] r2964 - trunk/LinuxBIOSv2/targets/asus/a8v-e_se
by svn＠openbios.org 13 Nov '07

13 Nov '07

Author: uwe Date: 2007-11-13 16:26:56 +0100 (Tue, 13 Nov 2007) New Revision: 2964 Modified: trunk/LinuxBIOSv2/targets/asus/a8v-e_se/Config.lb Log: Small fixes. Drop unneeded or incorrect lines (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/targets/asus/a8v-e_se/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/asus/a8v-e_se/Config.lb 2007-11-13 15:16:06 UTC (rev 2963) +++ trunk/LinuxBIOSv2/targets/asus/a8v-e_se/Config.lb 2007-11-13 15:26:56 UTC (rev 2964) @@ -21,42 +21,18 @@ mainboard asus/a8v-e_se romimage "normal" -# 48K for SCSI FW -# option ROM_SIZE = 475136 -# option ROM_SIZE = 512*1024-36*1024 - option ROM_SIZE = 512*1024 -# 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 425984 -# 64K for Etherboot -# option ROM_SIZE = 458752 -# option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x18800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" - -# give path to filo.elf if needed - payload filo.elf + option ROM_SIZE = 512 * 1024 + option USE_FALLBACK_IMAGE = 0 + option ROM_IMAGE_SIZE = 128 * 1024 + option LINUXBIOS_EXTRA_VERSION=".0Normal" + payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE=1 -# option USE_FAILOVER_IMAGE=0 - -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x19800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" - -# give path to filo.elf if needed - - payload filo.elf + option USE_FALLBACK_IMAGE = 1 + option ROM_IMAGE_SIZE = 128 * 1024 + option LINUXBIOS_EXTRA_VERSION=".0Fallback" + payload /tmp/filo.elf end buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

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[LinuxBIOS] r2963 - trunk/util/superiotool
by svn＠openbios.org 13 Nov '07

13 Nov '07

Author: uwe Date: 2007-11-13 16:16:06 +0100 (Tue, 13 Nov 2007) New Revision: 2963 Modified: trunk/util/superiotool/nsc.c Log: Add dump support for NSC PC87360. Signed-off-by: Ulf Jordan <jordan(a)chalmers.se> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/nsc.c =================================================================== --- trunk/util/superiotool/nsc.c 2007-11-13 14:56:54 UTC (rev 2962) +++ trunk/util/superiotool/nsc.c 2007-11-13 15:16:06 UTC (rev 2963) @@ -30,6 +30,48 @@ {0xdf, "PC97371", { /* From sensors-detect */ {EOT}}}, {0xe1, "PC87360", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x2a, + 0x2b,0x2c,0x2d,0x2e,EOT}, + {0xe1,0x11,0x00,0x03,0x00,0x00,0x00,NANA,0x00,MISC, + 0x00,0x00,0x00,RSVD,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,EOT}, + {0x00,0x03,0xf2,0x06,0x03,0x02,0x04,0x24,0x00,EOT}}, + {0x1, "Parallel port", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0x78,0x07,0x02,0x04,0x04,0xf2,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}}, + {0x3, "COM1", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}}, + {0x4, "System wake-up control (SWC)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}}, + {0x5, "Mouse", + {0x30,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x0c,0x02,0x04,0x04,EOT}}, + {0x6, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,0xf0, + EOT}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x04,0x04,0x40, + EOT}}, + {0x7, "GPIO", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf2, + EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,0x00,0x00, + EOT}}, + {0x8, "ACCESS.bus (ACB)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,EOT}}, + {0x9, "Fan speed control and monitor (FSCM)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,EOT}}, + {0xa, "Watchdog timer", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x02,EOT}}, {EOT}}}, {0xe2, "PC87351", { {NOLDN, NULL,

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[LinuxBIOS] r2959 build service
by LinuxBIOS information 13 Nov '07

13 Nov '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2959 to the LinuxBIOS source repository and caused the following changes: Change Log: Add support for the Advantech PCM-5820. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of agami:aruma is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2959&device=aruma&vendor=… Compilation of amd:serengeti_cheetah is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2959&device=serengeti_che… Compilation of asus:a8v-e_se is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2959&device=a8v-e_se&vend… Compilation of iwill:dk8_htx is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2959&device=dk8_htx&vendo… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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[LinuxBIOS] [PATCH] flashrom: Fix ATMEL 29C020 detection
by Carl-Daniel Hailfinger 13 Nov '07

13 Nov '07

Fix ATMEL 29C020 detection with flashrom. The JEDEC probe routine had a delay of 10 us after entering ID mode and this was insufficient for the 29C020. The data sheet claims we have to wait 10 ms, but tests have shown that 20 us suffice. Allow for variations in chip delays with a factor of 2 safety margin. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: util/flashrom/jedec.c =================================================================== --- util/flashrom/jedec.c (Revision 2955) +++ util/flashrom/jedec.c (Arbeitskopie) @@ -89,7 +89,11 @@ *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; myusec_delay(10); *(volatile uint8_t *)(bios + 0x5555) = 0x90; - myusec_delay(10); + /* Older chips may need up to 100 us to respond. The ATMEL 29C020 + * needs 10 ms according to the data sheet, but it has been tested + * to work reliably with 20 us. Allow a factor of 2 safety margin. + */ + myusec_delay(40); /* Read product ID */ id1 = *(volatile uint8_t *)bios; @@ -101,7 +105,7 @@ *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; myusec_delay(10); *(volatile uint8_t *)(bios + 0x5555) = 0xF0; - myusec_delay(10); + myusec_delay(40); printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2); if (id1 == flash->manufacture_id && id2 == flash->model_id)

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[LinuxBIOS] r2962 - trunk/util/flashrom
by svn＠openbios.org 13 Nov '07

13 Nov '07

Author: hailfinger Date: 2007-11-13 15:56:54 +0100 (Tue, 13 Nov 2007) New Revision: 2962 Modified: trunk/util/flashrom/jedec.c Log: Fix ATMEL 29C020 detection with flashrom. The JEDEC probe routine had a delay of 10 us after entering ID mode and this was insufficient for the 29C020. The data sheet claims we have to wait 10 ms, but tests have shown that 20 us suffice. Allow for variations in chip delays with a factor of 2 safety margin. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/jedec.c =================================================================== --- trunk/util/flashrom/jedec.c 2007-11-13 14:40:45 UTC (rev 2961) +++ trunk/util/flashrom/jedec.c 2007-11-13 14:56:54 UTC (rev 2962) @@ -89,7 +89,11 @@ *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; myusec_delay(10); *(volatile uint8_t *)(bios + 0x5555) = 0x90; - myusec_delay(10); + /* Older chips may need up to 100 us to respond. The ATMEL 29C020 + * needs 10 ms according to the data sheet, but it has been tested + * to work reliably with 20 us. Allow a factor of 2 safety margin. + */ + myusec_delay(40); /* Read product ID */ id1 = *(volatile uint8_t *)bios; @@ -101,7 +105,7 @@ *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; myusec_delay(10); *(volatile uint8_t *)(bios + 0x5555) = 0xF0; - myusec_delay(10); + myusec_delay(40); printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2); if (id1 == flash->manufacture_id && id2 == flash->model_id)

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[LinuxBIOS] r2961 - trunk/LinuxBIOSv2/src/mainboard/tyan/s1846
by svn＠openbios.org 13 Nov '07

13 Nov '07

Author: uwe Date: 2007-11-13 15:40:45 +0100 (Tue, 13 Nov 2007) New Revision: 2961 Removed: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/failover.c Log: Drop obsolete failover.c, forgot it in the last commit (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de>

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[LinuxBIOS] [PATCH] Various Tyan S1846 fixes (repost)
by Uwe Hermann 13 Nov '07

13 Nov '07

See patch. This brings the S1846 in line with all the other 440BX based boards. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] r2960 - in trunk/LinuxBIOSv2: src/mainboard/tyan/s1846 targets/tyan/s1846
by svn＠openbios.org 13 Nov '07

13 Nov '07

Author: uwe Date: 2007-11-13 15:31:30 +0100 (Tue, 13 Nov 2007) New Revision: 2960 Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/chip.h trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/failover.c trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb Log: Various small fixes to make the Tyan S1846 match the format of the other supported 440BX boards. Fix up totally b0rked static device tree in Config.lb. Drop useless and duplicated failover.c, use global one. Make CPU init actually work (result: massive speed-up). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb 2007-11-13 14:26:54 UTC (rev 2959) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb 2007-11-13 14:31:30 UTC (rev 2960) @@ -1,173 +1,131 @@ ## -## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## This file is part of the LinuxBIOS project. ## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> ## -## Compute the start location and size size of -## The linuxBIOS bootloader. +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. ## -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. ## -## Compute where this copy of linuxBIOS will start in the boot rom +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) -## -## Compute a range of ROM that can cached to speed up linuxBIOS, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## -## Set all of the defaults for an x86 architecture -## - +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) arch i386 end - -## -## Build the objects we have code for in this directory. -## - driver mainboard.o - -#if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o - -## -## Romcc output -## +if HAVE_PIRQ_TABLE + object irq_tables.o +end makerule ./failover.E - depends "$(MAINBOARD)/failover.c ./romcc" - action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end - makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ./romcc" - action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end - -makerule ./auto.E - depends "$(MAINBOARD)/auto.c ./romcc" - action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +makerule ./auto.E + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end -makerule ./auto.inc +makerule ./auto.inc + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" depends "$(MAINBOARD)/auto.c ./romcc" - action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + action "./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end - -## -## Build our 16 bit and 32 bit linuxBIOS entry code -## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where linuxBIOS is entered) -## -if USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds end - -### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of linuxBIOS startup -### Things are delicate and we test to see if we should -### failover to another image. -### if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds + ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit ./auto.inc mainboardinit cpu/x86/mmx/disable_mmx.inc -## -## Include the secondary Configuration files -## dir /pc80 config chip.h chip northbridge/intel/i440bx # Northbridge - device pci_domain 0 on + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge - device pci 1.0 on end # AGP bridge + device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge chip superio/nsc/pc87309 # Super I/O - device pnp 2e.5 on # PS/2 keyboard (+ mouse?) - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - # irq 0x72 = 12 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.b on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.c on # Com2 / IR + device pnp 2e.2 on # COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.d on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 + device pnp 2e.3 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.e on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + device pnp 2e.4 on # Power management end - device pnp 2e.f on # PS/2 mouse + device pnp 2e.5 on # PS/2 mouse irq 0x70 = 12 end + device pnp 2e.6 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end end end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB + device pci 7.1 on end # IDE + device pci 7.2 on end # USB device pci 7.3 on end # ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" end end - chip cpu/intel/slot_2 # CPU - end end - Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Options.lb 2007-11-13 14:26:54 UTC (rev 2959) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Options.lb 2007-11-13 14:31:30 UTC (rev 2960) @@ -1,3 +1,24 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -26,6 +47,7 @@ uses _RAMBASE uses XIP_ROM_SIZE uses XIP_ROM_BASE +uses HAVE_MP_TABLE uses CROSS_COMPILE uses CC uses HOSTCC @@ -37,113 +59,41 @@ uses TTYS0_BASE uses TTYS0_LCS uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from linuxBIOS -## -default HAVE_HARD_RESET=0 - -## -## Build code to export a programmable irq routing table -## -default HAVE_PIRQ_TABLE=0 -default IRQ_SLOT_COUNT=4 - -## -## Build code to export a CMOS option table -## -default HAVE_OPTION_TABLE=0 - -### -### LinuxBIOS layout values -### - -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_SIZE = 256 * 1024 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default ROM_IMAGE_SIZE = 64 * 1024 default FALLBACK_SIZE = 128 * 1024 - -## -## Use a small 8K stack -## -default STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default HAVE_OPTION_TABLE = 0 #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE default USE_OPTION_TABLE = 0 - default _RAMBASE = 0x00004000 - default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 9 +default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_CONSOLE_VGA = 1 +default CONFIG_PCI_ROM_RUN = 1 -## -## The default compiler -## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 - -# Select the serial console base port -default TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 - -## -### Select the linuxBIOS loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=9 -## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=9 - -default CONFIG_UDELAY_TSC=1 - end - Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/auto.c 2007-11-13 14:26:54 UTC (rev 2959) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/auto.c 2007-11-13 14:31:30 UTC (rev 2960) @@ -31,12 +31,12 @@ #include "ram/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" -#include "mainboard/bitworks/ims/debug.c" // FIXME +#include "mainboard/asus/mew-vm/debug.c" /* FIXME */ #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "superio/nsc/pc87309/pc87309_early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" +#include "superio/nsc/pc87309/pc87309_early_serial.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87309_SP1) @@ -49,64 +49,24 @@ #include "northbridge/intel/i440bx/debug.c" #include "sdram/generic_sdram.c" -static void enable_mainboard_devices(void) -{ - device_t dev = pci_locate_device(PCI_ID(0x8086, 0x7110), 0); - - if (dev == PCI_DEV_INVALID) { - die("Southbridge not found!\n"); - } else { - print_debug("Southbridge found!\n"); - } -} - static void main(unsigned long bist) { static const struct mem_controller memctrl[] = { { .d0 = PCI_DEV(0, 0, 0), .channel0 = {0x50, 0x51, 0x52, 0x53}, - }, + } }; - /* Skip this if there was a built in self test failure. */ - if (bist == 0) { + if (bist == 0) early_mtrr_init(); - } pc87309_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); - - /* Halt if there was a built in self test failure. */ report_bist_failure(bist); - - enable_mainboard_devices(); - enable_smbus(); - - dump_spd_registers(&memctrl[0]); - + /* dump_spd_registers(&memctrl[0]); */ sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); - - /* Check whether RAM is working. - * - * Do _not_ check the area from 640 KB - 768 KB, as that's not really - * RAM, but rather reserved for the 'Video Buffer Area'. - * - * Other stuff in the range from 640 KB - 1 MB: - * - * - 640 KB - 768 KB: Video Buffer Area - * - 768 KB - 896 KB: Expansion Area - * - 896 KB - 960 KB: Extended System BIOS Area - * - 960 KB - 1 MB: Memory (BIOS Area) - System BIOS Area - * - * Trying to check these areas will usually fail, too. However, you - * probably can set the PAM registers of the northbridge to map - * those areas to RAM (read/write). In that case you can use the - * range from 768 KB - 1 MB as normal RAM, and thus check it here. - */ - ram_check(0x00000000, 0x0009ffff); /* 0 - 640 KB */ - ram_check(0x000c0000, 0x00100000); /* 768 KB - 1 MB */ - // ram_check(0x00100000, 0x007c0000); /* 1 MB - 64 MB */ + /* ram_check(0, 640 * 1024); */ } Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/chip.h 2007-11-13 14:26:54 UTC (rev 2959) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/chip.h 2007-11-13 14:31:30 UTC (rev 2960) @@ -19,6 +19,4 @@ */ extern struct chip_operations mainboard_tyan_s1846_ops; - -struct mainboard_tyan_s1846_config { -}; +struct mainboard_tyan_s1846_config {}; Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/failover.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/failover.c 2007-11-13 14:26:54 UTC (rev 2959) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/failover.c 2007-11-13 14:31:30 UTC (rev 2960) @@ -1,32 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "arch/romcc_io.h" -#include "pc80/mc146818rtc_early.c" - -static unsigned long main(unsigned long bist) -{ - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} Modified: trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb 2007-11-13 14:26:54 UTC (rev 2959) +++ trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb 2007-11-13 14:31:30 UTC (rev 2960) @@ -22,23 +22,30 @@ mainboard tyan/s1846 option ROM_SIZE = 256 * 1024 -option FALLBACK_SIZE = ROM_SIZE -# romimage "normal" -# option USE_FALLBACK_IMAGE = 0 -# option ROM_IMAGE_SIZE = 56 * 1024 -# option LINUXBIOS_EXTRA_VERSION = ".0Normal" -# payload /tmp/filo.elf -# # payload /tmp/memtest -# end +option MAINBOARD_VENDOR = "Tyan" +option MAINBOARD_PART_NUMBER = "S1846" +# TODO: Add/fix PIRQ table. +option HAVE_PIRQ_TABLE = 0 +option IRQ_SLOT_COUNT = 0 # FIXME + +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 + +option CONFIG_CONSOLE_VGA = 1 +option CONFIG_PCI_ROM_RUN = 1 + +romimage "normal" + option USE_FALLBACK_IMAGE = 0 + option LINUXBIOS_EXTRA_VERSION = ".0Normal" + payload /tmp/filo.elf +end + romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option ROM_IMAGE_SIZE = 56 * 1024 option LINUXBIOS_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf - # payload /tmp/memtest end -# buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" -buildrom ./linuxbios.rom ROM_SIZE "fallback" +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

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coreboot November 2007