coreboot October 2007

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[LinuxBIOS] [flashrom] request for review: VT8233A support
by Peter Lemenkov 22 Oct '07

22 Oct '07

Hello All! Looking at the lspci output I created simple patch for adding VT8233A support. Unfortunately I can't find out what flash-chip is on my mainboard (it's far away from me so I can perform only "software" look) but maybe someone else tests whether this patch works or not? Unfortunately guys from Via still don't answer on my request for datasheets... -- With best regards!

3 7

[LinuxBIOS] r2883 - in trunk/LinuxBIOSv2/src/southbridge/via: . k8t890
by svn＠openbios.org 22 Oct '07

22 Oct '07

Author: uwe Date: 2007-10-22 21:59:57 +0200 (Mon, 22 Oct 2007) New Revision: 2883 Added: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/Config.lb trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890.h trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_ctrl.c trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_dram.c trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_early_car.c trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_host.c trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_host_ctrl.c trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_pcie.c trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_traf_ctrl.c trunk/LinuxBIOSv2/src/southbridge/via/k8t890/romstrap.inc trunk/LinuxBIOSv2/src/southbridge/via/k8t890/romstrap.lds Log: This patch adds support for K8T890CE northbridge. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/Config.lb 2007-10-22 19:59:57 UTC (rev 2883) @@ -0,0 +1,25 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License v2 as published by +## the Free Software Foundation. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver k8t890_ctrl.o +driver k8t890_dram.o +driver k8t890_host.o +driver k8t890_host_ctrl.o +driver k8t890_pcie.o +driver k8t890_traf_ctrl.o Added: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890.h =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890.h (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890.h 2007-10-22 19:59:57 UTC (rev 2883) @@ -0,0 +1,35 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUTHBRIDGE_VIA_K8T890_K8T890_H +#define SOUTHBRIDGE_VIA_K8T890_K8T890_H + +/* Static resources for K8T890. */ +#define K8T890_APIC_ID 0x3 + +/* + * Please check the datasheet and traf_ctrl_enable before change! + * It can't be changed to an arbitrary address. + */ +#define K8T890_APIC_BASE 0xfecc0000 + +#define K8T890_MMCONFIG_MBAR 0x61 +#define K8T890_MULTIPLE_FN_EN 0x4f + +#endif Added: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_ctrl.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_ctrl.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_ctrl.c 2007-10-22 19:59:57 UTC (rev 2883) @@ -0,0 +1,102 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <console/console.h> + +static void ctrl_enable(struct device *dev) +{ + u8 regm, regm2, regm3; + device_t devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_3, 0); + + /* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0] + should to 1 */ + + /* C2P Read ACK Return Priority */ + /* PCI CFG Address bits[27:24] are used as extended register address + bit[11:8] */ + pci_write_config8(dev, 0x47, 0x30); + + /* FIXME: Program V-link 8X 16bit full duplex, this needs to be fixed + for other than VT8237R SB */ + pci_write_config8(dev, 0x48, 0x23); + + /* Magic init. This is not well documented :/ */ + pci_write_config8(dev, 0x70, 0xc2); + + /* PCI Control */ + pci_write_config8(dev, 0x72, 0xee); + pci_write_config8(dev, 0x73, 0x01); + pci_write_config8(dev, 0x74, 0x24); + pci_write_config8(dev, 0x75, 0x0f); + pci_write_config8(dev, 0x76, 0x50); + pci_write_config8(dev, 0x77, 0x08); + pci_write_config8(dev, 0x78, 0x01); + /* APIC on HT */ + pci_write_config8(dev, 0x7c, 0x7f); + pci_write_config8(dev, 0x7f, 0x02); + + /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */ + + regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ + pci_write_config8(dev, 0x57, regm); + + regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ + pci_write_config8(dev, 0x61, regm); + + regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ + pci_write_config8(dev, 0x62, regm); + + regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ + pci_write_config8(dev, 0xe6, regm); + + regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ + + /* + * All access bits for 0xE0000-0xEFFFF encode as just 2 bits! + * So the NB reg is quite inconsistent, we expect there only 0xff or 0x00, + * and write them to 0x63 7-6 but! VIA 8237A has the mirror at 0x64! + */ + if (regm3 == 0xff) + regm3 = 0xc0; + else + regm3 = 0x0; + + /* Shadow page F + memhole copy */ + regm = pci_read_config8(devfun3, 0x83); + pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F)); +} + +static struct device_operations ctrl_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = ctrl_enable, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_7, +}; Added: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_dram.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_dram.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_dram.c 2007-10-22 19:59:57 UTC (rev 2883) @@ -0,0 +1,78 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> + +static void dram_enable(struct device *dev) +{ + msr_t msr; + u16 reg; + + /* + * Enable Lowest Interrupt arbitration for APIC, enable NB APIC + * decoding, MSI support,�no SMRAM, compatible SMM. + */ + pci_write_config8(dev, 0x86, 0x39); + + /* + * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if + * memory is doing K8 the DMA from SB will fail if we have it wrong, + * AND even we have it here, we must later copy it to SB to make it work :/ + */ + + /* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for + * C0000-C3FFF etc. + */ + pci_write_config8(dev, 0x80, 0xff); + /* For page D0000-DFFFF */ + pci_write_config8(dev, 0x81, 0xff); + /* For page E0000-EFFFF */ + pci_write_config8(dev, 0x82, 0xff); + pci_write_config8(dev, 0x83, 0x30); + + msr = rdmsr(TOP_MEM); + reg = pci_read_config16(dev, 0x84); + reg &= 0xf; + pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg); + + reg = pci_read_config16(dev, 0x88); + reg &= 0xf800; + + pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); +} + +static struct device_operations dram_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = dram_enable, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &dram_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_3, +}; Added: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_early_car.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_early_car.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_early_car.c 2007-10-22 19:59:57 UTC (rev 2883) @@ -0,0 +1,56 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Seems the link and width of HT link needs to be setup too, you need to + * generate PCI reset or LDTSTOP to apply. + */ + +u8 k8t890_early_setup_car(u8 width, u8 speed) +{ + u8 awidth, aspeed; + + print_debug("LDT width and speed for K8T890 was"); + awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67); + print_debug_hex8(awidth); + + aspeed = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d); + print_debug_hex8(aspeed); + + if ((aspeed == speed) && (((width == 16) && (awidth == 0x11)) || + ((width == 8) && (awidth == 0x00)))) + return 0; + + /* Update the desired HT LNK capabilities in NB too. */ + pci_write_config8(PCI_DEV(0, 0x0, 0), 0x67, + (width == 16) ? 0x11 : 0x00); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0x6d, speed); + + print_debug(" and will after HT reset: "); + + awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67); + print_debug_hex8(awidth); + + aspeed = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d); + print_debug_hex8(aspeed); + + print_debug("\n"); + + return 1; +} Added: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_host.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_host.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_host.c 2007-10-22 19:59:57 UTC (rev 2883) @@ -0,0 +1,45 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <console/console.h> +#include "k8t890.h" + +static void host_enable(struct device *dev) +{ + /* Multiple function control */ + pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01); +} + +static struct device_operations host_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_enable, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &host_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_0, +}; Added: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_host_ctrl.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_host_ctrl.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_host_ctrl.c 2007-10-22 19:59:57 UTC (rev 2883) @@ -0,0 +1,93 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <console/console.h> + +/* This fine tunes the HT link settings, which were loaded by ROM strap. */ +static void host_ctrl_enable(struct device *dev) +{ + dump_south(dev); + + /* + * Bit 4 is reserved but set by AW. Set PCI to HT outstanding + * requests to 3. + */ + pci_write_config8(dev, 0xa0, 0x13); + + /* Disable NVRAM and enable non-posted PCI writes. */ + pci_write_config8(dev, 0xa1, 0x8e); + + /* + * NVRAM I/O base 0xe00-0xeff, but it is disabled. + * Some bits are set and reserved. + */ + pci_write_config8(dev, 0xa2, 0x0e); + /* Arbitration control, some bits are reserved. */ + pci_write_config8(dev, 0xa5, 0x3c); + + /* Arbitration control 2 */ + pci_write_config8(dev, 0xa6, 0x80); + + writeback(dev, 0xa0, 0x13); /* Bit4 is reserved! */ + writeback(dev, 0xa1, 0x8e); /* Some bits are reserved. */ + writeback(dev, 0xa2, 0x0e); /* I/O NVRAM base 0xe00-0xeff disabled. */ + writeback(dev, 0xa3, 0x31); + writeback(dev, 0xa4, 0x30); + + writeback(dev, 0xa5, 0x3c); /* Some bits reserved. */ + writeback(dev, 0xa6, 0x80); /* Some bits reserved. */ + writeback(dev, 0xa7, 0x86); /* Some bits reserved. */ + writeback(dev, 0xa8, 0x7f); /* Some bits reserved. */ + writeback(dev, 0xa9, 0xcf); /* Some bits reserved. */ + writeback(dev, 0xaa, 0x44); + writeback(dev, 0xab, 0x22); + writeback(dev, 0xac, 0x35); /* Maybe bit0 is read-only? */ + + writeback(dev, 0xae, 0x22); + writeback(dev, 0xaf, 0x40); + /* b0 is missing. */ + writeback(dev, 0xb1, 0x13); + writeback(dev, 0xb4, 0x02); /* Some bits are reserved. */ + writeback(dev, 0xc0, 0x20); + writeback(dev, 0xc1, 0xaa); + writeback(dev, 0xc2, 0xaa); + writeback(dev, 0xc3, 0x02); + writeback(dev, 0xc4, 0x50); + writeback(dev, 0xc5, 0x50); + + dump_south(dev); +} + +static struct device_operations host_ctrl_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_ctrl_enable, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &host_ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_2, +}; Added: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_pcie.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_pcie.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_pcie.c 2007-10-22 19:59:57 UTC (rev 2883) @@ -0,0 +1,164 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> + +void peg_init(struct device *dev) +{ + u8 reg; + + printk_debug("Configuring PCIe PEG\n"); + dump_south(dev); + + /* Disable link. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg | 0x10); + + /* Award has 0xb, VIA recomends 0x4. */ + pci_write_config8(dev, 0xe1, 0xb); + + /* + * pci_write_config8(dev, 0xe2, 0x0); + * pci_write_config8(dev, 0xe3, 0x92); + */ + /* Disable scrambling bit 6 to 1. */ + pci_write_config8(dev, 0xc0, 0x43); + + /* Set replay timer limit. */ + pci_write_config8(dev, 0xb1, 0xf0); + + /* Bit0 = 1 SDP (Start DLLP) always at Lane0. */ + reg = pci_read_config8(dev, 0xb8); + pci_write_config8(dev, 0xb8, reg | 0x1); + + /* + * Downstream wait and Upstream Checking Malformed TLP through + * "Byte Enable Rule" And "Over 4K Boundary Rule". + */ + reg = pci_read_config8(dev, 0xa4); + pci_write_config8(dev, 0xa4, reg | 0x30); + + /* Enable link. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg & ~0x10); + + /* Retrain link. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg | 0x20); + + reg = pci_read_config8(dev, 0x3e); + reg |= 0x40; /* Bus reset. */ + pci_write_config8(dev, 0x3e, reg); + + reg = pci_read_config8(dev, 0x3e); + reg &= ~0x40; /* Clear reset. */ + pci_write_config8(dev, 0x3e, reg); + + dump_south(dev); +} + +void pcie_init(struct device *dev) +{ + u8 reg; + + printk_debug("Configuring PCIe PEXs\n"); + dump_south(dev); + + /* Disable link. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg | 0x10); + + /* Award has 0xb, VIA recommends 0x4. */ + pci_write_config8(dev, 0xe1, 0xb); + /* Set replay timer limit. */ + pci_write_config8(dev, 0xb1, 0xf0); + + /* Enable link. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg & ~0x10); + + /* Retrain. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg | 0x20); + + reg = pci_read_config8(dev, 0x3e); + reg |= 0x40; /* Bus reset. */ + pci_write_config8(dev, 0x3e, reg); + + reg = pci_read_config8(dev, 0x3e); + reg &= ~0x40; /* Clear reset. */ + pci_write_config8(dev, 0x3e, reg); + + dump_south(dev); +} + +static struct device_operations peg_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .enable = peg_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, +}; + +static struct device_operations pcie_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .enable = pcie_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &peg_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEG, +}; + +static struct pci_driver pcie_drvd3f0 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX0, +}; + +static struct pci_driver pcie_drvd3f1 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX1, +}; + +static struct pci_driver pcie_drvd3f2 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX2, +}; + +static struct pci_driver pcie_drvd3f3 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX3, +}; Added: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_traf_ctrl.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_traf_ctrl.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_traf_ctrl.c 2007-10-22 19:59:57 UTC (rev 2883) @@ -0,0 +1,121 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <console/console.h> + +#include "k8t890.h" + +void mmconfig_set_resources(device_t dev) +{ + struct resource *resource; + u8 reg; + + resource = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (resource) { + report_resource_stored(dev, resource, "<mmconfig>"); + + /* Remember this resource has been stored. */ + resource->flags |= IORESOURCE_STORED; + pci_write_config8(dev, K8T890_MMCONFIG_MBAR, + (resource->base >> 28)); + reg = pci_read_config8(dev, 0x60); + reg |= 0x3; + /* Enable MMCONFIG decoding. */ + pci_write_config8(dev, 0x60, reg); + } + pci_dev_set_resources(dev); +} + +static void apic_mmconfig_read_resources(device_t dev) +{ + struct resource *res; + pci_dev_read_resources(dev); + + res = new_resource(dev, 0x40); + /* NB APIC fixed to this address. */ + res->base = K8T890_APIC_BASE; + res->size = 256; + res->limit = res->base + res->size - 1; + res->align = 8; + res->gran = 8; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Add an MMCONFIG resource. */ + res = new_resource(dev, K8T890_MMCONFIG_MBAR); + res->size = 256 * 1024 * 1024; + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffff; /* 4G */ + res->flags = IORESOURCE_MEM; +} + +static void traf_ctrl_enable(struct device *dev) +{ + volatile u32 *apic; + u32 data; + + /* Enable D3F1-D3F3, no device2 redirect, enable just one device behind + * bridge device 2 and device 3). + */ + pci_write_config8(dev, 0x60, 0x88); + + /* Will enable MMCONFIG later. */ + pci_write_config8(dev, 0x64, 0x23); + /* No extended RCRB Base Address. */ + pci_write_config8(dev, 0x62, 0x00); + + /* Offset80 ->95 bit 4 in 1 in Award. */ + + /* Enable APIC, to K8T890_APIC_BASE. */ + pci_write_config8(dev, 0x41, 0x00); + pci_write_config8(dev, 0x40, 0x8c); + /* BT_INTR enable, APIC Nonshare Mode Enable. */ + pci_write_config8(dev, 0x42, 0x5); + + apic = (u32 *)K8T890_APIC_BASE; + + /* Set APIC to FSB transported messages. */ + apic[0] = 3; + data = apic[4]; + apic[4] = (data & 0xFFFFFE) | 1; + + /* Set APIC ID. */ + apic[0] = 0; + data = apic[4]; + apic[4] = (data & 0xF0FFFF) | (K8T890_APIC_ID << 24); +} + +static struct device_operations traf_ctrl_ops = { + .read_resources = apic_mmconfig_read_resources, + .set_resources = mmconfig_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = traf_ctrl_enable, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &traf_ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_5, +}; Added: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/romstrap.inc =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/romstrap.inc (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/romstrap.inc 2007-10-22 19:59:57 UTC (rev 2883) @@ -0,0 +1,61 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2004 Tyan Computer + * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer) + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file constructs the ROM strap table for K8T890. */ + +.section ".romstrap", "a", @progbits + +.globl __romstrap_start +.globl __romstrap_end + +__romstrap_start: + +/* + * Below are some Dev0 Func2 HT control registers values, + * depending on strap pin, one of below lines is used. + */ +tblpointer: +.long 0x504400AA, 0x61970FC2 //;200M +.long 0x504400AA, 0x61970FC2 //;400M +.long 0x504400AA, 0x61970FC2 //;600M +.long 0x504400AA, 0x61970FC2 //;800M +.long 0x504400AA, 0x61970FC2 //;1000M +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 + +/* + * The pointer to above table should be at 0xffffd, + * the table itself MUST be aligned to 128B it seems! + */ +.long tblpointer - 0xFFF00000 + +__romstrap_end: + +.previous Added: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/romstrap.lds =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/romstrap.lds (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/romstrap.lds 2007-10-22 19:59:57 UTC (rev 2883) @@ -0,0 +1,29 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Modified for K8T890 ROM strap by Rudolf Marek <r.marek(a)assembler.cz>. */ + +SECTIONS { + . = (_ROMBASE + ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start); + .romstrap (.): { + *(.romstrap) + } +}

1 0

[LinuxBIOS] [flashrom] patch: more flashchip vendors (trivial)
by Peter Lemenkov 22 Oct '07

22 Oct '07

Hello All! This patch simply adds some more existing chip vendors ID. No more no less. Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- -- With best regards!

2 1

[LinuxBIOS] r2882 build service
by LinuxBIOS information 22 Oct '07

22 Oct '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "rminnich" checked in revision 2882 to the LinuxBIOS source repository and caused the following changes: Change Log: Trivial: remove unused variable. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2882&device=hdama&vendor=… Configuration of bcom:winnet100 is still broken Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2882&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2882&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2882&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2882&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2882&device=dk8x&vendor=i… Compilation of newisys:khepri is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2882&device=khepri&vendor… If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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[LinuxBIOS] r2882 - trunk/LinuxBIOSv2/src/ram
by svn＠openbios.org 22 Oct '07

22 Oct '07

Author: rminnich Date: 2007-10-22 19:04:39 +0200 (Mon, 22 Oct 2007) New Revision: 2882 Modified: trunk/LinuxBIOSv2/src/ram/ramtest.c Log: Trivial: remove unused variable. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/LinuxBIOSv2/src/ram/ramtest.c =================================================================== --- trunk/LinuxBIOSv2/src/ram/ramtest.c 2007-10-22 16:15:28 UTC (rev 2881) +++ trunk/LinuxBIOSv2/src/ram/ramtest.c 2007-10-22 17:04:39 UTC (rev 2882) @@ -94,7 +94,6 @@ void ram_check(unsigned long start, unsigned long stop) { - int result; /* * This is much more of a "Is my DRAM properly configured?" * test than a "Is my DRAM faulty?" test. Not all bits

1 0

[LinuxBIOS] r2881 build service
by LinuxBIOS information 22 Oct '07

22 Oct '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "hailfinger" checked in revision 2881 to the LinuxBIOS source repository and caused the following changes: Change Log: Introduce block and sector erase routines to flashrom, but do not use them yet. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2881&device=hdama&vendor=… Configuration of bcom:winnet100 is still broken Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2881&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2881&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2881&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2881&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2881&device=dk8x&vendor=i… Compilation of newisys:khepri is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2881&device=khepri&vendor… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

1 0

[LinuxBIOS] [PATCH] flashrom: SPI serial flash: The sector/block erase pitfalls
by Carl-Daniel Hailfinger 22 Oct '07

22 Oct '07

This is more a rant than a tutorial how to solve the remaining problems. Almost all SPI flash falls into at least one of three categories: * Does not respect the JEDEC standards * Totally different chips with exactly the same ID and no means to tell them apart unless you physically look at their part number * Completely weird configuration, unique per chip SST SST25* chips claim not to support standard JEDEC RDID. Maybe someone just forgot to write something about RDID support in the data sheet, but even then we don't know what values they would return. Macronix MX25* chips sometimes have two variants of the same chip (exactly same electronic ID) with different sector sizes. The slow variant with useless big sectors and less reflash cycles calls itself "eliteflash". EON EN25* chips have variable sized blocks between 4-32k, call these blocks sectors and have no sector erase support. To make matters worse, different chips with different block configurations return exactly the same values from RDID. At least they can somewhat be told apart when using REMS. This patch introduces block and sector erase routines, but does not use them yet. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> --- Index: util/flashrom/spi.c =================================================================== --- util/flashrom/spi.c (Revision 2876) +++ util/flashrom/spi.c (Arbeitskopie) @@ -45,17 +45,31 @@ #define JEDEC_WRDI_OUTSIZE 0x01 #define JEDEC_WRDI_INSIZE 0x00 -/* Both Chip Erase commands below should work */ -/* Chip Erase 0x60 */ +/* Chip Erase 0x60 is supported by Macronix/SST chips */ #define JEDEC_CE_1 {0x60}; #define JEDEC_CE_1_OUTSIZE 0x01 #define JEDEC_CE_1_INSIZE 0x00 -/* Chip Erase 0xc7 */ +/* Chip Erase 0xc7 is supported by EON/Macronix chips */ #define JEDEC_CE_2 {0xc7}; #define JEDEC_CE_2_OUTSIZE 0x01 #define JEDEC_CE_2_INSIZE 0x00 +/* Block Erase 0x52 is supported by SST chips */ +#define JEDEC_BE_1 {0x52}; +#define JEDEC_BE_1_OUTSIZE 0x04 +#define JEDEC_BE_1_INSIZE 0x00 + +/* Block Erase 0xd8 is supported by EON/Macronix chips */ +#define JEDEC_BE_2 {0xd8}; +#define JEDEC_BE_2_OUTSIZE 0x04 +#define JEDEC_BE_2_INSIZE 0x00 + +/* Sector Erase 0x20 is supported by Macronix/SST chips*/ +#define JEDEC_SE {0x20}; +#define JEDEC_SE_OUTSIZE 0x04 +#define JEDEC_SE_INSIZE 0x00 + /* Read Status Register */ #define JEDEC_RDSR {0x05}; #define JEDEC_RDSR_OUTSIZE 0x01 @@ -269,13 +283,52 @@ generic_spi_write_enable(); /* Send CE (Chip Erase) */ - generic_spi_command(1, 0, cmd, NULL); + generic_spi_command(JEDEC_CE_2_OUTSIZE, JEDEC_CE_2_INSIZE, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared */ while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP) sleep(1); return 0; } +/* Block size is usually + * 64k for Macronix + * 32k for SST + * 4-32k non-uniform for EON + */ +int generic_spi_block_erase(struct flashchip *flash, unsigned long addr) +{ + unsigned char cmd[JEDEC_BE_2_OUTSIZE] = JEDEC_BE_2; + + cmd[1] = (addr & 0x00ff0000) >> 16; + cmd[2] = (addr & 0x0000ff00) >> 8; + cmd[3] = (addr & 0x000000ff); + generic_spi_write_enable(); + /* Send BE (Block Erase) */ + generic_spi_command(JEDEC_BE_2_OUTSIZE, JEDEC_BE_2_INSIZE, cmd, NULL); + /* Wait until the Write-In-Progress bit is cleared */ + while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + usleep(100 * 1000); + return 0; +} + +/* Sector size is usually 4k, though Macronix eliteflash has 64k */ +int generic_spi_sector_erase(struct flashchip *flash, unsigned long addr) +{ + unsigned char cmd[JEDEC_SE_OUTSIZE] = JEDEC_SE; + cmd[1] = (addr & 0x00ff0000) >> 16; + cmd[2] = (addr & 0x0000ff00) >> 8; + cmd[3] = (addr & 0x000000ff); + + generic_spi_write_enable(); + /* Send SE (Sector Erase) */ + generic_spi_command(JEDEC_SE_OUTSIZE, JEDEC_SE_INSIZE, cmd, NULL); + /* Wait until the Write-In-Progress bit is cleared */ + while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + usleep(10 * 1000); + return 0; +} + +/* Page size is usually 256 bytes */ void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios) { int i;

3 4

[LinuxBIOS] r2881 - trunk/util/flashrom
by svn＠openbios.org 22 Oct '07

22 Oct '07

Author: hailfinger Date: 2007-10-22 18:15:28 +0200 (Mon, 22 Oct 2007) New Revision: 2881 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c trunk/util/flashrom/spi.c Log: Introduce block and sector erase routines to flashrom, but do not use them yet. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2007-10-22 10:07:46 UTC (rev 2880) +++ trunk/util/flashrom/flash.h 2007-10-22 16:15:28 UTC (rev 2881) @@ -72,7 +72,7 @@ #define EON_ID 0x1C /* EN25 chips are SPI, first byte of device id is memory type, - second byte of device id is log(bitsize)-9 */ + * second byte of device id is log(bitsize)-9. */ #define EN_25B05 0x2010 /* 2^19 kbit or 2^16 kByte */ #define EN_25B10 0x2011 #define EN_25B20 0x2012 @@ -82,9 +82,8 @@ #define EN_25B32 0x2016 #define MX_ID 0xC2 /* Macronix (MX) */ -#define MX_29F002 0xB0 -/* MX25L chips are SPI, first byte of device id is memory type, - second byte of device id is log(bitsize)-9 */ +/* MX25 chips are SPI, first byte of device id is memory type, + * second byte of device id is log(bitsize)-9. */ #define MX_25L512 0x2010 /* 2^19 kbit or 2^16 kByte */ #define MX_25L1005 0x2011 #define MX_25L2005 0x2012 @@ -95,11 +94,22 @@ #define MX_25L6405 0x2017 /* MX25L3205{,D} */ #define MX_25L1635D 0x2415 #define MX_25L3235D 0x2416 +#define MX_29F002 0xB0 #define SHARP_ID 0xB0 /* Sharp */ #define SHARP_LHF00L04 0xCF #define SST_ID 0xBF /* SST */ +/* SST25 chips are SPI, first byte of device id is memory type, second + * byte of device id is related to log(bitsize) at least for some chips. */ +#define SST_25WF512 0x2501 +#define SST_25WF010 0x2502 +#define SST_25WF020 0x2503 +#define SST_25WF040 0x2504 +#define SST_25VF016B 0x2541 +#define SST_25VF032B 0x254A +#define SST_25VF040B 0x258D +#define SST_25VF080B 0x258E #define SST_29EE020A 0x10 #define SST_28SF040 0x04 #define SST_39SF010 0xB5 @@ -210,7 +220,7 @@ /* spi.c */ int probe_spi(struct flashchip *flash); int it87xx_probe_spi_flash(const char *name); -int generic_spi_command(unsigned char writecnt, unsigned char readcnt, const unsigned char *writearr, unsigned char *readarr); +int generic_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); void generic_spi_write_enable(); void generic_spi_write_disable(); int generic_spi_chip_erase(struct flashchip *flash); Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2007-10-22 10:07:46 UTC (rev 2880) +++ trunk/util/flashrom/flashchips.c 2007-10-22 16:15:28 UTC (rev 2881) @@ -36,7 +36,7 @@ probe_jedec, erase_chip_jedec, write_jedec}, {"At29C020", ATMEL_ID, AT_29C020, 256, 256, probe_jedec, erase_chip_jedec, write_jedec}, - {"Mx29f002", MX_ID, MX_29F002, 256, 64 * 1024, + {"MX29F002", MX_ID, MX_29F002, 256, 64 * 1024, probe_29f002, erase_29f002, write_29f002}, {"MX25L4005", MX_ID, MX_25L4005, 512, 4 * 1024, probe_spi, generic_spi_chip_erase, generic_spi_chip_write}, Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2007-10-22 10:07:46 UTC (rev 2880) +++ trunk/util/flashrom/spi.c 2007-10-22 16:15:28 UTC (rev 2881) @@ -45,17 +45,31 @@ #define JEDEC_WRDI_OUTSIZE 0x01 #define JEDEC_WRDI_INSIZE 0x00 -/* Both Chip Erase commands below should work */ -/* Chip Erase 0x60 */ +/* Chip Erase 0x60 is supported by Macronix/SST chips. */ #define JEDEC_CE_1 {0x60}; #define JEDEC_CE_1_OUTSIZE 0x01 #define JEDEC_CE_1_INSIZE 0x00 -/* Chip Erase 0xc7 */ +/* Chip Erase 0xc7 is supported by EON/Macronix chips. */ #define JEDEC_CE_2 {0xc7}; #define JEDEC_CE_2_OUTSIZE 0x01 #define JEDEC_CE_2_INSIZE 0x00 +/* Block Erase 0x52 is supported by SST chips. */ +#define JEDEC_BE_1 {0x52}; +#define JEDEC_BE_1_OUTSIZE 0x04 +#define JEDEC_BE_1_INSIZE 0x00 + +/* Block Erase 0xd8 is supported by EON/Macronix chips. */ +#define JEDEC_BE_2 {0xd8}; +#define JEDEC_BE_2_OUTSIZE 0x04 +#define JEDEC_BE_2_INSIZE 0x00 + +/* Sector Erase 0x20 is supported by Macronix/SST chips. */ +#define JEDEC_SE {0x20}; +#define JEDEC_SE_OUTSIZE 0x04 +#define JEDEC_SE_INSIZE 0x00 + /* Read Status Register */ #define JEDEC_RDSR {0x05}; #define JEDEC_RDSR_OUTSIZE 0x01 @@ -144,7 +158,7 @@ whereas the IT8716F splits commands internally into address and non-address commands with the address in inverse wire order. That's why the register ordering in case 4 and 5 may seem strange. */ -static int it8716f_spi_command(uint16_t port, unsigned char writecnt, unsigned char readcnt, const unsigned char *writearr, unsigned char *readarr) +static int it8716f_spi_command(uint16_t port, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint8_t busy, writeenc; int i; @@ -188,7 +202,7 @@ return 1; } /* Start IO, 33MHz, readcnt input bytes, writecnt output bytes. Note: - * We can't use writecnt directly, but have to use a strange encoding + * We can't use writecnt directly, but have to use a strange encoding. */ outb((0x5 << 4) | ((readcnt & 0x3) << 2) | (writeenc), port); do { @@ -202,7 +216,7 @@ return 0; } -int generic_spi_command(unsigned char writecnt, unsigned char readcnt, const unsigned char *writearr, unsigned char *readarr) +int generic_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { if (it8716f_flashport) return it8716f_spi_command(it8716f_flashport, writecnt, readcnt, writearr, readarr); @@ -269,13 +283,58 @@ generic_spi_write_enable(); /* Send CE (Chip Erase) */ - generic_spi_command(1, 0, cmd, NULL); - /* Wait until the Write-In-Progress bit is cleared */ + generic_spi_command(JEDEC_CE_2_OUTSIZE, JEDEC_CE_2_INSIZE, cmd, NULL); + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 1-85 s, so wait in 1 s steps. + */ while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP) sleep(1); return 0; } +/* Block size is usually + * 64k for Macronix + * 32k for SST + * 4-32k non-uniform for EON + */ +int generic_spi_block_erase(const struct flashchip *flash, unsigned long addr) +{ + unsigned char cmd[JEDEC_BE_2_OUTSIZE] = JEDEC_BE_2; + + cmd[1] = (addr & 0x00ff0000) >> 16; + cmd[2] = (addr & 0x0000ff00) >> 8; + cmd[3] = (addr & 0x000000ff); + generic_spi_write_enable(); + /* Send BE (Block Erase) */ + generic_spi_command(JEDEC_BE_2_OUTSIZE, JEDEC_BE_2_INSIZE, cmd, NULL); + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + usleep(100 * 1000); + return 0; +} + +/* Sector size is usually 4k, though Macronix eliteflash has 64k */ +int generic_spi_sector_erase(const struct flashchip *flash, unsigned long addr) +{ + unsigned char cmd[JEDEC_SE_OUTSIZE] = JEDEC_SE; + cmd[1] = (addr & 0x00ff0000) >> 16; + cmd[2] = (addr & 0x0000ff00) >> 8; + cmd[3] = (addr & 0x000000ff); + + generic_spi_write_enable(); + /* Send SE (Sector Erase) */ + generic_spi_command(JEDEC_SE_OUTSIZE, JEDEC_SE_INSIZE, cmd, NULL); + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 15-800 ms, so wait in 10 ms steps. + */ + while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + usleep(10 * 1000); + return 0; +} + +/* Page size is usually 256 bytes */ void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios) { int i; @@ -286,7 +345,9 @@ bios[256 * block + i] = buf[256 * block + i]; } outb(0, it8716f_flashport); - /* Wait until the Write-In-Progress bit is cleared */ + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 1-10 ms, so wait in 1 ms steps. + */ while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP) usleep(1000); }

1 0

[LinuxBIOS] r2880 build service
by LinuxBIOS information 22 Oct '07

22 Oct '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "stepan" checked in revision 2880 to the LinuxBIOS source repository and caused the following changes: Change Log: This is a hack for easier testing of GRUB2 in LinuxBIOSv2 since it is still our most wide-spread codebase. The patch is pretty trivial, and nobody except Torsten even looked at it in a week, so.... Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2880&device=hdama&vendor=… Configuration of bcom:winnet100 is still broken Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2880&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2880&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2880&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2880&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2880&device=dk8x&vendor=i… Compilation of newisys:khepri is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2880&device=khepri&vendor… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

1 0

[LinuxBIOS] r2880 - in trunk/LinuxBIOSv2: src/mainboard/emulation/qemu-i386 targets/emulation/qemu-i386
by svn＠openbios.org 22 Oct '07

22 Oct '07

Author: stepan Date: 2007-10-22 12:07:46 +0200 (Mon, 22 Oct 2007) New Revision: 2880 Added: trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/vgabios.c Modified: trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/Config.lb trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/mainboard.c trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.lb Log: This is a hack for easier testing of GRUB2 in LinuxBIOSv2 since it is still our most wide-spread codebase. The patch is pretty trivial, and nobody except Torsten even looked at it in a week, so.... Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/Config.lb 2007-10-21 04:33:02 UTC (rev 2879) +++ trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/Config.lb 2007-10-22 10:07:46 UTC (rev 2880) @@ -39,6 +39,7 @@ ## driver mainboard.o +object vgabios.o if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o Modified: trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/mainboard.c 2007-10-21 04:33:02 UTC (rev 2879) +++ trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/mainboard.c 2007-10-22 10:07:46 UTC (rev 2880) @@ -1,6 +1,38 @@ +#include <console/console.h> #include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> #include "chip.h" +void vga_enable_console(); + +static void vga_init(device_t dev) +{ + /* code to make vga init run in real mode - does work but against the current Linuxbios philosophy */ + printk_debug("INSTALL REAL-MODE IDT\n"); + setup_realmode_idt(); + printk_debug("DO THE VGA BIOS\n"); + do_vgabios(); + + vga_enable_console(); +} + +static struct device_operations vga_operations = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = vga_init, + .ops_pci = 0, +}; + +static struct pci_driver vga_driver __pci_driver = { + .ops = &vga_operations, + .vendor = 0x1013, + .device = 0x00b8, +}; + struct chip_operations mainboard_emulation_qemu_i386_ops = { CHIP_NAME("QEMU Mainboard") }; Added: trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/vgabios.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/vgabios.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/emulation/qemu-i386/vgabios.c 2007-10-22 10:07:46 UTC (rev 2880) @@ -0,0 +1,838 @@ +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#undef __KERNEL__ +#include <arch/io.h> +#include <string.h> + +/* vgabios.c. Derived from: */ + +/*------------------------------------------------------------ -*- C -*- + * 2 Kernel Monte a.k.a. Linux loading Linux on x86 + * + * Erik Arjan Hendriks <hendriks(a)lanl.gov> + * + * This version is a derivative of the original two kernel monte + * which is (C) 2000 Scyld. + * + * Copyright (C) 2000 Scyld Computing Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Portions related to the alpha architecture are: + * + * Copyright(C) 2001 University of California. LA-CC Number 01-67. + * This software has been authored by an employee or employees of the + * University of California, operator of the Los Alamos National + * Laboratory under Contract No. W-7405-ENG-36 with the U.S. + * Department of Energy. The U.S. Government has rights to use, + * reproduce, and distribute this software. If the software is + * modified to produce derivative works, such modified software should + * be clearly marked, so as not to confuse it with the version + * available from LANL. + * + * This software may be used and distributed according to the terms + * of the GNU General Public License, incorporated herein by + * reference to http://www.gnu.org/licenses/gpl.html. + * + * This software is provided by the author(s) "as is" and any express + * or implied warranties, including, but not limited to, the implied + * warranties of merchantability and fitness for a particular purpose + * are disclaimed. In no event shall the author(s) be liable for any + * direct, indirect, incidental, special, exemplary, or consequential + * damages (including, but not limited to, procurement of substitute + * goods or services; loss of use, data, or profits; or business + * interruption) however caused and on any theory of liability, + * whether in contract, strict liability, or tort (including + * negligence or otherwise) arising in any way out of the use of this + * software, even if advised of the possibility of such damage. + * + * $Id: vgabios.c,v 1.5 2004/10/06 17:33:52 rminnich Exp $ + *--------------------------------------------------------------------*/ + +/* Modified to be a self sufficient plug in so that it can be used + without reliance on other parts of core Linuxbios + (C) 2005 Nick.Barker9(a)btinternet.com + + Used initially for epia-m where there are problems getting the bios + emulator to successfully run this bios. +*/ + +/* Declare a temporary global descriptor table - necessary because the + Core part of the bios no longer sets up any 16 bit segments */ +__asm__ ( + /* pointer to original gdt */ + "gdtarg: \n" + " .word gdt_limit \n" + " .long gdt \n" + + /* compute the table limit */ + "__mygdt_limit = __mygdt_end - __mygdt - 1 \n" + + "__mygdtaddr: \n" + " .word __mygdt_limit \n" + " .long __mygdt \n" + + "__mygdt: \n" + /* selgdt 0, unused */ + " .word 0x0000, 0x0000 \n" + " .byte 0x00, 0x00, 0x00, 0x00 \n" + + /* selgdt 8, unused */ + " .word 0x0000, 0x0000 \n" + " .byte 0x00, 0x00, 0x00, 0x00 \n" + + /* selgdt 0x10, flat code segment */ + " .word 0xffff, 0x0000 \n" + " .byte 0x00, 0x9b, 0xcf, 0x00 \n" + + /* selgdt 0x18, flat data segment */ + " .word 0xffff, 0x0000 \n" + " .byte 0x00, 0x93, 0xcf, 0x00 \n" + + /* selgdt 0x20, unused */ + " .word 0x0000, 0x0000 \n" + " .byte 0x00, 0x00, 0x00, 0x00 \n" + + /* selgdt 0x28 16-bit 64k code at 0x00000000 */ + " .word 0xffff, 0x0000 \n" + " .byte 0, 0x9a, 0, 0 \n" + + /* selgdt 0x30 16-bit 64k data at 0x00000000 */ + " .word 0xffff, 0x0000 \n" + " .byte 0, 0x92, 0, 0 \n" + + "__mygdt_end: \n" +); + +/* Declare a pointer to where our idt is going to be i.e. at mem zero */ +__asm__ ("__myidt: \n" + /* 16-bit limit */ + " .word 1023 \n" + /* 24-bit base */ + " .long 0 \n" + " .word 0 \n" +); + +/* The address arguments to this function are PHYSICAL ADDRESSES */ +static void real_mode_switch_call_vga(unsigned long devfn) +{ + __asm__ __volatile__ ( + // paranoia -- does ecx get saved? not sure. This is + // the easiest safe thing to do. + " pushal \n" + /* save the stack */ + " mov %esp, __stack \n" + " jmp 1f \n" + "__stack: .long 0 \n" + "1:\n" + /* get devfn into %ecx */ + " movl %esp, %ebp \n" + " movl 8(%ebp), %ecx \n" + /* load 'our' gdt */ + " lgdt %cs:__mygdtaddr \n" + + /* This configures CS properly for real mode. */ + " ljmp $0x28, $__rms_16bit\n" + "__rms_16bit: \n" + " .code16 \n" + /* 16 bit code from here on... */ + + /* Load the segment registers w/ properly configured segment + * descriptors. They will retain these configurations (limits, + * writability, etc.) once protected mode is turned off. */ + " mov $0x30, %ax \n" + " mov %ax, %ds \n" + " mov %ax, %es \n" + " mov %ax, %fs \n" + " mov %ax, %gs \n" + " mov %ax, %ss \n" + + /* Turn off protection (bit 0 in CR0) */ + " movl %cr0, %eax \n" + " andl $0xFFFFFFFE, %eax \n" + " movl %eax, %cr0 \n" + + /* Now really going into real mode */ + " ljmp $0, $__rms_real\n" + "__rms_real: \n" + + /* put the stack at the end of page zero. + * that way we can easily share it between real and protected, + * since the 16-bit ESP at segment 0 will work for any case. + /* Setup a stack */ + " mov $0x0, %ax \n" + " mov %ax, %ss \n" + " movl $0x1000, %eax \n" + " movl %eax, %esp \n" + + /* Load our 16 it idt */ + " xor %ax, %ax \n" + " mov %ax, %ds \n" + " lidt __myidt \n" + + /* Dump zeros in the other segregs */ + " mov %ax, %es \n" + " mov %ax, %fs \n" + " mov %ax, %gs \n" + " mov $0x40, %ax \n" + " mov %ax, %ds \n" + " mov %cx, %ax \n" + + /* run VGA BIOS at 0xc000:0003 */ + " lcall $0xc000, $0x0003\n" + + /* if we got here, just about done. + * Need to get back to protected mode */ + " movl %cr0, %eax \n" + " orl $0x0000001, %eax\n" /* PE = 1 */ + " movl %eax, %cr0 \n" + + /* Now that we are in protected mode jump to a 32 bit code segment. */ + " data32 ljmp $0x10, $vgarestart\n" + "vgarestart:\n" + " .code32\n" + " movw $0x18, %ax \n" + " mov %ax, %ds \n" + " mov %ax, %es \n" + " mov %ax, %fs \n" + " mov %ax, %gs \n" + " mov %ax, %ss \n" + + /* restore proper gdt and idt */ + " lgdt %cs:gdtarg \n" + " lidt idtarg \n" + + ".globl vga_exit \n" + "vga_exit: \n" + " mov __stack, %esp \n" + " popal \n" + ); +} + +__asm__ (".text\n""real_mode_switch_end:\n"); +extern char real_mode_switch_end[]; + +/* call vga bios int 10 function 0x4f14 to enable main console + epia-m does not always autosence the main console so forcing it on is good !! */ +void vga_enable_console() +{ + __asm__ __volatile__ ( + /* paranoia -- does ecx get saved? not sure. This is + * the easiest safe thing to do. */ + " pushal \n" + /* save the stack */ + " mov %esp, __stack \n" + + /* load 'our' gdt */ + " lgdt %cs:__mygdtaddr \n" + + /* This configures CS properly for real mode. */ + " ljmp $0x28, $__vga_ec_16bit\n" + "__vga_ec_16bit: \n" + " .code16 \n" + /* 16 bit code from here on... */ + + /* Load the segment registers w/ properly configured segment + * descriptors. They will retain these configurations (limits, + * writability, etc.) once protected mode is turned off. */ + " mov $0x30, %ax \n" + " mov %ax, %ds \n" + " mov %ax, %es \n" + " mov %ax, %fs \n" + " mov %ax, %gs \n" + " mov %ax, %ss \n" + + /* Turn off protection (bit 0 in CR0) */ + " movl %cr0, %eax \n" + " andl $0xFFFFFFFE, %eax\n" + " movl %eax, %cr0 \n" + + /* Now really going into real mode */ + " ljmp $0, $__vga_ec_real \n" + "__vga_ec_real: \n" + + /* put the stack at the end of page zero. + * that way we can easily share it between real and protected, + * since the 16-bit ESP at segment 0 will work for any case. + /* Setup a stack */ + " mov $0x0, %ax \n" + " mov %ax, %ss \n" + " movl $0x1000, %eax \n" + " movl %eax, %esp \n" + + /* debugging for RGM */ + " mov $0x11, %al \n" + " outb %al, $0x80 \n" + + /* Load our 16 it idt */ + " xor %ax, %ax \n" + " mov %ax, %ds \n" + " lidt __myidt \n" + + /* Dump zeros in the other segregs */ + " mov %ax, %ds \n" + " mov %ax, %es \n" + " mov %ax, %fs \n" + " mov %ax, %gs \n" + + /* ask bios to enable main console */ + /* set up for int 10 call - values found from X server + * bios call routines */ + //" movw $0x4f14,%ax \n" + " movw $0x0002,%ax \n" + //" movw $0x8003,%bx \n" + " movw $1, %cx \n" + " movw $0, %dx \n" + " movw $0, %di \n" + " int $0x10 \n" + + " movb $0x55, %al \n" + " outb %al, $0x80 \n" + + /* if we got here, just about done. + * Need to get back to protected mode */ + " movl %cr0, %eax \n" + " orl $0x0000001, %eax\n" /* PE = 1 */ + " movl %eax, %cr0 \n" + + /* Now that we are in protected mode jump to a 32 bit code segment. */ + " data32 ljmp $0x10, $vga_ec_restart\n" + "vga_ec_restart:\n" + " .code32\n" + " movw $0x18, %ax \n" + " mov %ax, %ds \n" + " mov %ax, %es \n" + " mov %ax, %fs \n" + " mov %ax, %gs \n" + " mov %ax, %ss \n" + + /* restore proper gdt and idt */ + " lgdt %cs:gdtarg \n" + " lidt idtarg \n" + " .globl vga__ec_exit \n" + "vga_ec_exit:\n" + " mov __stack, %esp \n" + " popal\n" + ); +} + +void do_vgabios(void) +{ + device_t dev; + unsigned long busdevfn; + unsigned int rom = 0; + unsigned char *buf; + unsigned int size = 64*1024; + int i; + + /* clear vga bios data area */ + for (i = 0x400; i < 0x500; i++) { + *(unsigned char *) i = 0; + } + + dev = dev_find_class(PCI_CLASS_DISPLAY_VGA<<8 , 0); + + if (!dev) { + printk_debug("NO VGA FOUND\n"); + return; + } + printk_debug("found VGA: vid=%x, did=%x\n", dev->vendor, dev->device); + + /* declare rom address here - keep any config data out of the way + * of core LXB stuff */ + + rom = 0xc0000; + // pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1); + printk_debug("rom base, size: %x\n", rom); + + buf = (unsigned char *) rom; + if ((buf[0] == 0x55) && (buf[1] == 0xaa)) { + memcpy((void *) 0xc0000, buf, size); + + // write_protect_vgabios(); // in northbridge + + // check signature again + buf = (unsigned char *) 0xc0000; + if (buf[0]==0x55 && buf[1]==0xAA) { + busdevfn = (dev->bus->secondary << 8) | dev->path.u.pci.devfn; + printk_debug("bus/devfn = %#x\n", busdevfn); + + real_mode_switch_call_vga(busdevfn); + } else + printk_debug("Failed to copy VGA BIOS to 0xc0000\n"); + } else + printk_debug("BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]); + + pci_write_config32(dev, PCI_ROM_ADDRESS, 0); +} + + +// we had hoped to avoid this. +// this is a stub IDT only. It's main purpose is to ignore calls +// to the BIOS. +// no longer. Dammit. We have to respond to these. +struct realidt { + unsigned short offset, cs; +}; + +// from a handy writeup that andrey found. + +// handler. +// There are some assumptions we can make here. +// First, the Top Of Stack (TOS) is located on the top of page zero. +// we can share this stack between real and protected mode. +// that simplifies a lot of things ... +// we'll just push all the registers on the stack as longwords, +// and pop to protected mode. +// second, since this only ever runs as part of linuxbios, +// we know all the segment register values -- so we don't save any. +// keep the handler that calls things small. It can do a call to +// more complex code in linuxbios itself. This helps a lot as we don't +// have to do address fixup in this little stub, and calls are absolute +// so the handler is relocatable. +void handler(void) +{ + __asm__ __volatile__ ( + " .code16 \n" + "idthandle: \n" + " pushal \n" + " movb $0, %al \n" + " ljmp $0, $callbiosint16\n" + "end_idthandle: \n" + " .code32 \n" + ); +} + +void debughandler(void) +{ + __asm__ __volatile__ ( + " .code16 \n" + "debughandle: \n" + " pushw %cx \n" + " movw $250, %cx \n" + "dbh1: \n" + " loop dbh1 \n" + " popw %cx \n" + " iret \n" + "end_debughandle: \n" + ".code32 \n" + ); +} + +// Calling conventions. The first C function is called with this stuff +// on the stack. They look like value parameters, but note that if you +// modify them they will go back to the INTx function modified. +// the C function will call the biosint function with these as +// REFERENCE parameters. In this way, we can easily get +// returns back to the INTx caller (i.e. vgabios) +void callbiosint(void) +{ + __asm__ __volatile__ ( + " .code16 \n" + "callbiosint16: \n" + " push %ds \n" + " push %es \n" + " push %fs \n" + " push %gs \n" + // clean up the int #. To save space we put it in the lower + // byte. But the top 24 bits are junk. + " andl $0xff, %eax\n" + // this push does two things: + // - put the INT # on the stack as a parameter + // - provides us with a temp for the %cr0 mods. + " pushl %eax \n" + " movl %cr0, %eax\n" + " orl $0x00000001, %eax\n" /* PE = 1 */ + " movl %eax, %cr0\n" + /* Now that we are in protected mode jump to a 32 bit code segment. */ + " data32 ljmp $0x10, $biosprotect\n" + "biosprotect: \n" + " .code32 \n" + " movw $0x18, %ax \n" + " mov %ax, %ds \n" + " mov %ax, %es \n" + " mov %ax, %fs \n" + " mov %ax, %gs \n" + " mov %ax, %ss \n" + " lidt idtarg \n" + " call biosint \n" + // back to real mode ... + " ljmp $0x28, $__rms_16bit2\n" + "__rms_16bit2: \n" + " .code16 \n" + /* 16 bit code from here on... */ + /* Load the segment registers w/ properly configured segment + * descriptors. They will retain these configurations (limits, + * writability, etc.) once protected mode is turned off. */ + " mov $0x30, %ax \n" + " mov %ax, %ds \n" + " mov %ax, %es \n" + " mov %ax, %fs \n" + " mov %ax, %gs \n" + " mov %ax, %ss \n" + + /* Turn off protection (bit 0 in CR0) */ + " movl %cr0, %eax \n" + " andl $0xFFFFFFFE, %eax \n" + " movl %eax, %cr0 \n" + + /* Now really going into real mode */ + " ljmp $0, $__rms_real2 \n" + "__rms_real2: \n" + + /* Setup a stack + * FixME: where is esp? */ + " mov $0x0, %ax \n" + " mov %ax, %ss \n" + + /* ebugging for RGM */ + " mov $0x11, %al \n" + " outb %al, $0x80 \n" + + /* Load our 16 it idt */ + " xor %ax, %ax \n" + " mov %ax, %ds \n" + " lidt __myidt \n" + + /* Dump zeros in the other segregs */ + " mov %ax, %es \n" + " mov %ax, %fs \n" + " mov %ax, %gs \n" + " mov $0x40, %ax \n" + " mov %ax, %ds \n" + + /* pop the INT # that you pushed earlier */ + " popl %eax \n" + " pop %gs \n" + " pop %fs \n" + " pop %es \n" + " pop %ds \n" + " popal \n" + " iret \n" + " .code32 \n" + ); +} + +enum { + PCIBIOS = 0x1a, + MEMSIZE = 0x12 +}; + +int pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, + unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, + unsigned long *pecx, unsigned long *peax, unsigned long *pflags); + +int handleint21(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, + unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, + unsigned long *pecx, unsigned long *peax, unsigned long *pflags + ); + +extern void vga_exit(void); + +int biosint(unsigned long intnumber, + unsigned long gsfs, unsigned long dses, + unsigned long edi, unsigned long esi, + unsigned long ebp, unsigned long esp, + unsigned long ebx, unsigned long edx, + unsigned long ecx, unsigned long eax, + unsigned long cs_ip, unsigned short stackflags) +{ + unsigned long ip; + unsigned long cs; + unsigned long flags; + int ret = -1; + + ip = cs_ip & 0xffff; + cs = cs_ip >> 16; + flags = stackflags; + + printk_debug("biosint: INT# 0x%lx\n", intnumber); + printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", + eax, ebx, ecx, edx); + printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n", + ebp, esp, edi, esi); + printk_debug("biosint: ip 0x%x cs 0x%x flags 0x%x\n", + ip, cs, flags); + + // cases in a good compiler are just as good as your own tables. + switch (intnumber) { + case 0 ... 15: + // These are not BIOS service, but the CPU-generated exceptions + printk_info("biosint: Oops, exception %u\n", intnumber); + if (esp < 0x1000) { + printk_debug("Stack contents: "); + while (esp < 0x1000) { + printk_debug("0x%04x ", *(unsigned short *) esp); + esp += 2; + } + printk_debug("\n"); + } + printk_debug("biosint: Bailing out\n"); + // "longjmp" + vga_exit(); + break; + + case PCIBIOS: + ret = pcibios( &edi, &esi, &ebp, &esp, + &ebx, &edx, &ecx, &eax, &flags); + break; + case MEMSIZE: + // who cares. + eax = 64 * 1024; + ret = 0; + break; + case 0x15: + ret=handleint21( &edi, &esi, &ebp, &esp, + &ebx, &edx, &ecx, &eax, &flags); + break; + default: + printk_info("BIOSINT: Unsupport int #0x%x\n", + intnumber); + break; + } + if (ret) + flags |= 1; // carry flags + else + flags &= ~1; + stackflags = flags; + return ret; +} + + +void setup_realmode_idt(void) +{ + extern unsigned char idthandle, end_idthandle; + extern unsigned char debughandle, end_debughandle; + + int i; + struct realidt *idts = (struct realidt *) 0; + int codesize = &end_idthandle - &idthandle; + unsigned char *intbyte, *codeptr; + + // for each int, we create a customized little handler + // that just pushes %ax, puts the int # in %al, + // then calls the common interrupt handler. + // this necessitated because intel didn't know much about + // architecture when they did the 8086 (it shows) + // (hmm do they know anymore even now :-) + // obviously you can see I don't really care about memory + // efficiency. If I did I would probe back through the stack + // and get it that way. But that's really disgusting. + for (i = 0; i < 256; i++) { + idts[i].cs = 0; + codeptr = (char*) 4096 + i * codesize; + idts[i].offset = (unsigned) codeptr; + memcpy(codeptr, &idthandle, codesize); + intbyte = codeptr + 3; + *intbyte = i; + } + + // fixed entry points + + // VGA BIOSes tend to hardcode f000:f065 as the previous handler of + // int10. + // calling convention here is the same as INTs, we can reuse + // the int entry code. + codeptr = (char*) 0xff065; + memcpy(codeptr, &idthandle, codesize); + intbyte = codeptr + 3; + *intbyte = 0x42; /* int42 is the relocated int10 */ + + /* debug handler - useful to set a programmable delay between instructions if the + TF bit is set upon call to real mode */ + idts[1].cs = 0; + idts[1].offset = 16384; + memcpy(16384, &debughandle, &end_debughandle - &debughandle); + + +} + + + +enum { + CHECK = 0xb001, + FINDDEV = 0xb102, + READCONFBYTE = 0xb108, + READCONFWORD = 0xb109, + READCONFDWORD = 0xb10a, + WRITECONFBYTE = 0xb10b, + WRITECONFWORD = 0xb10c, + WRITECONFDWORD = 0xb10d +}; + +// errors go in AH. Just set these up so that word assigns +// will work. KISS. +enum { + PCIBIOS_NODEV = 0x8600, + PCIBIOS_BADREG = 0x8700 +}; + +int +pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, + unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, + unsigned long *pecx, unsigned long *peax, unsigned long *pflags) +{ + unsigned long edi = *pedi; + unsigned long esi = *pesi; + unsigned long ebp = *pebp; + unsigned long esp = *pesp; + unsigned long ebx = *pebx; + unsigned long edx = *pedx; + unsigned long ecx = *pecx; + unsigned long eax = *peax; + unsigned long flags = *pflags; + unsigned short func = (unsigned short) eax; + int retval = 0; + unsigned short devid, vendorid, devfn; + short devindex; /* Use short to get rid of gabage in upper half of 32-bit register */ + unsigned char bus; + device_t dev; + + switch(func) { + case CHECK: + *pedx = 0x4350; + *pecx = 0x2049; + retval = 0; + break; + case FINDDEV: + { + devid = *pecx; + vendorid = *pedx; + devindex = *pesi; + dev = 0; + while ((dev = dev_find_device(vendorid, devid, dev))) { + if (devindex <= 0) + break; + devindex--; + } + if (dev) { + unsigned short busdevfn; + *peax = 0; + // busnum is an unsigned char; + // devfn is an int, so we mask it off. + busdevfn = (dev->bus->secondary << 8) + | (dev->path.u.pci.devfn & 0xff); + printk_debug("0x%x: return 0x%x\n", func, busdevfn); + *pebx = busdevfn; + retval = 0; + } else { + *peax = PCIBIOS_NODEV; + retval = -1; + } + } + break; + case READCONFDWORD: + case READCONFWORD: + case READCONFBYTE: + case WRITECONFDWORD: + case WRITECONFWORD: + case WRITECONFBYTE: + { + unsigned long dword; + unsigned short word; + unsigned char byte; + unsigned char reg; + + devfn = *pebx & 0xff; + bus = *pebx >> 8; + reg = *pedi; + dev = dev_find_slot(bus, devfn); + if (! dev) { + printk_debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn); + // idiots. the pcibios guys assumed you'd never pass a bad bus/devfn! + *peax = PCIBIOS_BADREG; + retval = -1; + } + switch(func) { + case READCONFBYTE: + byte = pci_read_config8(dev, reg); + *pecx = byte; + break; + case READCONFWORD: + word = pci_read_config16(dev, reg); + *pecx = word; + break; + case READCONFDWORD: + dword = pci_read_config32(dev, reg); + *pecx = dword; + break; + case WRITECONFBYTE: + byte = *pecx; + pci_write_config8(dev, reg, byte); + break; + case WRITECONFWORD: + word = *pecx; + pci_write_config16(dev, reg, word); + break; + case WRITECONFDWORD: + dword = *pecx; + pci_write_config32(dev, reg, dword); + break; + } + + if (retval) + retval = PCIBIOS_BADREG; + printk_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n", + func, bus, devfn, reg, *pecx); + *peax = 0; + retval = 0; + } + break; + default: + printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func); + break; + } + + return retval; +} + +int handleint21(unsigned long *edi, unsigned long *esi, unsigned long *ebp, + unsigned long *esp, unsigned long *ebx, unsigned long *edx, + unsigned long *ecx, unsigned long *eax, unsigned long *flags) +{ + int res=-1; + switch(*eax&0xffff) + { + case 0x5f19: + break; + case 0x5f18: + *eax=0x5f; + *ebx=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory + *ecx=0x060; + res=0; + break; + case 0x5f00: + *eax = 0x8600; + break; + case 0x5f01: + *eax = 0x5f; + *ecx = (*ecx & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768 + res = 0; + break; + case 0x5f02: + *eax=0x5f; + *ebx= (*ebx & 0xffff0000) | 2; + *ecx= (*ecx & 0xffff0000) | 0x401; // PAL + crt only + *edx= (*edx & 0xffff0000) | 0; // TV Layout - default + res=0; + break; + case 0x5f0f: + *eax=0x860f; + break; + } + return res; +} Modified: trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.lb 2007-10-21 04:33:02 UTC (rev 2879) +++ trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config.lb 2007-10-22 10:07:46 UTC (rev 2880) @@ -12,8 +12,8 @@ romimage "image" option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION="-OpenBIOS" - payload /home/stepan/openbios.elf + option LINUXBIOS_EXTRA_VERSION="-GRUB2" + payload /home/stepan/core.img end buildrom ./qemu-bios.rom ROM_SIZE "image"

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coreboot October 2007