coreboot November 2006

coreboot@coreboot.org

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260 discussions

[LinuxBIOS] r2498 - in trunk/LinuxBIOSv2/src: mainboard/agami/aruma mainboard/amd/serengeti_cheetah mainboard/amd/serengeti_leopard mainboard/iwill/dk8_htx northbridge/amd/amdk8
by svn＠openbios.org 19 Nov '06

19 Nov '06

Author: stepan Date: 2006-11-19 20:24:06 +0100 (Sun, 19 Nov 2006) New Revision: 2498 Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Config.lb trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Config.lb trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Config.lb trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/Config.lb trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/Config.lb Log: Fix hardcoding of iasl path. iasl is in the user path in the pmtools packages of upcoming SUSE 10.2, too, so the problem will go away. (new package installed on linuxbios.org, too) See also http://www.linuxbios.org/pipermail/linuxbios/2006-September/015968.html Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Config.lb 2006-11-11 18:46:38 UTC (rev 2497) +++ trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Config.lb 2006-11-19 19:24:06 UTC (rev 2498) @@ -51,14 +51,14 @@ makerule dsdt.c depends "$(MAINBOARD)/dx/dsdt_lb.dsl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + action "iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl" action "mv dsdt_lb.hex dsdt.c" end object ./dsdt.o makerule ssdt.c depends "$(MAINBOARD)/ssdt_lb_x.dsl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/ssdt_lb_x.dsl" + action "iasl -tc $(MAINBOARD)/ssdt_lb_x.dsl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt_lb_x.hex" action "mv ssdt_lb_x.hex ssdt.c" end @@ -67,21 +67,21 @@ if ACPI_SSDTX_NUM makerule ssdt2.c depends "$(MAINBOARD)/dx/pci2.asl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci2.asl" + action "iasl -tc $(MAINBOARD)/dx/pci2.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" action "mv pci2.hex ssdt2.c" end object ./ssdt2.o makerule ssdt3.c depends "$(MAINBOARD)/dx/pci3.asl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci3.asl" + action "iasl -tc $(MAINBOARD)/dx/pci3.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex" action "mv pci3.hex ssdt3.c" end object ./ssdt3.o makerule ssdt4.c depends "$(MAINBOARD)/dx/pci4.asl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci4.asl" + action "iasl -tc $(MAINBOARD)/dx/pci4.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex" action "mv pci4.hex ssdt4.c" end Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Config.lb 2006-11-11 18:46:38 UTC (rev 2497) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Config.lb 2006-11-19 19:24:06 UTC (rev 2498) @@ -90,7 +90,7 @@ object fadt.o makerule dsdt.c depends "$(MAINBOARD)/dx/dsdt_lb.dsl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + action "iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl" action "mv dsdt_lb.hex dsdt.c" end object ./dsdt.o @@ -100,21 +100,21 @@ if ACPI_SSDTX_NUM makerule ssdt2.c depends "$(MAINBOARD)/dx/pci2.asl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci2.asl" + action "iasl -tc $(MAINBOARD)/dx/pci2.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" action "mv pci2.hex ssdt2.c" end object ./ssdt2.o makerule ssdt3.c depends "$(MAINBOARD)/dx/pci3.asl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci3.asl" + action "iasl -tc $(MAINBOARD)/dx/pci3.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex" action "mv pci3.hex ssdt3.c" end object ./ssdt3.o makerule ssdt4.c depends "$(MAINBOARD)/dx/pci4.asl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci4.asl" + action "iasl -tc $(MAINBOARD)/dx/pci4.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex" action "mv pci4.hex ssdt4.c" end Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Config.lb 2006-11-11 18:46:38 UTC (rev 2497) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Config.lb 2006-11-19 19:24:06 UTC (rev 2498) @@ -90,7 +90,7 @@ object fadt.o makerule dsdt.c depends "$(MAINBOARD)/dx/dsdt_lb.dsl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + action "iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl" action "mv dsdt_lb.hex dsdt.c" end object ./dsdt.o @@ -100,7 +100,7 @@ if ACPI_SSDTX_NUM makerule ssdt2.c depends "$(MAINBOARD)/dx/pci2.asl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci2.asl" + action "iasl -tc $(MAINBOARD)/dx/pci2.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" action "mv pci2.hex ssdt2.c" end Modified: trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/Config.lb 2006-11-11 18:46:38 UTC (rev 2497) +++ trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/Config.lb 2006-11-19 19:24:06 UTC (rev 2498) @@ -90,7 +90,7 @@ object fadt.o makerule dsdt.c depends "$(MAINBOARD)/dx/dsdt_lb.dsl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + action "iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl" action "mv dsdt_lb.hex dsdt.c" end object ./dsdt.o @@ -100,21 +100,21 @@ if ACPI_SSDTX_NUM makerule ssdt2.c depends "$(MAINBOARD)/dx/pci2.asl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci2.asl" + action "iasl -tc $(MAINBOARD)/dx/pci2.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" action "mv pci2.hex ssdt2.c" end object ./ssdt2.o makerule ssdt3.c depends "$(MAINBOARD)/dx/pci3.asl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci3.asl" + action "iasl -tc $(MAINBOARD)/dx/pci3.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex" action "mv pci3.hex ssdt3.c" end object ./ssdt3.o makerule ssdt4.c depends "$(MAINBOARD)/dx/pci4.asl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci4.asl" + action "iasl -tc $(MAINBOARD)/dx/pci4.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex" action "mv pci4.hex ssdt4.c" end Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/Config.lb 2006-11-11 18:46:38 UTC (rev 2497) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/Config.lb 2006-11-19 19:24:06 UTC (rev 2498) @@ -21,7 +21,7 @@ object amdk8_acpi.o makerule ssdt.c depends "$(TOP)/src/northbridge/amd/amdk8/ssdt.dsl" - action "/usr/sbin/iasl -tc $(TOP)/src/northbridge/amd/amdk8/ssdt.dsl" + action "iasl -tc $(TOP)/src/northbridge/amd/amdk8/ssdt.dsl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex" action "mv ssdt.hex ssdt.c" end

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[LinuxBIOS] My first attempt at linuxbios
by Jon Dufresne 19 Nov '06

19 Nov '06

Hello, I am creating an embedded system. Right now I am investigating different custom bioses and am seriously considering LinuxBIOS. Let me give you a rundown of the hardware I am using CPU: Pentium M Mainboard: Custom board based on BCM GT855 Northbridge: Intel 855GME Southbridge: Intel 82801DB SuperIO: ITE IT8712-F In the source tree it looks like there is some level of soupport for all these devices except the mainboard. I am going to attempt to create a mainboard and target to get this setup working. One thing I want to do is build a minimal target and then implement the features incrementally. With this is mind, do I need to create any source code for the initial run or is the entire build defined by the Config.lb and Options.lb? I've read through all the documentation I could find on th website so I think I have a decent idea about how the LinuxBIOS system works. I believe my payload will be FILO. In the end my system will be booting RHEL. I'm willing to put a lot of work into this, but I want to see what others thought about compatibility with this hardware setup. While I'm here, what is the difference between the Config.lb and the Options.lb file. They both look like they set configuations/optoins, but I am not sure what options/configuations go in which file. Thanks for the great soft/firmware and thanks for any feedback. -Jon If you're interested here is the output from lspci -vvvxxx 00:00.0 Host bridge: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) Subsystem: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- Latency: 0 Region 0: Memory at e0000000 (32-bit, prefetchable) [size=256M] Capabilities: [40] Vendor Specific Information Capabilities: [a0] AGP version 2.0 Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW+ AGP3- Rate=x1,x2,x4 Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=x1 00: 86 80 80 35 06 01 90 20 02 00 00 06 00 00 80 00 10: 08 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 80 35 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 a0 05 81 00 00 00 00 00 00 c1 fe 02 28 00 0e 50: 00 01 44 00 00 00 00 00 00 10 11 11 00 00 00 00 60: 0a 39 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 02 09 00 00 56 60 00 02 01 00 80 00 00 00 00 00 80: 02 00 00 a4 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 02 00 20 00 17 02 00 1f 01 00 00 00 00 00 00 00 b0: 00 00 f0 e9 00 00 00 00 00 00 00 00 20 10 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 02 00 09 01 00 00 00:00.1 System peripheral: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) Subsystem: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00: 86 80 84 35 06 00 80 00 02 00 80 08 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 84 35 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 10 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 50: 33 77 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 44 00 2a 00 00 00 00 30 04 f1 10 00 00 00 00 70: 71 99 00 20 01 00 00 00 74 e9 1f 00 00 00 00 00 80: 39 00 af 00 3c 03 00 00 10 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 84 c6 5a df 46 00 4e 40 a0: ff a2 0a 30 00 00 00 00 7a 15 02 00 00 00 00 00 b0: 00 00 00 00 8a c1 a7 00 2c 52 00 00 fc a3 c7 05 c0: 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:00.3 System peripheral: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) Subsystem: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00: 86 80 85 35 06 00 80 00 02 00 80 08 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 85 35 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 04 04 00 00 00 00 11 11 3c 4c 62 09 4b 60 09 4b 50: 60 09 00 00 00 00 00 00 01 08 39 2d 30 33 02 0b 60: 00 00 00 00 00 00 00 00 04 04 00 00 2d 41 00 00 70: 00 00 00 00 04 04 41 27 e7 c7 0f 7f 7f 00 84 02 80: ff 1f 00 00 ef 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 80 13 1f 00 00 00 00 b0: 00 00 00 00 80 02 00 00 00 00 00 00 00 00 00 00 c0: 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 00 21 02 00 00 00 00 08 c3 00 ff 25 00 00 00 e0: 2a 00 1f 00 98 00 9f 00 00 00 00 00 00 04 00 00 f0: 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 00:01.0 PCI bridge: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to AGP Controller (rev 02) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=32 I/O behind bridge: 0000e000-0000efff Memory behind bridge: fdc00000-fdcfffff Prefetchable memory behind bridge: fdb00000-fdbfffff Secondary status: 66Mhz+ FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 00: 86 80 81 35 07 00 a0 00 02 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 20 e0 e0 a0 22 20: c0 fd c0 fd b0 fd b0 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.0 VGA compatible controller: Intel Corporation 82852/855GM Integrated Graphics Device (rev 02) (prog-if 00 [VGA]) Subsystem: Intel Corporation 82852/855GM Integrated Graphics Device Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 169 Region 0: Memory at f0000000 (32-bit, prefetchable) [size=128M] Region 1: Memory at fdf00000 (32-bit, non-prefetchable) [size=512K] Region 2: I/O ports at ff00 [size=8] Capabilities: [d0] Power Management version 1 Flags: PMEClk- DSI+ D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 86 80 82 35 07 00 90 00 02 00 00 03 00 00 80 00 10: 08 00 00 f0 00 00 f0 fd 01 ff 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 82 35 30: 00 00 00 00 d0 00 00 00 00 00 00 00 0a 01 00 00 40: 09 a0 05 81 00 40 00 00 00 00 00 00 00 00 00 00 50: 00 01 44 00 00 00 00 00 00 00 02 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: ff a2 0a 30 00 00 00 00 0e 1c 02 00 00 00 00 00 b0: 00 00 00 00 74 06 a8 00 1c 59 00 00 64 0c c9 05 c0: 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 00 21 02 00 00 00 00 08 c3 00 ff 25 00 00 00 e0: 2a 00 1f 00 98 00 9f 00 00 00 00 00 00 04 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.1 Display controller: Intel Corporation 82852/855GM Integrated Graphics Device (rev 02) Subsystem: Intel Corporation 82852/855GM Integrated Graphics Device Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Region 0: Memory at 40000000 (32-bit, prefetchable) [size=128M] Region 1: Memory at 48000000 (32-bit, non-prefetchable) [size=512K] Capabilities: [d0] Power Management version 1 Flags: PMEClk- DSI+ D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 86 80 82 35 02 00 90 00 02 00 80 03 00 00 80 00 10: 08 00 00 40 00 00 00 48 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 82 35 30: 00 00 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 40: 09 a0 05 81 00 40 00 00 00 00 00 00 00 00 00 00 50: 00 01 44 00 00 00 00 00 00 00 02 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: ff a2 0a 30 00 00 00 00 4a 1c 02 00 00 00 00 00 b0: 00 00 00 00 c4 0f a8 00 8c 59 00 00 ac 5a c9 05 c0: 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 00 21 02 00 00 00 00 08 c3 00 ff 25 00 00 00 e0: 2a 00 1f 00 98 00 9f 00 00 00 00 00 00 04 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:1d.0 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1 (rev 02) (prog-if 00 [UHCI]) Subsystem: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 169 Region 4: I/O ports at fe00 [size=32] 00: 86 80 c2 24 05 00 80 02 02 00 03 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 fe 00 00 00 00 00 00 00 00 00 00 86 80 c2 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 27 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00 00:1d.1 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #2 (rev 02) (prog-if 00 [UHCI]) Subsystem: Intel Corporation: Unknown device 24c2 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin B routed to IRQ 177 Region 4: I/O ports at fd00 [size=32] 00: 86 80 c4 24 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 fd 00 00 00 00 00 00 00 00 00 00 86 80 c2 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 27 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00 00:1d.2 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #3 (rev 02) (prog-if 00 [UHCI]) Subsystem: Intel Corporation: Unknown device 24c2 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin C routed to IRQ 185 Region 4: I/O ports at fc00 [size=32] 00: 86 80 c7 24 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 fc 00 00 00 00 00 00 00 00 00 00 86 80 c2 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 03 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 27 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00 00:1d.7 USB Controller: Intel Corporation 82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller (rev 02) (prog-if 20 [EHCI]) Subsystem: Intel Corporation 82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin D routed to IRQ 193 Region 0: Memory at fdfff000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 86 80 cd 24 06 00 90 02 02 20 03 0c 00 00 00 00 10: 00 f0 ff fd 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 cd 24 30: 00 00 00 00 50 00 00 00 00 00 00 00 09 04 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 c2 c9 00 00 00 00 0a 00 80 20 00 00 00 00 60: 20 20 7f 00 00 00 00 00 01 00 00 00 00 00 08 80 70: 00 00 c5 0f 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3f 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 78 bf 1f 00 88 83 00 00 60 0f 00 00 06 00 00 00 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 82) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR+ Latency: 0 Bus: primary=00, secondary=02, subordinate=02, sec-latency=32 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: fde00000-fdefffff Prefetchable memory behind bridge: fdd00000-fddfffff Secondary status: 66Mhz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 00: 86 80 4e 24 07 00 80 80 82 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 20 d0 d0 80 22 20: e0 fd e0 fd d0 fd d0 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 02 28 20 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 02 74 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 10 00 08 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 01 00 02 00 00 00 c0 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 52 2c 00:1f.0 ISA bridge: Intel Corporation 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge (rev 02) Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00: 86 80 c0 24 0f 00 80 02 02 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 04 00 00 10 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 08 00 00 00 81 04 00 00 10 00 00 00 60: 8a 85 8b 8a d0 00 00 00 8b 80 80 89 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 55 54 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 20 02 00 00 00 00 00 00 12 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 55 15 41 09 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 86 29 20 00 02 0f 00 00 04 00 00 00 00 00 00 00 e0: 10 00 00 c0 01 08 03 34 33 22 11 00 91 02 67 45 f0: 0f 00 40 00 00 00 00 00 60 0f 02 00 00 00 81 00 00:1f.1 IDE interface: Intel Corporation 82801DB (ICH4) IDE Controller (rev 02) (prog-if 8a [Master SecP PriP]) Subsystem: Intel Corporation: Unknown device 24c2 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 185 Region 0: I/O ports at <unassigned> Region 1: I/O ports at <unassigned> Region 2: I/O ports at <unassigned> Region 3: I/O ports at <unassigned> Region 4: I/O ports at fb00 [size=16] Region 5: Memory at 48080000 (32-bit, non-prefetchable) [size=1K] 00: 86 80 cb 24 07 00 80 02 02 8a 01 01 00 00 00 00 10: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 20: 01 fb 00 00 00 00 08 48 00 00 00 00 86 80 c2 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 01 00 00 40: 00 80 07 a3 00 00 00 00 04 00 00 02 00 00 00 00 50: 00 00 00 00 00 04 00 00 00 00 00 00 00 00 00 00 60: 08 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00 00:1f.3 SMBus: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller (rev 02) Subsystem: Intel Corporation: Unknown device 24c2 Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin B routed to IRQ 201 Region 4: I/O ports at 0500 [size=32] 00: 86 80 c3 24 01 00 80 02 02 00 05 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 05 00 00 00 00 00 00 00 00 00 00 86 80 c2 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 05 02 00 00 40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00 00:1f.5 Multimedia audio controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Audio Controller (rev 02) Subsystem: Unknown device 414c:4770 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin B routed to IRQ 201 Region 0: I/O ports at f400 [size=256] Region 1: I/O ports at f900 [size=64] Region 2: Memory at fdffe000 (32-bit, non-prefetchable) [size=512] Region 3: Memory at fdffd000 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 86 80 c5 24 07 00 90 02 02 00 01 04 00 00 00 00 10: 01 f4 00 00 01 f9 00 00 00 e0 ff fd 00 d0 ff fd 20: 00 00 00 00 00 00 00 00 00 00 00 00 4c 41 70 47 30: 00 00 00 00 50 00 00 00 00 00 00 00 05 02 00 00 40: 09 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 c2 c9 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00 02:08.0 Ethernet controller: Intel Corporation 82801DB PRO/100 VE (LOM) Ethernet Controller (rev 82) Subsystem: Intel Corporation: Unknown device 0001 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (2000ns min, 14000ns max), Cache Line Size 08 Interrupt: pin A routed to IRQ 209 Region 0: Memory at fdeff000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at df00 [size=64] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=2 PME- 00: 86 80 39 10 07 00 90 02 82 00 00 02 08 40 00 00 10: 00 f0 ef fd 01 df 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 01 00 30: 00 00 00 00 dc 00 00 00 00 00 00 00 0b 01 08 38 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 22 fe e0: 00 40 00 3a 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

4 3

[LinuxBIOS] How to add support to a Hyper Transport card
by Moses Reuben 19 Nov '06

19 Nov '06

Hi all I have a HT nic (this is a new card) and i want the bios to support it what should i change in the code && configuration . I have a Iwill/dk8_htx board. Thanks

3 4

[LinuxBIOS] port 80h pci board
by Shaddam Corrino IV 18 Nov '06

18 Nov '06

Hello, Does anyone here has MSD's port 80h pci board? It is model PCIPCM-11. If you do, can you PLEASE send me a high resolution photo of the B side (circuit side). Their current offering seems to be PCIPCM-15, which is more recent than my board: http://www.postcodemaster.com/products2.htm#PCIPCM11 PS: This below should be a nice trick to write to port 80h from user space (untested): printf "\001" | dd bs=1 seek=128 of=/dev/port -- Thanks! Shaddam IV

3 2

[LinuxBIOS] flashrom: patch for jedec.c
by Giampiero Giancipoli 18 Nov '06

18 Nov '06

Hi to all, I used flashrom to flash the BIOS on a AxiomTek SBC84500, which mounts a Winbond W29C020C. All is recognized fine, but the flashing fails. # flashrom -v -w axiom.bin No LinuxBIOS table found. Enabling flash write on CS5530...OK W29C020C found at physical address: 0xfffc0000 Flash part is S29C51002T (256 KB) Flash image seems to be a legacy BIOS. Disabling checks. Programming Page: 2047 at address: 0x0003ff80 Verifying flash - FAILED. Trying fo find out the cause of the failure I eventually found a grave error in jedec.c, at write_page_write_jedec(). The code: if (*src == 0xFF) continue; *dst++ = *src++; is, of course, wrong. It should be if (*src != 0xFF ) *dst = *src; dst++; src++; I include a patch which fixes this error. But this is not enough. Sector writes sometimes fail, so included a check/rewrite code similar to write_byte_program_jedec(). Maybe this is not the best way to do the task, but at least for me works :) Furthermore, the patch adds support for the SyncMos S29C51002T 256K flash. Tested successfully on a Boser HS-2603. It is high probable that the same configuration would work with all the chips of the same family. # flashrom -v -w boser.bin No LinuxBIOS table found. Enabling flash write on CS5530...OK S29C51002T found at physical address: 0xfffc0000 Flash part is S29C51002T (256 KB) Flash image seems to be a legacy BIOS. Disabling checks. Programming Page: 2047 at address: 0x0003ff80 Verifying flash - VERIFIED That's all. Ciao.

7 15

Re: [LinuxBIOS] LinuxBIOSv2/util/flashrom
by Uwe Hermann 18 Nov '06

18 Nov '06

Hi, [please always write to the mailing list, there are more people there who can timely respond] On Wed, Nov 15, 2006 at 01:07:57PM +0000, Idwer Vollering wrote: > (I guess e-mail is more suitable than icq..) > > (http://tracker.linuxbios.org/trac/LinuxBIOS/browser/trunk/LinuxBIOSv2/util/…) > > How do i add code-wise support for several dip-32 flashroms ? Usually you have to add the vendor/device number in flash.h and then some entries in flashchips.c. Depending on your mainboard maybe you also need to add support in flash_enable.c. > Lying in front of me are: > > Intel P28F001-BXT150: > http://pdf1.alldatasheet.com/datasheet-pdf/view/66052/INTEL/P28F001BX-T150/… > > ST M29F002NT-120P1 -- couldn't find a exact datasheet about this one :( > except http://www.datasheets.org.uk/specsheet.php?part=M29F002T120P1 The vendor should have a datasheet: http://www.st.com Or: http://www.datasheets.org.uk/search.php?q=M29F002NT-90XK6TR&sType=part HTH, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

3 2

[LinuxBIOS] MSI RS482M – IL
by Randall Philipson 17 Nov '06

17 Nov '06

I would like to develop LinuxBIOS support for the MSI RS482M – IL motherboard with the following Sempron 3000+ (Rev E), 1.8GHz 512MB DDR1-400 ATI RS482M + SB400 chipset I haven't had any luck finding any datasheets for the ATI chipset, so I'm worried that this may be an uphill battle. I have access to a programmer so I can program BIOS chips to my hearts content, don't have a POST card though, may need to look into that. I don't have the board yet, it should be coming in within the next couple of weeks. I guess what I'm asking is, based on the vast amount of experience in this group, is this a reasonably achievable goal. I've been monitoring this list for a while and despite some fairly decent programming skills I have, LinuxBIOS has me somewhat stumped, so if I go this route there may be a lot of stupid questions hitting the list. Thanks for any guidance, Randy Philipson

2 1

[LinuxBIOS] More payloads?
by Uwe Hermann 16 Nov '06

16 Nov '06

Hi, for the wiki: Do we have confirmed boots of any payloads not yet listed in the wiki? E.g. Open Firmware, GNUFI, GRUB2, etc? If yes, they should be added to the front page. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

1 0

Re: [LinuxBIOS] Failure with Tyan K8WE S2895
by Lu, Yinghai 16 Nov '06

16 Nov '06

1. Mem size? 2. Linux Kernel version when you are flashing linuxbios.rom? 3. you need to use tiny kernel to boot from SATA. YH

3 2

[LinuxBIOS] google, qa.linuxbios.org
by David H. Barr 16 Nov '06

16 Nov '06

From... http://google-code-updates.blogspot.com/2006/11/ google-sponsors-linuxbios-project.html ...by way of... http://www.linuxbios.org/Press "Anyone with a spare board supported by LinuxBIOS is welcome to put it into the automated test system, thus helping the LinuxBIOS project increase their quality on your hardware." More details? Let's say, for instance, that I wanted to donate a test board for one or more of the soon-to-be AM2 desktops; how would I go about accomplishing this? -dhbarr.

4 5

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coreboot November 2006