coreboot October 2006

coreboot@coreboot.org

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208 discussions

Re: [LinuxBIOS] Tyan s2892 the OLPC way
by Lu, Yinghai 18 Oct '06

18 Oct '06

Or modify you cache_as_ram_auto.c failover.c, force it to jump to fallback only for safe. YH -----Original Message----- From: Myles Watson [mailto:myles@mouselemur.cs.byu.edu] Sent: Wednesday, October 18, 2006 11:28 AM To: Lu, Yinghai Subject: RE: [LinuxBIOS] Tyan s2892 the OLPC way That was it. When should I have to do that? Myles > -----Original Message----- > From: Lu, Yinghai [mailto:yinghai.lu@amd.com] > Sent: Wednesday, October 18, 2006 12:16 PM > To: myles(a)mouselemur.cs.byu.edu > Subject: RE: [LinuxBIOS] Tyan s2892 the OLPC way > > Clear your CMOS by using the hw jump. > > YH > > -----Original Message----- > From: Myles Watson [mailto:myles@mouselemur.cs.byu.edu] > Sent: Wednesday, October 18, 2006 11:14 AM > To: Lu, Yinghai > Subject: RE: [LinuxBIOS] Tyan s2892 the OLPC way > > Yes. > > I checked and the first few bytes of the image are AA55, like they > should > be. > > Myles > > > -----Original Message----- > > From: Lu, Yinghai [mailto:yinghai.lu@amd.com] > > Sent: Wednesday, October 18, 2006 12:07 PM > > To: myles(a)mouselemur.cs.byu.edu; ron minnich > > Subject: RE: [LinuxBIOS] Tyan s2892 the OLPC way > > > > Are you using "cat atix.rom linuxbios.rom > s2892_linuxbios.rom" to > get > > final rom? > > > > YH > > > > > > > >

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Re: [LinuxBIOS] Tyan s2892 the OLPC way
by Myles Watson 18 Oct '06

18 Oct '06

Do we need a new variable FALLBACK_ONLY ? I put together the attached patch to try to modify it nicely, but I'm not sure it works as I intended. I wanted to only try to jump to normal when there is a normal, but the variables are all FALLBACK-oriented. Myles > Or modify you cache_as_ram_auto.c failover.c, force it to jump to > fallback only for safe. > > YH > > That was it. When should I have to do that? > > Myles > > > -----Original Message----- > > From: Lu, Yinghai [mailto:yinghai.lu@amd.com] > > Sent: Wednesday, October 18, 2006 12:16 PM > > To: myles(a)mouselemur.cs.byu.edu > > Subject: RE: [LinuxBIOS] Tyan s2892 the OLPC way > > > > Clear your CMOS by using the hw jump.

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[LinuxBIOS] r2461 - trunk/LinuxBIOSv2/src/mainboard/olpc/btest
by svn＠openbios.org 18 Oct '06

18 Oct '06

Author: rminnich Date: 2006-10-18 18:00:10 +0200 (Wed, 18 Oct 2006) New Revision: 2461 Modified: trunk/LinuxBIOSv2/src/mainboard/olpc/btest/mainboard.c Log: add the CAFE IRQ support Modified: trunk/LinuxBIOSv2/src/mainboard/olpc/btest/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/olpc/btest/mainboard.c 2006-10-18 15:46:24 UTC (rev 2460) +++ trunk/LinuxBIOSv2/src/mainboard/olpc/btest/mainboard.c 2006-10-18 16:00:10 UTC (rev 2461) @@ -68,6 +68,33 @@ write_bit(rev > 0 ? 1 : 0); } +void +init_cafe_irq(void){ + const unsigned char slots_cafe[4] = {11, 0, 0, 0}; + + + /* CAFE PCI slots */ + pci_assign_irqs(0, 0x0C, slots_cafe); + + /* Make the pin assignments - NOTENOTENOTE: This should be + * configurable! + */ + + /* Configure the GPIO pins to use - class 0, index 9 to configure + * AB. Write 0xFF to disable + */ + + vrWrite(0x9, 0XFF00); + + /* Configure the GPIO pins to use - class 0, index A to configure + * CD. Write 0xFF to disable + */ + + vrWrite(0xA, 0xFFFF); + +} + + static void init(struct device *dev) { /* unsigned bus = 0; @@ -94,6 +121,7 @@ #endif init_dcon(); + init_cafe_irq(); printk_debug("OLPC BTEST EXIT %s\n", __FUNCTION__); }

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[LinuxBIOS] r2460 - in trunk/LinuxBIOSv2/targets/olpc: . btest
by svn＠openbios.org 18 Oct '06

18 Oct '06

Author: rminnich Date: 2006-10-18 17:46:24 +0200 (Wed, 18 Oct 2006) New Revision: 2460 Added: trunk/LinuxBIOSv2/targets/olpc/btest/ trunk/LinuxBIOSv2/targets/olpc/btest/Config.lb Log: add btest mainboard Added: trunk/LinuxBIOSv2/targets/olpc/btest/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/olpc/btest/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/olpc/btest/Config.lb 2006-10-18 15:46:24 UTC (rev 2460) @@ -0,0 +1,24 @@ +# Config file for the olpc btest + +target btest +mainboard olpc/btest + +# Don't let LinuxBIOS compress the payload +#option CONFIG_COMPRESSED_ROM_STREAM_NRV2B=0 +#option CONFIG_COMPRESSED_ROM_STREAM_LZMA=1 +#option CONFIG_PRECOMPRESSED_ROM_STREAM=0 + +# leave 64k for vsa and 64k for EC code +option ROM_SIZE=(1024*1024)-(64*1024)-(64*1024) +option FALLBACK_SIZE=ROM_SIZE + +option DEFAULT_CONSOLE_LOGLEVEL = 11 +option MAXIMUM_CONSOLE_LOGLEVEL = 11 +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=32*1024 + option LINUXBIOS_EXTRA_VERSION=".0Fallback" + payload /tmp/olpcpayload.elf +end + +buildrom ./linuxbios.rom ROM_SIZE "fallback"

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[LinuxBIOS] r2459 - in trunk/LinuxBIOSv2/src/mainboard/olpc: . btest
by svn＠openbios.org 18 Oct '06

18 Oct '06

Author: rminnich Date: 2006-10-18 17:23:28 +0200 (Wed, 18 Oct 2006) New Revision: 2459 Added: trunk/LinuxBIOSv2/src/mainboard/olpc/btest/ trunk/LinuxBIOSv2/src/mainboard/olpc/btest/Config.lb trunk/LinuxBIOSv2/src/mainboard/olpc/btest/Options.lb trunk/LinuxBIOSv2/src/mainboard/olpc/btest/auto.c trunk/LinuxBIOSv2/src/mainboard/olpc/btest/chip.h trunk/LinuxBIOSv2/src/mainboard/olpc/btest/cmos.layout trunk/LinuxBIOSv2/src/mainboard/olpc/btest/debug.c trunk/LinuxBIOSv2/src/mainboard/olpc/btest/failover.c trunk/LinuxBIOSv2/src/mainboard/olpc/btest/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/olpc/btest/mainboard.c trunk/LinuxBIOSv2/src/mainboard/olpc/btest/reset.c Log: add the btest mainboard Added: trunk/LinuxBIOSv2/src/mainboard/olpc/btest/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/olpc/btest/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/olpc/btest/Config.lb 2006-10-18 15:23:28 UTC (rev 2459) @@ -0,0 +1,170 @@ +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +if HAVE_PIRQ_TABLE object irq_tables.o end +#object reset.o + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit ./auto.inc + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +chip northbridge/amd/gx2 + register "irqmap" = "0xaa5b" + register "setupflash" = "0" + device apic_cluster 0 on + chip cpu/amd/model_gx2 + device apic 0 on end + end + end + device pci_domain 0 on + device pci 1.0 on end + device pci 1.1 on end + chip southbridge/amd/cs5536 + # 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080. + # Frame Pulse Width = 4clocks + # IRQ Data Frames = 17Frames + # SIRQ Mode = continous , It would be better if the EC could operate in + # Active(Quiet) mode. Save power.... + # SIRQ Enable = Enabled + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + register "lpc_irq" = "0x00001002" + register "lpc_serirq_enable" = "0xEFFD0080" + register "enable_gpio0_inta" = "1" + register "enable_ide_nand_flash" = "1" + register "enable_uarta" = "1" + register "enable_USBP4_host" = "1" + register "audio_irq" = "5" + register "usbf4_irq" = "10" + register "usbf5_irq" = "10" + register "usbf6_irq" = "0" + register "usbf7_irq" = "0" + device pci d.0 on end # Realtek 8139 LAN + device pci f.0 on end # ISA Bridge + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC + register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG + register "unwanted_vpci[2]" = "0" # End of list has a zero + end + end +end + Added: trunk/LinuxBIOSv2/src/mainboard/olpc/btest/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/olpc/btest/Options.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/olpc/btest/Options.lb 2006-10-18 15:23:28 UTC (rev 2459) @@ -0,0 +1,163 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_STREAM +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_STREAM_START +uses CONFIG_COMPRESSED_ROM_STREAM_NRV2B +uses CONFIG_COMPRESSED_ROM_STREAM_LZMA +uses CONFIG_PRECOMPRESSED_ROM_STREAM +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + +## ROM_SIZE is the size of boot ROM that this board will use. +default ROM_SIZE = 256*1024 + +### +### Build options +### + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## no MP table +## +default HAVE_MP_TABLE=0 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=0 + +## Delay timer options +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=2 +#object irq_tables.o + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=0 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 +default FALLBACK_SIZE = 131072 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 + +default _RAMBASE = 0x00004000 + +default CONFIG_ROM_STREAM = 1 + +## +## The default compiler +## +default CROSS_COMPILE="" +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +end + Added: trunk/LinuxBIOSv2/src/mainboard/olpc/btest/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/olpc/btest/auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/olpc/btest/auto.c 2006-10-18 15:23:28 UTC (rev 2459) @@ -0,0 +1,193 @@ +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" +#include "cpu/x86/bist.h" +#include "cpu/x86/msr.h" +#include <cpu/amd/gx2def.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +#include "southbridge/amd/cs5536/cs5536_early_smbus.c" +#include "southbridge/amd/cs5536/cs5536_early_setup.c" + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/gx2/raminit.h" + +static inline unsigned int fls(unsigned int x) +{ + int r; + + __asm__("bsfl %1,%0\n\t" + "jnz 1f\n\t" + "movl $32,%0\n" + "1:" : "=r" (r) : "g" (x)); + return r; +} + + + + +/* sdram parameters for OLPC: + row address = 13 + col address = 9 + banks = 4 + dimm0size=128MB + d0_MB=1 (module banks) + d0_cb=4 (component banks) + do_psz=4KB (page size) + Trc=10 (clocks) (ref2act) + Tras=7 (act2pre) + Trcd=3 (act2cmd) + Trp=3 (pre2act) + Trrd=2 (act2act) + Tref=17.8ms + */ +static void sdram_set_spd_registers(const struct mem_controller *ctrl) +{ + /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) * + * component Banks (byte 17) * module banks, side (byte 5) * + * width in bits (byte 6,7) + * = Density per side (byte 31) * number of sides (byte 5) */ + /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */ + msr_t msr; + unsigned char module_banks, val; + + msr = rdmsr(MC_CF07_DATA); + + /* get module banks (sides) per dimm, SPD byte 5 */ + module_banks = 1; + module_banks >>= 1; + msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT); + msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT); + + /* get component banks per module bank, SPD byte 17 */ + val = 4; + val >>= 2; + msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT); + msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT); + + /* get the module bank density, SPD byte 31 */ + /* this is multiples of 8 MB */ + /* actually it is 2^x*4, where x is the value you put in */ + /* for OLPC, set default size */ + /* dimm size - hardcoded 128Mb */ + val = 5; + msr.hi &= ~(0xf << CF07_UPPER_D0_SZ_SHIFT); + msr.hi |= (val << CF07_UPPER_D0_SZ_SHIFT); + + /* page size = 2^col address */ + val = 2; /* 4096 bytes */ + msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT); + msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT); + + print_debug("computed msr.hi "); + print_debug_hex32(msr.hi); + print_debug("\r\n"); + + /* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */ + /* well, it may be close. It's about 200,000 ticks */ + msr.lo = 0x00003000; + wrmsr(MC_CF07_DATA, msr); + + /* timing and mode ... */ + + msr = rdmsr(0x20000019); + + /* per standard bios settings */ + + msr.hi = 0x18000108; + msr.lo = + (6<<28) | // cas_lat + (10<<24)| // ref2act + (7<<20)| // act2pre + (3<<16)| // pre2act + (3<<12)| // act2cmd + (2<<8)| // act2act + (2<<6)| // dplwr + (2<<4)| // dplrd + (3); // dal + /* the msr value reported by quanta is very, very different. + * we will go with that value for now. + */ + msr.lo = 0x286332a3; + + wrmsr(0x20000019, msr); + +} + +#include "northbridge/amd/gx2/raminit.c" +#include "sdram/generic_sdram.c" + +#define PLLMSRhi 0x00001490 +#define PLLMSRlo 0x02000030 +#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24)) +#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0)) +#include "northbridge/amd/gx2/pll_reset.c" +#include "cpu/amd/model_gx2/cpureginit.c" +#include "cpu/amd/model_gx2/syspreinit.c" +static void msr_init(void) +{ + __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02); + + __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); + __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); + + __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); + __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); +} + +static void gpio_init(void) +{ + unsigned long m; + + /* Make sure events enable for gpio 12 is off */ + + m = inl(GPIOL_EVENTS_ENABLE); + m &= ~GPIOL_12_SET; + m |= GPIOL_12_CLEAR; + outl(m, GPIOL_EVENTS_ENABLE); +} + +static void main(unsigned long bist) +{ + static const struct mem_controller memctrl [] = { + {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + /* NOTE: must do this AFTER the early_setup! + * it is counting on some early MSR setup + * for cs5536 + */ + cs5536_setup_onchipuart(); + gpio_init(); + uart_init(); + console_init(); + + pll_reset(); + + cpuRegInit(); + print_err("done cpuRegInit\n"); + + sdram_initialize(1, memctrl); + + /* Check all of memory */ + //ram_check(0x00000000, 640*1024); +} Added: trunk/LinuxBIOSv2/src/mainboard/olpc/btest/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/olpc/btest/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/olpc/btest/chip.h 2006-10-18 15:23:28 UTC (rev 2459) @@ -0,0 +1,5 @@ +extern struct chip_operations mainboard_olpc_btest_ops; + +struct mainboard_olpc_btest_config { + int nothing; +}; Added: trunk/LinuxBIOSv2/src/mainboard/olpc/btest/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/olpc/btest/cmos.layout (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/olpc/btest/cmos.layout 2006-10-18 15:23:28 UTC (rev 2459) @@ -0,0 +1,75 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 1 e 0 dcon_present +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + Added: trunk/LinuxBIOSv2/src/mainboard/olpc/btest/debug.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/olpc/btest/debug.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/olpc/btest/debug.c 2006-10-18 15:23:28 UTC (rev 2459) @@ -0,0 +1,66 @@ + +static void print_debug_pci_dev(unsigned dev) +{ + print_debug("PCI: "); + print_debug_hex8((dev >> 16) & 0xff); + print_debug_char(':'); + print_debug_hex8((dev >> 11) & 0x1f); + print_debug_char('.'); + print_debug_hex8((dev >> 8) & 7); +} + +static void print_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + print_debug_pci_dev(dev); + print_debug("\r\n"); + } +} + +static void dump_pci_device(unsigned dev) +{ + int i; + print_debug_pci_dev(dev); + print_debug("\r\n"); + + for(i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\r\n"); + } + } +} + +static void dump_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } +} Added: trunk/LinuxBIOSv2/src/mainboard/olpc/btest/failover.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/olpc/btest/failover.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/olpc/btest/failover.c 2006-10-18 15:23:28 UTC (rev 2459) @@ -0,0 +1,34 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include "arch/romcc_io.h" +#include "pc80/mc146818rtc_early.c" + +static unsigned long main(unsigned long bist) +{ +#if 0 + /* This is the primary cpu how should I boot? */ + if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: +#endif + return bist; +} Added: trunk/LinuxBIOSv2/src/mainboard/olpc/btest/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/olpc/btest/irq_tables.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/olpc/btest/irq_tables.c 2006-10-18 15:23:28 UTC (rev 2459) @@ -0,0 +1,31 @@ +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up + * + * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*2, /* there can be total 2 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0x800, /* IRQs devoted exclusively to PCI usage */ + 0x1078, /* Vendor */ + 0x2, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, + } +}; +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/LinuxBIOSv2/src/mainboard/olpc/btest/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/olpc/btest/mainboard.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/olpc/btest/mainboard.c 2006-10-18 15:23:28 UTC (rev 2459) @@ -0,0 +1,109 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <pc80/mc146818rtc.h> +#include "chip.h" +#include "../southbridge/amd/cs5536/cs5536_smbus2.h" + +/* Borrowed from mc146818rtc.c */ + +#define CMOS_READ(addr) ({ \ + outb((addr),RTC_PORT(0)); \ + inb(RTC_PORT(1)); \ + }) + +#define CMOS_WRITE(val, addr) ({ \ + outb((addr),RTC_PORT(0)); \ + outb((val),RTC_PORT(1)); \ + }) + +static void write_bit(unsigned char val) { + + unsigned char byte = CMOS_READ(440 / 8); + + /* Don't change it if its already set */ + + if ((byte & 1) == (val & 1)) + return; + + byte &= ~1; + byte |= val & 1; + CMOS_WRITE(val, 440/8); +} + +static unsigned short _getsmbusbase(void) { + unsigned devfn = PCI_DEVFN(0xf, 0); + device_t dev = dev_find_slot(0x0, devfn); + unsigned long addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + + return (unsigned short) (addr & ~1); +} + +static void init_dcon(void) { + + int ret = 1; + unsigned short rev = 0; + unsigned short iobase = _getsmbusbase(); + + printk_debug("CHECKING FOR DCON (%x)\n", iobase); + + /* Get the IO base for the SMBUS */ + + rev = do_smbus_read_word(iobase, 0x0D << 1, 0x00); + + if (rev & 0xDC00) { + printk_debug("DCON FOUND - REV %x\n", rev); + + /* Enable the DCON */ + ret = do_smbus_write_word(iobase, 0x0D << 1, 0x01, 0x0069); + if (ret != 0) + printk_debug("DCON ENABLE FAILED\n", ret); + } + else + printk_debug("DCON NOT FOUND (%x)\n", rev); + + write_bit(rev > 0 ? 1 : 0); +} + +static void init(struct device *dev) { +/* + unsigned bus = 0; + unsigned devfn = PCI_DEVFN(0xf, 4); + device_t usb = NULL; + unsigned char usbirq = 0xa; +*/ + + printk_debug("OLPC BTEST ENTER %s\n", __FUNCTION__); + +#if 0 + /* I can't think of any reason NOT to just set this. If it turns out we want this to be + * conditional we can make it a config variable later. + */ + + printk_debug("%s (%x,%x)SET USB PCI interrupt line to %d\n", + __FUNCTION__, bus, devfn, usbirq); + usb = dev_find_slot(bus, devfn); + if (! usb){ + printk_err("Could not find USB\n"); + } else { + pci_write_config8(usb, PCI_INTERRUPT_LINE, usbirq); + } +#endif + + init_dcon(); + printk_debug("OLPC BTEST EXIT %s\n", __FUNCTION__); +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + +struct chip_operations mainboard_olpc_btest_ops = { + CHIP_NAME("olpc btest mainboard ") + .enable_dev = enable_dev, + +}; Added: trunk/LinuxBIOSv2/src/mainboard/olpc/btest/reset.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/olpc/btest/reset.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/olpc/btest/reset.c 2006-10-18 15:23:28 UTC (rev 2459) @@ -0,0 +1,43 @@ +#if 0 +//#include "arch/romcc_io.h" +#include <arch/io.h> + +typedef unsigned device_t; + +#define PCI_DEV(BUS, DEV, FN) ( \ + (((BUS) & 0xFF) << 16) | \ + (((DEV) & 0x1f) << 11) | \ + (((FN) & 0x7) << 8)) + +static void pci_write_config8(device_t dev, unsigned where, unsigned char value) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outb(value, 0xCFC + (addr & 3)); +} + +static void pci_write_config32(device_t dev, unsigned where, unsigned value) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); +} + +static unsigned pci_read_config32(device_t dev, unsigned where) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); +} + +#include "../../../northbridge/amd/amdk8/reset_test.c" + +void hard_reset(void) +{ + set_bios_reset(); + pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1); +} +#endif

1 0

Re: [LinuxBIOS] Tyan s2892 the OLPC way
by Lu, Yinghai 17 Oct '06

17 Oct '06

It didn't find the partitions. Try to enable partition in your kernel config. YH -----Original Message----- From: Myles Watson [mailto:myles@mouselemur.cs.byu.edu] Sent: Friday, October 13, 2006 1:29 PM To: Lu, Yinghai; linuxbios(a)linuxbios.org Subject: RE: [LinuxBIOS] Tyan s2892 the OLPC way > > Boot log? Attached. Sorry it took so long. I needed to change the console to the serial port. Myles > > > I think the error is something different. I can mount my USB key > that I > > > formatted ext2, but when I try /dev/hda1 instead of /dev/sda1, it > says > > > Unknown error 6, which is "no such device or address". > > > > > > > Forgive if you have done this already Just trying to cover all the > > simple fixes first. Have you verified that you really have IDE > > devices enabled in your kernel? > > No problem, I appreciate the help > > I have > CONFIG_IDE > CONFIG_BLK_DEV_IDE > CONFIG_IDE_GENERIC > > All enabled. I couldn't find any others that made sense to me. > > Myles > >

5 5

Re: [LinuxBIOS] sunw ultra40
by Lu, Yinghai 17 Oct '06

17 Oct '06

Just worked it out, it doesn't support my rom emulator. Need some time to finialize the interrupt...and reduce FAN speed., will do it tomorrow... YH -----Original Message----- From: Ronald G Minnich [mailto:rminnich@lanl.gov] Sent: Monday, October 16, 2006 7:15 PM To: Lu, Yinghai Cc: LinuxBIOS Subject: Re: [LinuxBIOS] sunw ultra40 Lu, Yinghai wrote: > Yes. You need to stop the watchdog asap, otherwise it will shutdown the > system. according to an expert, there is no active watchdog on this ultra40. thanks ron

1 0

Re: [LinuxBIOS] Tyan s2892 the OLPC way
by Myles Watson 17 Oct '06

17 Oct '06

> You can also try to reduce ROM_IMAGE_SIZE to get some space for your > payload. > > FALLBACK_SIZE-ROM_IMAGE_SIZE will be your payload size. I don't think that'll give me enough space. I'll try it, though. My 64-bit kernel payload is 874K right now. I was hoping that there was a way that I could make LinuxBIOS think there was a full fallback image, but just have the code to jump to the normal image included. > >Another question is about kexec. I have booted into the 64-bit kernel > >using FILO & Etherboot, but then when I try to kexec the kernel, it > resets > the machine saying > > > >#INIT detected from --- {APICID == 00 NODEID == 00 COREID == 00} --- > > Do you have kexec enabled in your kernel Config? I didn't test if I can > kexec 64 bit kernel from 32 bit kernel.. Eric, is that supported? > I can kexec a 64-bit kernel from a 32-bit kernel. I haven't been successful with kexec from a 64-bit kernel to another 64-bit kernel. It may be because the stripped down version of kexec that I'm using from olpc is too stripped-down. Myles

2 1

[LinuxBIOS] r2458 - trunk/LinuxBIOSv2/util/optionlist
by svn＠openbios.org 17 Oct '06

17 Oct '06

Author: stepan Date: 2006-10-17 22:58:47 +0200 (Tue, 17 Oct 2006) New Revision: 2458 Added: trunk/LinuxBIOSv2/util/optionlist/Options-wiki.xsl Modified: trunk/LinuxBIOSv2/util/optionlist/Makefile Log: add xsl stylesheet for wiki table generation Modified: trunk/LinuxBIOSv2/util/optionlist/Makefile =================================================================== --- trunk/LinuxBIOSv2/util/optionlist/Makefile 2006-10-14 21:35:30 UTC (rev 2457) +++ trunk/LinuxBIOSv2/util/optionlist/Makefile 2006-10-17 20:58:47 UTC (rev 2458) @@ -1,7 +1,13 @@ -all: +all: html wiki + +html: ./mkOptionList.py @#saxon Options.xml Options.xsl >Options.html xsltproc Options.xsl Options.xml > Options.html +wiki: + ./mkOptionList.py + xsltproc Options-wiki.xsl Options.xml > Options.wiki + clean: - rm Options.xml Options.html + rm -rf Options.xml Options.html Options.wiki Added: trunk/LinuxBIOSv2/util/optionlist/Options-wiki.xsl =================================================================== --- trunk/LinuxBIOSv2/util/optionlist/Options-wiki.xsl (rev 0) +++ trunk/LinuxBIOSv2/util/optionlist/Options-wiki.xsl 2006-10-17 20:58:47 UTC (rev 2458) @@ -0,0 +1,32 @@ +<?xml version="1.0"?> +<xsl:stylesheet version="1.0" xmlns:xsl="http://www.w3.org/1999/XSL/Transform"> + +<xsl:output method="text" + encoding="utf-8" + indent="yes" /> + +<xsl:template match="/"> +==LinuxBIOS Options== + +This is an automatically generated list of LinuxBIOS compile time +options. Created at <xsl:value-of select="//creationdate"/>. + +{| border="1" +|- bgcolor="#0975a7" +! align="left" | Option +! align="left" | Comment +! align="left" | Default +! align="left" | Export +! align="left" | Format<xsl:for-each select="options/option"> +|- +| <xsl:value-of select="@name"/> +| <xsl:value-of select="comment"/> +| <xsl:value-of select="default"/> +| <xsl:value-of select="export"/> +| <xsl:value-of select="format"/> +</xsl:for-each> +|} + + +</xsl:template> +</xsl:stylesheet>

1 0

Re: [LinuxBIOS] sunw ultra40
by Lu, Yinghai 17 Oct '06

17 Oct '06

Yes. You need to stop the watchdog asap, otherwise it will shutdown the system. YH -----Original Message----- From: Ronald G Minnich [mailto:rminnich@lanl.gov] Sent: Friday, October 13, 2006 2:12 PM To: Lu, Yinghai Cc: LinuxBIOS Subject: Re: [LinuxBIOS] sunw ultra40 Lu, Yinghai wrote: > That is for extra GPIO manuipulation on SuperIO to enable FAN or disable > watchdog. So you need open one window on SB, But ultra 40 donesn't need > it. ah! so sio_setup is SuperIO setup, not Serial Setup, right? But still, then, why this call top the enable serial with GPIO params? Is this to enable the device and setup the I/O base for it? Ah, I get it. ron

5 5

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coreboot October 2006