coreboot October 2006

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208 discussions

[LinuxBIOS] ACPI NVS and last 64k-ish area of RAM?
by Alan Mimms 04 Oct '06

04 Oct '06

We have AMD dual Opteron hardware with AMD 8131+8111 chipsets attached. Using LinuxBIOS, we have a slight problem, that APPEARS to be related to the last 64Kbytes of RAM. Our kboot based environment, running in 32 bit instruction set, seems to randomly crash, and the implicated area of memory is this last 64KB. When we run a commercial BIOS on nearly identical hardware, we see that that BIOS has created in the E820 table an ACPI Non-Volatile-Storage area covering this last 64KB. LinuxBIOS is NOT doing that; LinuxBIOS is treating all of the space as simple USABLE space. In trying to figure this out, we have used the AMD HDT tool to read the last 64KB. We (SOMETIMES) the system crashes when we read this area using HDT. Can someone please explain what this area is for and why it's strange to read even using a hardware debugging tool? Is it REALLY in use for the ACPI NVS, and can we simply tell Linux to ignore it (map it out) by creating an entry in E820 table so it won't be used (we don't use ACPI suspend/resume)? Thanks very much for any information. Alan Mimms, Senior Architect F5 Networks, Inc. Spokane Development Center 1322 North Whitman Lane Liberty Lake, Washington 99019 v: 509-343-3524 f: 509-343-3501

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[LinuxBIOS] via/epia/
by Tyler Pohl 04 Oct '06

04 Oct '06

At first after flashing the eeprom i soft rebooted my output was: My monitor flashed colors Serial Output: ÔXaÓinuxBIOS-2.0.0.0Fallback Tue Oct 3 19:11:16 PDT 2006 starting... 87 is the comm register SMBus controller enabled vt8601 init starting 00000000 is the north 1106 0601 0120d4 is the computed timing NOP PRECHARGE DUMMY READS CBR MRS NORMAL set ref. rate enable multi-page open Slot 00 is SDRAM 08000000 bytes x2 0080 is the chip size 0008 is the MA type Slot 01 is SDRAM 04000000 bytes x2 0040 is the chip size 0008 is the MA type Slot 02 is empty Slot 03 is empty vt8601 done Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-2.0.0.0Fallback Tue Oct 3 19:11:16 PDT 2006 booting... Enumerating buses... scan_static_bus for Root Device Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 0 set_pci_ops: seeking driver for 1106:601 class 60000 PCI: 00:00.0 [1106/0601] ops PCI: 00:00.0 [1106/0601] enabled malloc Enter, size 668, free_mem_ptr 00018000 malloc 0x00018000 set_pci_ops: seeking driver for 1106:8601 class 60400 Capability: 0x07 @ 0x80 Capability: 0x08 @ 0x80 Capability: 0x10 @ 0x80 PCI: 00:01.0 [1106/8601] enabled PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff set_pci_ops: seeking driver for 1106:8231 class 60100 PCI: 00:11.0 [1106/8231] bus ops PCI: 00:11.0 [1106/8231] enabled set_pci_ops: seeking driver for 1106:571 class 1018a PCI: 00:11.1 [1106/0571] ops PCI: 00:11.1 [1106/0571] enabled set_pci_ops: seeking driver for 1106:3038 class c0300 PCI: 00:11.2 [1106/3038] disabled set_pci_ops: seeking driver for 1106:3038 class c0300 PCI: 00:11.3 [1106/3038] disabled set_pci_ops: seeking driver for 1106:8235 class 68000 PCI: 00:11.4 [1106/8235] ops PCI: 00:11.4 [1106/8235] disabled set_pci_ops: seeking driver for 1106:3058 class 40100 PCI: 00:11.5 [1106/3058] disabled set_pci_ops: seeking driver for 1106:3068 class 78000 PCI: 00:11.6 [1106/3068] enabled PCI: devfn 0x8f, bad id 0xffffffff set_pci_ops: seeking driver for 1106:3065 class 20000 PCI: 00:12.0 [1106/3065] ops PCI: 00:12.0 [1106/3065] enabled PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 1 malloc Enter, size 668, free_mem_ptr 0001829c malloc 0x0001829c set_pci_ops: seeking driver for 1023:8500 class 30000 PCI: 01:00.0 [1023/8500] enabled PCI: devfn 0x8, bad id 0xffffffff PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: devfn 0x88, bad id 0xffffffff PCI: devfn 0x90, bad id 0xffffffff PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=01 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:11.0 PNP: 002e.0 enabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 disabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b enabled scan_static_bus for PCI: 00:11.0 done PCI: pci_scan_bus returning with max=01 scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 0 LinuxBIOS-2.0.0.0Fallback Tue Oct 3 19:11:16 PDT 2006 starting... 87 is the comm register SMBus controller enabled vt8601 init starting 00000000 is the north 1106 0601 0120d4 is the computed timing NOP PRECHARGE DUMMY READS CBR MRS NORMAL set ref. rate enable multi-page open Slot 00 is SDRAM 08000000 bytes x2 0080 is the chip size 0008 is the MA type Slot 01 is SDRAM 04000000 bytes x2 0040 is the chip size 0008 is the MA type Slot 02 is empty Slot 03 is empty vt8601 done Copying LinuxBIOS to ram. Jumping to LinuxBIOS. ____________________________________________- Then I powered down the via board and my output was: No video at all serial output: LinuxBIOS-2.0.0.0Normal Tue Oct 3 19:10:30 PDT 2006 starting... 87 is the comm register SMBus controller enabled vt8601 init starting 00000000 is the north 1106 0601 0120d4 is the computed timing NOP PRECHARGE DUMMY READS CBR MRS NORMAL set ref. rate enable multi-page open Slot 00 is SDRAM 08000000 bytes x2 0080 is the chip size 0008 is the MA type Slot 01 is SDRAM 04000000 bytes x2 0040 is the chip size 0008 is the MA type Slot 02 is empty Slot 03 is empty vt8601 done Copying LinuxBIOS to ram. Jumping to LinuxBIOS. Any sugestions? How do you enable the RAM test function? In mainboard/via/epia/auto.c ........... I did the following tring to enable the RAM test but when i do a make i get an error Unblocked the following beacuse i don't know how the conditional assembly works in this case. ram_check(0x00000000, msr.lo); static const struct { unsigned long lo, hi; } check_addrs[] = { /* Check 16MB of memory @ 0*/ { 0x00000000, 0x01000000 }, My make error: /home/tyler/LinuxBIOSv2/src/mainboard/via/epia/auto.c -o auto.inc auto.c:113.34: msr undeclared make[1]: *** [auto.inc] Error 1 make[1]: Leaving directory `/home/tyler/LinuxBIOSv2/targets/via/epia/epia/normal' make: *** [normal/linuxbios.rom] Error 1 Where or what should msr be decalred as ? Thanks Again.

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[LinuxBIOS] FW: rev F support code
by Devils-Hawk 04 Oct '06

04 Oct '06

I am no expert myself but as far as i know, the license is all about copyright. So because you( more spec. AMD ) is the copyright holder and copyright law grants certain rights ( e.g. prohibiting copying, modifying, etc ) only you can add the GPL notice, which does in fact only state that you forever revoke some of the rights granted to you by copyright law. If somebody else does add the notice you, the copyright holder, still has the right to sue for copyright infringement whenever it is convenient, because you did not grant the right to modify the code in the first place. The problem is, even if you state per mail that you have no problem with somebody else adding the GPL notice, such an written agreement is not enforecable in court in most of the countries on this planet. And another problem is that the "All rights Reserved" clause is as far as i know not compatible with the GPL, because you cannot reserve all rights at the same time you willingly give away some of them. For more detailed information you should probably go to groklaw.net or ask your in house lawyers. http://www.gnu.org/licenses/gpl-faq.html is a pretty good source of information too. Kind regards, DevH > To my personal understanding, copyright is copyright, license is > license. > > Every code in LinuxBIOS is under GPL. > > YH

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[LinuxBIOS] request for programmers manual maintainer
by Ward Vandewege 03 Oct '06

03 Oct '06

Greetings from the LinuxBIOS symposium in Hamburg! We're on our second day, and things have been going very well. We've been having some very interesting sessions, and even started doing some (late-night) hacking. We got an OLPC demo - booting openfirmware and linux kernel payloads! The folks from AMD gave an interesting talk about AMD's linuxBIOS roadmap. We've talked about payloads, and about how to rework the configuration system. Lots of interesting stuff. The slides from the talks should be online soon - hopefully in a couple or days or so. Some pictures are already linked to from here: http://linuxbios.org/index.php/LinuxBIOS_Symposium_2006_Photos We'll post more links there as we upload more photos. Now; this morning we had a discussion about the creation of a Programmer's manual. The idea is to create much more documentation for people who want to start hacking on LinuxBIOS. People who contribute code would ideally also write documentation about that code - but there might be other contributors too, of course. The consensus of the discussion was that we need a coordinator for the Programmer's manual. Ideally someone who is *not* yet very familiar with the codebase, or even with low-level programming. Such a person would basically oversee the creation of the manual, encouraging (pestering?) coders to also contribute documentation, etc. It would be a great way to dive into LinuxBIOS programming - the coordinator is pretty much guaranteed to learn a lot as this manual takes shape. The question is - anyone here who would be interested in taking on this role? Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

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Re: [LinuxBIOS] FW: rev F support code
by Lu, Yinghai 03 Oct '06

03 Oct '06

Yes. Use cpu/amd/socket_AM2 instead of cpu/amd/socket_F in your MB Config. YH -----Original Message----- From: linuxbios-bounces(a)linuxbios.org [mailto:linuxbios-bounces@linuxbios.org] On Behalf Of Ed Swierk Sent: Monday, October 02, 2006 2:53 PM To: linuxbios(a)linuxbios.org Subject: Re: [LinuxBIOS] FW: rev F support code Does "rev F" include the AM2-socket Athlon 64 X2? I take it Serengeti refers to some internal AMD mainboard? Thanks, --Ed -- linuxbios mailing list linuxbios(a)linuxbios.org http://www.openbios.org/mailman/listinfo/linuxbios

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[LinuxBIOS] FW: rev F support code
by Lu, Yinghai 02 Oct '06

02 Oct '06

If you have problem with it, please let me know. Thanks Yinghai Lu

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[LinuxBIOS] flashrom SST49LF080A patch
by Roman Kononov 02 Oct '06

02 Oct '06

Hello, Second post. The first one has not reached the mailing list for some reason. The first patch changes chip erase method from JEDEC Chip Erase to JEDEC Sector Erase for each sector. See the comment in util/flashrom/sst49lf040.c, line #40. Verified on a real SST49LF080A chip, for which JEDEC Chip Erase did not work as well. The second patch makes printf working [as designed ?]. Roman Index: util/flashrom/flashchips.c =================================================================== --- util/flashrom/flashchips.c (revision 2434) +++ util/flashrom/flashchips.c (working copy) @@ -67,7 +67,7 @@ {"SST49LF040", SST_ID, SST_49LF040, NULL, 512, 4096, probe_jedec, erase_49lf040, write_49lf040,NULL}, {"SST49LF080A", SST_ID, SST_49LF080A, NULL, 1024, 4096, - probe_jedec, erase_chip_jedec, write_49lf040,NULL}, + probe_jedec, erase_49lf040, write_49lf040,NULL}, {"SST49LF002A/B", SST_ID, SST_49LF002A, NULL, 256, 16 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub, NULL}, {"SST49LF003A/B", SST_ID, SST_49LF003A, NULL, 384, 64 * 1024, Index: util/flashrom/sst49lf040.c =================================================================== --- util/flashrom/sst49lf040.c (revision 2434) +++ util/flashrom/sst49lf040.c (working copy) @@ -59,13 +59,11 @@ erase_sector_jedec(bios, i * page_size); /* write to the sector */ - if((i&0xfff)==0xfff) - printf("%04d at address: 0x%08x ", i, i * page_size); + printf("%04d at address: 0x%08x ", i, i * page_size); write_sector_jedec(bios, buf + i * page_size, bios + i * page_size, page_size); - if((i&0xfff)==0xfff) - printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); + printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); fflush(stdout); } printf("\n");

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[LinuxBIOS] LinuxBIOS on ASUS P2B-L
by Don Waugaman 02 Oct '06

02 Oct '06

Hi all, I'm working on putting LinuxBIOS on an old ASUS P2B-L that I'd like to convert into an "instant-on" server for home use. It has an Intel 440BX Host Bridge with Intel PIIX4e hard disk controller, and a Winbond W83977TF SuperIO chip. I downloaded the manuals for these various chips, so I think I might have a shot at getting them working correctly as long as I can get some debug output on the serial port. Since this will be a server, I don't need any video support, though I'd like to keep the card in the machine uninitialized for when I have to boot the factory BIOS. I've configured grub and the kernel to use the serial port as the console, which works OK. My plan is to use FILO as the LinuxBIOS payload. I've installed a BIOS Savior in the machine and flashed it with another copy of the factory BIOS, which works OK, so (barring checks in the utility's code) I should be able to use the ASUS AFLASH program rather than flashrom. First, I tried to build a FILO payload with serial console only and USE_GRUB=1, which didn't work - it looked like it was still trying to use the VGA console for some functions. It worked OK when I commented out the USE_GRUB line, but I'd still like to try the former configuration - any FILO experts have any tips on how to squash the VGA functions once and for all? Then I grabbed the SVN trees for both v1 and v2. I copied the bitworks/ims mainboard and target directories, as they seemed to be using the 440bx code, and I'm slogging through changing the various bitworks & ims entries in the code to asus & p2bl entries. So far, so good, though I feel somewhat like I'm in a maze of twisty little passages, all alike. My main question is: The W83977TF has support under v1, but not v2 - any tips on porting from one to the other? Also, once I have the superIO initialization code installed, is there some way to get some kind of debug output before RAM initialization? I'm not sure where to put my own debugging output into the code - just a "hello, I'm here" is all I need for starters. I'd be happy for pointers to some docs which might answer some of these questions - I perused some of what I could find in the SVN tree and wiki, but ended up just trying to jump right in instead. Another big question would be - should I continue ahead with v2, or go back to v1? I noticed that v1 had the 440bx support as well, but it looked like v2's configuration setup was a lot easier to deal with, so I started there. Would it be worth it to learn how v1 does things for this project? The other outstanding issue coming down the pike is that the machine has all ECC RAM. Is ECC supported by v1 or v2, and if not by either, which would make it easiest to add support? I'm assuming v2, but I'll try v1 if that would be easier. Many thanks, Don

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coreboot October 2006