December 2005 - coreboot - mail.coreboot.org

Re: [LinuxBIOS] Compiling errors for flashrom
by Richard Smith Dec. 15, 2005

Dec. 15, 2005

On 12/15/05, Christian Sühs <chris(a)suehsi.de> wrote: > BTW: GCC 2.96 compiles the flashrom tool without any warnings and > errors. At time it seems the tool works correct. It recognized the right > chipset and the right EEProm Chip. What flash part (EEProm) is on that board ? > But unfortunatly gcc 2.96 fails to compile the LinuxBios Image :D > However, if I recieve my chip I will try to flash LB with the 2.96 > compiled flashtool and the gcc 3.3 compiled image ;) and see what happens. What SVN rev are you using? I thought Stefan reciently fixed up all the compile and alignment issues to work with newer compilers. Its ok if flashrom and the linuxbios image are compiled with different compilers. -- Richard A. Smith

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Re: [LinuxBIOS] Compiling errors for flashrom
by Richard Smith Dec. 14, 2005

Dec. 14, 2005

> > > > Do you have a linuxbios table in your image? > > Oh, is their any what I understand wrong? > I thougt flashrom is a binary to flash rom images into EEProms. > It is but it looks for a linuxbios table to see what mfg and mainboard that image was built for. > I have called it without any parameters and it should spoke out > something about my board and my bios, like the output in the documentation. Hmm.. Dunno. You will have to look at the source to figure out why that fails. > However, I will try to get work LinuxBios on my VIA Epia ML. > Therefor I have done any step in the Epia HOWTO. I think their is a > linuxbios table in my image. But before I try the image, I will wait for > my second EEProm :D I think those howto's are pretty old. They should probally be more of a guide rather than a reciepe. -- Richard A. Smith

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Re: [LinuxBIOS] tyan s2881
by Lu, Yinghai Dec. 13, 2005

Dec. 13, 2005

Ron, Are you using flash_rom or flashrom? Stepan put sth in flashrom to check the LinuxBIOS image size=262144 MANUFACTURER: Tyan MAINBOARD ID: s2881 YH -----Original Message----- From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of Ward Vandewege Sent: Monday, December 12, 2005 6:05 PM To: Ronald G Minnich Cc: LinuxBIOS Subject: Re: [LinuxBIOS] tyan s2881 On Mon, Dec 12, 2005 at 05:25:48PM -0700, Ronald G Minnich wrote: > we use the v2 flashrom all the time on s2881 here. > > Also, Ward led me to believe he was getting serial output. Did I miss > something? Ah, sorry about the confusion, I get serial output when NOT running linuxbios. That was just me making sure that was set up correctly. I haven't yet managed to boot linuxbios. I'm obviously doing something stupid building the image - my images are not even being recognized by flashrom as being Linuxbios images. Yhlu sent me an image to test, but I can't burn that as it is being seen as not the correct size by flashrom. Real size: 524288 bytes flashrom: root@chimera:~/LinuxBIOSv2/util/flashrom# ./flashrom -v -w ../../../s2881_linuxbios.rom Calibrating delay loop... ok No LinuxBIOS table found. Enabling flash write on AMD8111...OK Pm49FL004 found at physical address: 0xfff80000 Flash part is Pm49FL004 LinuxBIOS image size=262144 MANUFACTURER: Tyan MAINBOARD ID: s2881 ERROR: This firmware image does not fit to this machine Override with -m ifyou know exactly what you are doing. Not sure what's going on here. Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator -- LinuxBIOS mailing list LinuxBIOS(a)openbios.org http://www.openbios.org/mailman/listinfo/linuxbios

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[LinuxBIOS] EPoX 8KTA3 Mainboard
by Keven L. Ates Dec. 13, 2005

Dec. 13, 2005

Hello All, Can anyone give me some feedback on using LinuxBIOS on the following: EPoX 8KTA3 Mainboard AMD Athlon 1GHz Socket A "lspci" output follows AGP Video Card - ATI Radeon PLCC with Award BIOS v6.0 (flashed updates with awdflash.exe) Some MBs may also have an optional RAID chip. http://www.epox.com/USA/product.asp?ID=EP-8KTA3 As it uses VIA chip I'm hoping for the best. I'm currently using SuSE Linux 9.3 (2.6 Kernel) and Windows 2000 booting from GRUB on the MBR of boot partition and would like LinuxBIOS to call the MBR (so LinuxBIOS only needs to do the minimum). NOTE: It seems to me that much of the configuration of a system can be derived from a linux installation directly such that the LinuxBIOS make can "read" a system its compiling on and set itself up. Particularly, it could "lspci", read the active BIOS or a supplied BIOS file for the video, etc. with very little user intervention and create an appropriate LinuxBIOS for the machine. Yeah, I know, what if you need to compile on one machine and feed to another? But, how about a "what if you don't" option? Could it be made to do it automagically? linux:~ # lspci -vvv 0000:00:00.0 Host bridge: VIA Technologies, Inc. VT8363/8365 [KT133/KM133] (rev 03) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR+ Latency: 8 Region 0: Memory at d8000000 (32-bit, prefetchable) Capabilities: [a0] AGP version 2.0 Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW+ AGP3- Rate=x1,x2,x4 Command: RQ=1 ArqSz=0 Cal=0 SBA+ AGP+ GART64- 64bit- FW- Rate=x4 Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:01.0 PCI bridge: VIA Technologies, Inc. VT8363/8365 [KT133/KM133 AGP] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000a000-0000afff Memory behind bridge: dc000000-ddffffff Prefetchable memory behind bridge: d0000000-d7ffffff Expansion ROM at 0000a000 [disabled] [size=4K] BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.0 ISA bridge: VIA Technologies, Inc. VT82C686 [Apollo Super South] (rev 40) Subsystem: VIA Technologies, Inc. VT82C686/A PCI to ISA Bridge Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE (rev 06) (prog-if 8a [Master SecP PriP]) Subsystem: VIA Technologies, Inc. VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 Region 4: I/O ports at b000 [size=16] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.2 USB Controller: VIA Technologies, Inc. USB (rev 16) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. (Wrong ID) USB Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32, cache line size 08 Interrupt: pin D routed to IRQ 10 Region 4: I/O ports at b400 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.3 USB Controller: VIA Technologies, Inc. USB (rev 16) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. (Wrong ID) USB Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32, cache line size 08 Interrupt: pin D routed to IRQ 10 Region 4: I/O ports at b800 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.4 Bridge: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] (rev 40) Subsystem: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin ? routed to IRQ 9 Capabilities: [68] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.5 Multimedia audio controller: VIA Technologies, Inc. VT82C686 AC97 Audio Controller (rev 50) Subsystem: VIA Technologies, Inc. Onboard Audio on EP7KXA Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin C routed to IRQ 5 Region 0: I/O ports at bc00 Region 1: I/O ports at c000 [size=4] Region 2: I/O ports at c400 [size=4] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:08.0 Multimedia audio controller: Creative Labs SB Live! EMU10k1 (rev 08) Subsystem: Creative Labs CT4760 SBLive! Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (500ns min, 5000ns max) Interrupt: pin A routed to IRQ 3 Region 0: I/O ports at c800 Capabilities: [dc] Power Management version 1 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:08.1 Input device controller: Creative Labs SB Live! MIDI/Game Port (rev 08) Subsystem: Creative Labs Gameport Joystick Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 Region 0: I/O ports at cc00 Capabilities: [dc] Power Management version 1 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:09.0 Unknown mass storage controller: Promise Technology, Inc. 20262 (rev 01) Subsystem: Promise Technology, Inc. Ultra66 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at d000 Region 1: I/O ports at d400 [size=4] Region 2: I/O ports at d800 [size=8] Region 3: I/O ports at dc00 [size=4] Region 4: I/O ports at e000 [size=64] Region 5: Memory at df000000 (32-bit, non-prefetchable) [size=128K] 0000:00:0a.0 Ethernet controller: National Semiconductor Corporation DP83815 (MacPhyter) Ethernet Controller Subsystem: Netgear FA311 / FA312 (FA311 with WoL HW) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (2750ns min, 13000ns max) Interrupt: pin A routed to IRQ 5 Region 0: I/O ports at e400 Region 1: Memory at df020000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=320mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME+ 0000:00:0b.0 Ethernet controller: National Semiconductor Corporation DP83815 (MacPhyter) Ethernet Controller Subsystem: Netgear FA311 / FA312 (FA311 with WoL HW) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (2750ns min, 13000ns max) Interrupt: pin A routed to IRQ 10 Region 0: I/O ports at e800 Region 1: Memory at df021000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=320mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:01:00.0 VGA compatible controller: ATI Technologies Inc Radeon R100 QD [Radeon 7200] (prog-if 00 [VGA]) Subsystem: ATI Technologies Inc Radeon AIW Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (2000ns min), cache line size 08 Interrupt: pin A routed to IRQ 3 Region 0: Memory at d0000000 (32-bit, prefetchable) Region 1: I/O ports at a000 [size=256] Region 2: Memory at dd000000 (32-bit, non-prefetchable) [size=512K] Capabilities: [58] AGP version 2.0 Status: RQ=48 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2,x4 Command: RQ=32 ArqSz=0 Cal=0 SBA+ AGP+ GART64- 64bit- FW- Rate=x4 Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME-

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[LinuxBIOS] tyan s2881
by Ward Vandewege Dec. 12, 2005

Dec. 12, 2005

Hi there, First of all, thanks for upgrading the SVN tree, it now compiles without problems (but still lots of warnings ;) for the Tyan s2881. I've managed to build a Linuxbios image, using FILO 0.5 and the latest subversion revision of the Linuxbios tree (2141). So I've compiled filo, built the rom image, and burned the rom into our biossavior. This is the filo configuration file I used: USE_GRUB = 1 MENULST_FILE = "sda1:/grub/menu.lst" AUTOBOOT_FILE = "sda1:/vmlinuz-2.6.12-9-amd64-generic root=/dev/sda4 console=tty0 console=ttyS0,19200n8" AUTOBOOT_DELAY = 4 IDE_DISK = 1 VGA_CONSOLE = 1 PC_KEYBOARD = 1 SERIAL_CONSOLE = 1 SERIAL_IOBASE = 0x3f8 SERIAL_SPEED = 19200 FSYS_EXT2FS = 1 FSYS_FAT = 1 FSYS_REISERFS = 1 FSYS_ISO9660 = 1 ELTORITO = 1 SUPPORT_PCI = 1 PCI_BRUTE_SCAN = 1 LINUX_LOADER = 1 PCI_CONFIG_1 = 1 I'm unsure about the references to sda in the MENULST_FILE and AUTOBOOT_FILE parameters. This is how my running kernel sees the SATA drives; Linuxbios supports booting from SATA, right? The Config.lb I'm using is: target s2881 mainboard tyan/s2881 # Tyan s2881 romimage "normal" option ROM_SIZE = 475136 option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" payload ../../../../../payloads/filo.elf end romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ../../../../../payloads/filo.elf end That's pretty much the stock version from the SVN tree. I used the flashrom tool to burn & verify the image. That works perfectly. Unfortunately, when trying to boot it, nothing happens. Nothing on the screen (but I didn't expect that as I'm still not clear about the whole vga bios thing). I've hooked up another linux box for capturing the serial output, and verified that that setup works (serial login to s2881 works, running the proprietary bios). When booting linuxbios, there is no output on the serial line. This MB has POST leds onboard; when booting from poweroff, they remain stuck at FF when using the linuxbios image. When booting the proprietary image, they cycle through a whole range of numbers, to finish on 00 once the system is up. I have a feeling I'm missing something important. Any pointers? Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

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Re: [LinuxBIOS] etherboot + linuxbios
by Lu, Yinghai Dec. 12, 2005

Dec. 12, 2005

It works well... YH -----Original Message----- From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of Jonathan McDowell Sent: Monday, December 12, 2005 2:37 PM To: Jason Schildt Cc: linuxbios(a)openbios.org Subject: Re: [LinuxBIOS] etherboot + linuxbios On Mon, Dec 12, 2005 at 03:30:33PM -0700, Jason Schildt wrote: > On Mon, Dec 12, 2005 at 10:17:29PM +0000, Jonathan McDowell wrote: > > What versions of etherboot are people using with LinuxBIOS? I've had > > problems with 5.4.1 just giving gibberish on the serial console so have > > ended up using 5.2.6; is this expected? > If you're getting gibberish over serial, then your baud rate is set > wrong. More than likely, LB is set to 115200 and Etherboot is set to > 9600. Or visa versa. I'm pretty sure I tried both with -DDCOMPRESERVE (which I understand should make etherboot use the LB settings) and -DCONSPEED=115200 (which is what lb is set to). If you (or anyone else) can confirm you're using 5.4.1 without problems with LB on a serial console then I'll go back and try again, but really I just wanted to know I wasn't spending time debugging something that was known not to work. J. -- /-\ | noodles is almost a national |@/ Debian GNU/Linux Developer | pastime in japan \- | -- LinuxBIOS mailing list LinuxBIOS(a)openbios.org http://www.openbios.org/mailman/listinfo/linuxbios

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Re: [LinuxBIOS] etherboot + linuxbios
by Jonathan McDowell Dec. 12, 2005

Dec. 12, 2005

On Mon, Dec 12, 2005 at 03:30:33PM -0700, Jason Schildt wrote: > On Mon, Dec 12, 2005 at 10:17:29PM +0000, Jonathan McDowell wrote: > > What versions of etherboot are people using with LinuxBIOS? I've had > > problems with 5.4.1 just giving gibberish on the serial console so have > > ended up using 5.2.6; is this expected? > If you're getting gibberish over serial, then your baud rate is set > wrong. More than likely, LB is set to 115200 and Etherboot is set to > 9600. Or visa versa. I'm pretty sure I tried both with -DDCOMPRESERVE (which I understand should make etherboot use the LB settings) and -DCONSPEED=115200 (which is what lb is set to). If you (or anyone else) can confirm you're using 5.4.1 without problems with LB on a serial console then I'll go back and try again, but really I just wanted to know I wasn't spending time debugging something that was known not to work. J. -- /-\ | noodles is almost a national |@/ Debian GNU/Linux Developer | pastime in japan \- |

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Re: [LinuxBIOS] etherboot + linuxbios
by Lu, Yinghai Dec. 12, 2005

Dec. 12, 2005

5.4.1 should be OK.... let me check it.... Gcc 3? YH -----Original Message----- From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of Jonathan McDowell Sent: Monday, December 12, 2005 2:17 PM To: linuxbios(a)openbios.org Subject: [LinuxBIOS] etherboot + linuxbios What versions of etherboot are people using with LinuxBIOS? I've had problems with 5.4.1 just giving gibberish on the serial console so have ended up using 5.2.6; is this expected? J. -- Web [ Trust me, you wouldn't like us when we're angry. ] site: http:// [ ] Made by www.earth.li/~noodles/ [ ] HuggieTag 0.0.23 -- LinuxBIOS mailing list LinuxBIOS(a)openbios.org http://www.openbios.org/mailman/listinfo/linuxbios

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[LinuxBIOS] etherboot + linuxbios
by Jonathan McDowell Dec. 12, 2005

Dec. 12, 2005

What versions of etherboot are people using with LinuxBIOS? I've had problems with 5.4.1 just giving gibberish on the serial console so have ended up using 5.2.6; is this expected? J. -- Web [ Trust me, you wouldn't like us when we're angry. ] site: http:// [ ] Made by www.earth.li/~noodles/ [ ] HuggieTag 0.0.23

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Re: [LinuxBIOS] Fwd: [issue50] put pgtbl after 1M
by Lu, Yinghai Dec. 12, 2005

Dec. 12, 2005

I worked out method 3 too... Please let me know if you want method 3 only or together with method 1. the detail about method 3: copy _secondary_start from 1M above to 1M below and mask the start_eip to 20bit only. It will make _RAMBASE > 0x100000 can work with SMP... BTW, why there are linuxbios(a)openbios.org and linubios(a)linuxbios.org? YH -----Original Message----- From: Lu, Yinghai Sent: Thursday, December 08, 2005 12:19 PM To: Lu, Yinghai; yhlu; Eric W. Biederman; LinuxBIOS Subject: RE: [LinuxBIOS] Fwd: [issue50] put pgtbl after 1M For 128 cpu system, will use method one and only keep stack for bsp in linuxbios_ram statck section. Other stack will be after pgtbl.... Anyway the Method is the best way if we can work it out, and that could make code more simple... YH -----Original Message----- From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of Lu, Yinghai Sent: Wednesday, December 07, 2005 4:52 PM To: yhlu; Eric W. Biederman; LinuxBIOS Subject: Re: [LinuxBIOS] Fwd: [issue50] put pgtbl after 1M Regarding the problem there are three way to solve. 1. move the pgtbl after 1M. this should work for a while.... the future 32 node abd quad core = 128 cpu, will have stack 128*8=1M, It will cross the 0xa000 again... 2. in linuxbios_ram.ld, force bss, stack and heap all after 1M, the total ram section will be larger then 1M (about 1.5M), (linuxbios_ram.bin still about 64K), it works well except the back and forth in two linuebios ram image in jmp_to_elf_entry will clear the 0xf0000-0x100000, the irq table ( and acpi region ) region 3. the best solution seems to set _RAMBASE=0x10400, so it will not clear our irq table and acpi tables...., the only thing to do is some 16 bit code in secondary.S need to move to rom....other wise the ap can not be started.... YH -----Original Message----- From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of yhlu Sent: Wednesday, December 07, 2005 12:47 AM To: Eric W. Biederman; LinuxBIOS Subject: [LinuxBIOS] Fwd: [issue50] put pgtbl after 1M Eric, I moved the pgtbl to the last 1M of CONFIG_LB_MEM_TOPK.... Please check it. YH ---------- Forwarded message ---------- From: Yinghai Lu <lxbios(a)openbios.org> Date: Dec 7, 2005 12:43 AM Subject: [issue50] put pgtbl after 1M To: ollie(a)lanl.gov, rminnich(a)lanl.gov, stepan(a)openbios.org, yinghailu(a)gmail.com New submission from Yinghai Lu <yinghailu(a)gmail.com>: This one is needed for 8 way dual core with VGA support enabled. The reason is every cpu page table will be 20k, and if there is 16 cpu will need 320k, it will push the stack and heap cross the 0xa0000, the region for vga font buffer. TO use that need to set CONFIG_LB_MEM_TOPK in MB Options.lb It also remove the hardcode 1M in clear_1m_ram.c to use CONFIG_LB_MEM_TOPK. YH ---------- files: 1207_put_pgtbl_after_1m.diff messages: 299 nosy: ollie, rminnich, stepan, yhlu priority: urgent status: chatting title: put pgtbl after 1M ________________________________________________ LinuxBIOS issue tracker <lxbios(a)openbios.org> <https://openbios.org/roundup/linuxbios/issue50> ________________________________________________ -- LinuxBIOS mailing list LinuxBIOS(a)openbios.org http://www.openbios.org/mailman/listinfo/linuxbios

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