coreboot August 2004

coreboot@coreboot.org

39 participants
76 discussions

RE: Nvidia CK804 and Tyan S2895 support
by YhLu 15 Sep '04

15 Sep '04

Still wait for Nvidia releasing the chipset. Some one said it will be released this Oct. Also I hope more guys can push Nvidia to let us to release the code for that. Nvidia doesn't make the final decision if they will support LinuxBIOS. Regards YH -----Original Message----- From: Ken Fuchs [mailto:kfuchs@winternet.com] Sent: Monday, August 30, 2004 8:47 PM To: linuxbios(a)clustermatic.org Subject: Re: Nvidia CK804 and Tyan S2895 support YhLu wrote: >Just FYI. >I just finished the LinuxBIOS support to S2895 (it has two CK804 >onboard). >Connection is > CPU1<----->CPU0<---->8131 > | | > | | > CK804 CK804 That was really, really fast work! Where can one access the LinuxBIOS source code for the Tyan S2895 mainboard (dual CK8-04 chips)? ------ I asked about CK8-04 chip support a rather short time ago in this thread: http://www.clustermatic.org/pipermail/linuxbios/2004-June/008326.html Thanks again Ron and David for your responses and especially YhLu for this very encouraging response: http://www.clustermatic.org/pipermail/linuxbios/2004-June/008328.html Again, I must say that was very quick work for such a new chip! Sincerely, Ken Fuchs <kfuchs(a)winternet.com> _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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EPIA-M build problem for freebios2
by Dan Sully 07 Sep '04

07 Sep '04

So first of all, it's not clear from any of the outdated documentation whether one should be using freebios or freebios2. So, I'm jumping in and trying to use 2 - but getting this error: ar cr linuxbios.a malloc.o apic_timer.o pci_ops.o vt8235.o chip.o memset.o fallback_boot.o keyboard.o cpuid.o pnp_device.o printk.o irq_tables.o pgtbl.o tables.o pci_device.o console.o cpufixup.o elfboot.o hardwaremain.o boot.o linuxbios_table.o delay.o version.o memcmp.o isa-dma.o hypertransport.o vtxprintf.o root_device.o mtrr.o uart8250.o device_util.o ./option_table.o compute_ip_checksum.o device.o memcpy.o northbridge.o clog2.o pirq_routing.o memmove.o mc146818rtc.o rom_stream.o c_start.o vsprintf.o cpu.o static.o gcc -nostdlib -r -o linuxbios_c.o c_start.o mainboard.o uart8250_console.o linuxbios.a /usr/lib/gcc-lib/i486-linux/3.3.4/libgcc.a gcc -nostdlib -nostartfiles -static -o linuxbios_c -T /home/dsully/src/freebios2/src/config/linuxbios_c.ld linuxbios_c.o linuxbios_c.o(.data+0x1e4): undefined reference to `mainboard_via_epia_m_control' collect2: ld returned 1 exit status make: *** [linuxbios_c] Error 1 targets/via/epia-m/epia-m/normal/static.c which includes: src/mainboard/via/epia-m/chip.h where mainboard_via_epia_m_control is set as extern. Any thoughts? Thanks. -D -- <weezyl> Oh, I cook bacon naked all the time. You just have to keep the heat on med-low.

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Mail Delivery (failure linuxbios@clustermatic.org)
by aip＠cwlinux.com 31 Aug '04

31 Aug '04

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RE: using the cosole device
by YhLu 31 Aug '04

31 Aug '04

You mean baud rate or others. The freebios2 has two Config.lb, one in the mainboard and the other in targets Freebios2/src/mainboard/ Freebios2/targets/. The chipset seeting is in mainboard, and others in targes. Regards YH _____ From: Sagiv Yefet [mailto:sagivy@3vium.com] Sent: Tuesday, August 31, 2004 3:56 AM To: linuxbios(a)clustermatic.org Subject: using the cosole device I am working on AMD64. What are the definition in the Config.lb file define the console device (rs232) Superio winbond/w83627hf Thanks.

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VGA Problem about 440bx chipset
by Chiu Gerald 31 Aug '04

31 Aug '04

HI,all I run linuxbios on a 440bx chipset mainboard using adlo+bochs,I can boot linux but still havn't started up the vga. what should I do if I want to bring up the vga card? I found the work done about vga are: (1) allocate_vga_resource() in newpci.c enbale io/mem of the vga adapter then walk up the bridges setting the VGA enable (2) copy the vga bios to 0xc0000 using adlo,and run bochs bios. I'm not sure if it had initilized the vga controller enough. And I found there are some registers about AGP from 440bx northbridge datasheet ( 82443bx hostbridge/controller),such as AGP capability identifier register,AGP command register,AGP status register... But this work hadn't been done in linuxbios,maybe I need to set these registers correctly according to the datasheet to enable AGP? Regards, Gerald _________________________________________________________________ 免费下载 MSN Explorer: http://explorer.msn.com/lccn

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unsupport int error when vga init
by zhu shi song 31 Aug '04

31 Aug '04

Dear lists, I have two questions: (1) I use getpir(8.30 freebios v1) to get irq_tables.c of epia-500. I have compared mine with one under mainboard/via/epia. They are always different. What cause it? My irq_tables.c is as following: /* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS s ets up Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM */ #include <arch/pirq_routing.h> const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32+16*5, /* there can be total 5 devices on the bus */ 0, /* Where the interrupt router lies (bus) */ 0, /* Where the interrupt router lies (dev) */ 0x1c00, /* IRQs devoted exclusively to PCI usage */ 0, /* Vendor */ 0, /* Device */ 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x88, /* u8 checksum , this hase to set to some value that woul d give 0 after the sum of all bytes for this structure (including checksum) */ { {0,0x98, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xd eb8}}, 0x2, 0}, {0,0x50, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xd eb8}}, 0x3, 0}, {0,0x58, {{0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xd eb8}}, 0x4, 0}, {0,0x8, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xde b8}}, 0, 0}, {0x50,0, {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, } }; (2) I've got QDIA6T MB based on vt8601 and vt82c686. I have made some progress on this MB(8.30 freebios v1). The romimage can find VGABIOS, but unsupport int error occurred. The output log is as following: LinuxBIOS-1.0.0 Tue Aug 31 19:52:18 CST 2004 starting... Enabled first bank of RAM: 0x10000000 bytes Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.0.0 Tue Aug 31 19:52:18 CST 2004 booting... Finding PCI configuration type. PCI: Using configuration type 1 Scanning PCI bus...PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [1106/0601] PCI: 00:01.0 [1106/8601] PCI: 00:07.0 [1106/0686] PCI: 00:07.2 [1106/3038] PCI: 00:07.3 [1106/3038] PCI: 00:07.4 [1106/3057] PCI: 00:07.5 [1106/3058] PCI: pci_scan_bus for bus 1 PCI: 01:00.0 [1023/8500] PCI: pci_scan_bus returning with max=01 PCI: pci_scan_bus returning with max=01 done Allocating PCI resources... PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it ASSIGN RESOURCES, bus 0 PCI: 00:01.0 1c <- [0x00001000 - 0x00000fff] bus 1 io PCI: 00:01.0 24 <- [0xfe900000 - 0xfe8fffff] bus 1 prefmem PCI: 00:01.0 20 <- [0xfd800000 - 0xfe8fffff] bus 1 mem ASSIGN RESOURCES, bus 1 PCI: 01:00.0 10 <- [0xfd800000 - 0xfdffffff] mem PCI: 01:00.0 14 <- [0xfe800000 - 0xfe81ffff] mem PCI: 01:00.0 18 <- [0xfe000000 - 0xfe7fffff] mem ASSIGNED RESOURCES, bus 1 PCI: 00:07.2 20 <- [0x00001400 - 0x0000141f] io PCI: 00:07.3 20 <- [0x00001420 - 0x0000143f] io PCI: 00:07.5 10 <- [0x00001000 - 0x000010ff] io PCI: 00:07.5 14 <- [0x00001440 - 0x00001443] io PCI: 00:07.5 18 <- [0x00001450 - 0x00001453] io ASSIGNED RESOURCES, bus 0 Allocating VGA resource done. Enabling PCI resourcess...PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 cmd <- 07 PCI: 00:07.0 cmd <- 87 PCI: 00:07.2 cmd <- 01 PCI: 00:07.3 cmd <- 01 PCI: 00:07.4 cmd <- 00 PCI: 00:07.5 cmd <- 01 PCI: 01:00.0 cmd <- 03 done. Initializing PCI devices... PCI devices initialized Disable Cache Bank0 256MB (MA type 0xe) bank 2 MA 0x0: 0 bytes bank 2 MA 0x8: 0 bytes bank 2 MA 0xe: 0 bytes bank 4 MA 0x0: 0 bytes bank 4 MA 0x8: 0 bytes bank 4 MA 0xe: 0 bytes Enable Cache Total 248MB + frame buffer 8MB Enabling shadow DRAM at 0xC0000-0xFFFFF: done totalram: 248M Initializing CPU #0 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) type: WB Setting fixed MTRRs(24-88) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 128MB, type WB Setting variable MTRR 1, base: 128MB, range: 64MB, type WB Setting variable MTRR 2, base: 192MB, range: 32MB, type WB Setting variable MTRR 3, base: 224MB, range: 16MB, type WB Setting variable MTRR 4, base: 240MB, range: 8MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs done. Max cpuid index : 2 Vendor ID : GenuineIntel Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x08 Processor Mask : 0x00 Processor Stepping : 0x0a Feature flags : 0x0383fbff Cache/TLB descriptor values: 1 reads required Desc 0x01 : Instr TLB: 4KB pages, 4-way set assoc, 32 entries Desc 0x02 : Instr TLB: 4MB pages, fully assoc, 2 entries Desc 0x03 : Data TLB: 4KB pages, 4-way set assoc, 64 entries Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x41 : L2 Unified cache: 128K bytes, 4-way set assoc, 32 byte line size Desc 0x08 : Inst cache: 16K bytes, 4-way set assoc, 32 byte line size Desc 0x04 : Data TLB: 4MB pages, 4-way set assoc, 8 entries Desc 0x0c : Data cache: 16K bytes, 2-way or 4-way set assoc, 32 byte line size MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 Initialized Mainboard fixup IDE enable in reg. 48 is 0x3 set IDE reg. 48 to 0x1 IRQs in reg. 4a are 0x4 setting reg. 4a to 0x44 IDE enable in reg.1-40 is 0x8 set IDE reg.1-40 to 0x3 IDE enable in reg.1-40 read back is 0x3 enables in reg 0x9 0x8f enables in reg 0x9 read back as 0x8a command in reg 0x4 0x80 command in reg 0x4 reads back as 0x85 keyboard_on Final mainboard fixup Southbridge fixup keyboard_on IDE enable in reg. 48 is 0x5 set IDE reg. 48 to 0x5 IRQs in reg. 4a are 0x4 setting reg. 4a to 0x44 IDE enable in reg.1-40 is 0x3 set IDE reg.1-40 to 0x3 IDE enable in reg.1-40 read back is 0x3 enables in reg 0x9 0x8a enables in reg 0x9 read back as 0x8a command in reg 0x4 0x85 command in reg 0x4 reads back as 0x85 setting southbridge Assigning IRQ 10 to 0:7.5 Readback = 10 Assigning IRQ 11 to 1:0.0 Readback = 11 INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1023, did=8500 0x55 0xaa 0x60 0xeb 0x4d 0x37 0x34 0x30 0x30 0x30 0x37 0xdc 0x73 0x2a 0x2a 0x52 bus/devfn = 0x100 biosint: # 0x1a, eax 0xb109 ebx 0x100 ecx 0x100 edx 0xb1bf biosint: ebp 0x10fd8 esp 0xfc9 edi 0x2 esi 0x13f60 biosint: ip 0x56e8 cs 0xc000 flags 0x16 0xb109: bus 1 devfn 0x0 reg 0x2 val 0x8500 biosint: # 0xd8, eax 0xc000 ebx 0x100 ecx 0x8500 edx 0x3c2 biosint: ebp 0x10fd8 esp 0xfc7 edi 0x2 esi 0x13f60 biosint: ip 0x2329 cs 0xc000 flags 0x246 biosint: Unsupport int #0xd8 biosint: # 0xcd, eax 0xc000 ebx 0x100 ecx 0x8500 edx 0x3c2 biosint: ebp 0x10fd8 esp 0xfc7 edi 0x2 esi 0x13f60 biosint: ip 0x2329 cs 0xc000 flags 0x246 biosint: Unsupport int #0xcd __________________________________ Do you Yahoo!? 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using the cosole device
by Sagiv Yefet 31 Aug '04

31 Aug '04

I am working on AMD64. What are the definition in the Config.lb file define the console device (rs232) Superio winbond/w83627hf Thanks.

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RE: ROMCC problem
by YhLu 30 Aug '04

30 Aug '04

Thanks, It works. Regards YH -----Original Message----- From: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] Sent: Monday, August 30, 2004 9:45 PM To: YhLu Cc: ron minnich; linuxbios Subject: Re: ROMCC problem YhLu <YhLu(a)tyan.com> writes: > Eric, > the current romcc seems have problem to process "asm". Or bist cause the > problem? The optimizer took a look at the asm realized no one used the output of it. And optimized the instruction away. Correct but annoying. Just mark the asm as volatile and the code will work fine. Eric

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ROMCC problem
by YhLu 30 Aug '04

30 Aug '04

Eric, the current romcc seems have problem to process "asm". Or bist cause the problem? Regards YH In Failover.E normal_image: asm("jmp __normal_image" : : "a" (bist) : ); cpu_reset: asm("jmp __cpu_reset" : : "a"(bist) : ); fallback_image: will produce Lfailover1063: /* main,failover.c:68.11 */ Lfailover1064: /* ,:0.0 */ /* unknown %eax */ /* unknown %ebx */ /* unknown %ecx */ /* unknown %edx */ #ASM #NOT ASM Old romcc result it right Lfailover61: /* main,failover.c:21.28 */ /* main,failover.c:67.18 */ mov $0 , %eax #ASM jmp __normal_image #NOT ASM /* main,failover.c:68.11 */ Lfailover62: /* main,failover.c:21.28 */ /* main,failover.c:73.18 */ mov $0 , %eax #ASM jmp __cpu_reset #NOT ASM /* main,failover.c:74.16 */ Lfailover63: /* ,failover.c:82.1 */ Lfailover64: /* max inline depth 6 */

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Re: Nvidia CK804 and Tyan S2895 support
by Ken Fuchs 30 Aug '04

30 Aug '04

YhLu wrote: >Just FYI. >I just finished the LinuxBIOS support to S2895 (it has two CK804 >onboard). >Connection is > CPU1<----->CPU0<---->8131 > | | > | | > CK804 CK804 That was really, really fast work! Where can one access the LinuxBIOS source code for the Tyan S2895 mainboard (dual CK8-04 chips)? ------ I asked about CK8-04 chip support a rather short time ago in this thread: http://www.clustermatic.org/pipermail/linuxbios/2004-June/008326.html Thanks again Ron and David for your responses and especially YhLu for this very encouraging response: http://www.clustermatic.org/pipermail/linuxbios/2004-June/008328.html Again, I must say that was very quick work for such a new chip! Sincerely, Ken Fuchs <kfuchs(a)winternet.com>

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coreboot August 2004