July 2004 - coreboot - mail.coreboot.org

RE: sis630et memory init problem
by Nick Jarmany July 25, 2004

July 25, 2004

Zhu, On SiS630ET x8Eh has two active bits:- Bit 0: SDRAM synchronous mode. 0=Enable, 1=Disable Bit 1:Relationship between CPU & SDRAM clocks. 0=CPU>SDRAM, 1=CPU<SDRAM Default value of this register at POR=00h Regards, Nick -----Original Message----- From: linuxbios-admin(a)clustermatic.org [mailto:linuxbios-admin@clustermatic.org]On Behalf Of zhu shi song Sent: 25 July 2004 11:10 To: linuxbios(a)clustermatic.org Subject: sis630et memory init problem Hi, lists, I've got one ECS p6stmt motherboard based on sis630et. I have dumped pci host bridge settings: P6STMT 00:00.0 Host bridge: Silicon Integrated Systems: Unknown device 0630 (rev 30) 00: 39 10 30 06 07 00 10 22 30 00 00 06 00 20 80 00 10: 00 00 00 d8 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 9e 00 c5 00 00 19 00 01 00 15 51 00 00 00 00 00 60: 0b 00 00 a1 00 00 00 00 01 50 c6 00 e0 00 00 00 70: 3f 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 20 ff 7f 1f 60 00 03 40 00 08 00 00 78 88 00 55 90: 00 00 00 00 40 00 00 01 00 00 00 00 02 00 00 00 a0: 00 00 03 01 aa 00 00 00 00 00 00 00 00 00 f8 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 02 00 20 00 07 02 00 1f 04 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 SPD dump: Memory Type 0x04 Number of Row Address bits 0x0d Number of Column Address bits 0x0a Number of Sides 0x01 Number of Banks 0x04 I try to set the values just as the same as bios settings. But when ipl use stack, it hangs on copying linuxbios from DOC. It's obvious that memory init failed. I noticed that 0x8e is 0, It's very different with winfast6300's. winfast6300 0x8e is 03. What's the problem behind it? tks zhu _____ Do you Yahoo!? Yahoo! Mail is new and improved - Check <http://us.rd.yahoo.com/mail_us/taglines/new/*http://promotions.yahoo.com/ne…> it out!

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[NEWBIE question] LinuxBIOS & IEEE 1394
by Vincent BARBARIN July 25, 2004

July 25, 2004

Hi, here's a new one there, tired of those "Boot from ".... options that are not so available on those PCs... I'd like to know if there's any project going on to put in LinuxBIOS Int 13 support for IEEE 1394 drives (why not USB too ? motherboard integrated or not) Any link with linux1394.org ? Just for making any OS boot loader running from any drive... pleeeeeeeeeese ?

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Re: Was a newbie, now a polliwog
by Richard Smith July 25, 2004

July 25, 2004

Thomas Fritz wrote: > There's a PDF file on the tiny-linux site, which has a descriptions of > results - with a 2.6 kernel with more features than I'd need, the writer > says that he got it as small as a compressed 363K image, and a user > reported a compressed image as small as 191K. Thats very encouraging. I wonder what was enabled in the 191Kib version. 191+64 is just enough for those people with 256Kib flashes. > This is all very interesting, but while I have 512K to work in right > now, I have no idea how much space linuxbios needs. Also, keep in mind > I'm going to be trying to cross-compile for the PowerPC...does the same > code need more bytes or fewer bytes? In my current LB1 setup that does not netboot: LB = 60Kib ADLO = 136Kib By the time they run through the script the whole thing ends up being 228Kib but I have my settings so that the smallest alignment is like 64k or so. I don't remember exactly so I've got wasted space. I have no idea how the PPC code compares to x86. I've cc: this to the list perhaps some PPC person can comment. I think V2 is much larger due to the use of romcc but I don't have any hard info on that as I haven't made the jump yet.

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Is LinuxBIOS still alive?
by Marc Nicholas July 25, 2004

July 25, 2004

Hello... I used to be on the LinuxBIOS list a few years back...the website seems a little dry on information these days -- is LB still alive and kicking? I'm specifically interested in getting things working with VIA Mini-ITX boards, namely the M and MII. -marc

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sis630et memory init problem
by zhu shi song July 24, 2004

July 24, 2004

Hi, lists, I've got one ECS p6stmt motherboard based on sis630et. I have dumped pci host bridge settings: P6STMT 00:00.0 Host bridge: Silicon Integrated Systems: Unknown device 0630 (rev 30) 00: 39 10 30 06 07 00 10 22 30 00 00 06 00 20 80 00 10: 00 00 00 d8 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 9e 00 c5 00 00 19 00 01 00 15 51 00 00 00 00 00 60: 0b 00 00 a1 00 00 00 00 01 50 c6 00 e0 00 00 00 70: 3f 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 20 ff 7f 1f 60 00 03 40 00 08 00 00 78 88 00 55 90: 00 00 00 00 40 00 00 01 00 00 00 00 02 00 00 00 a0: 00 00 03 01 aa 00 00 00 00 00 00 00 00 00 f8 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 02 00 20 00 07 02 00 1f 04 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 SPD dump: Memory Type 0x04 Number of Row Address bits 0x0d Number of Column Address bits 0x0a Number of Sides 0x01 Number of Banks 0x04 I try to set the values just as the same as bios settings. But when ipl use stack, it hangs on copying linuxbios from DOC. It's obvious that memory init failed. I noticed that 0x8e is 0, It's very different with winfast6300's. winfast6300 0x8e is 03. What's the problem behind it? tks zhu --------------------------------- Do you Yahoo!? Yahoo! Mail is new and improved - Check it out!

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Does LinuxBIOS V2 support AGP (vedio card) for via/epia board
by Simon Xin Cheng July 23, 2004

July 23, 2004

I successfully boot Linux kernel 2.6.7 by LinuxBIOS V2 + filo. However, I have to disable AGP support in the kernel because I got some errors when Kernel initialized agpgart. I checked the source code. It seems that AGP is not supported for via/epia board either in V1 or in V2. Am I right? How can I obtain AGP support? I need Xwindow. Thanks. Simon Cheng www.msica.com

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AMD 8111 GPIO
by Jay Miller July 23, 2004

July 23, 2004

We've got Linux up and running on our Tyan S2885 motherboards, using etherboot and filo with USB support. Thanks for all your help, and patience! I was hoping that with all the expertise here with AMD 8111 chipset, that someone would be able to answer my question. Although it's not strictly LinuxBIOS, it is Linux. ;-) So I'm trying to write a Linux driver for the GPIO pins on the AMD 8111. I saw a comment in amd8111_smbus.c that PMIOEN is set. I believe this is part of what I need to be able to drive the GPIOs. But how/where were all those hex values determined? The spec uses mnemonics to abstract the addresses, and I don't see how they correlate. Thanks, Jay Miller 781-229-7812x117 Actuality Systems, Inc. jmiller(a)acutality-systems.com

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Re: Sis 630 memory init
by Richard Smith July 23, 2004

July 23, 2004

zhu shi song wrote: > Do you know what errors of original code have been corrected after using the new code? My suggestion would be to dump the northbridge of a BIOS that works correctly and compare it to what LinuxBios does. The go consult the data sheet on each difference.

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Re: Sis 630 memory init
by Richard Smith July 23, 2004

July 23, 2004

zhu shi song wrote: > Where is work placed? Can you kindly send me for reference? > Look in northbridge/intel/440bx/raminit.inc > I have checked the value of (sdram type, row, col, bank ,side ) through post code(output to 0x80 port). They are all correct values. But I still can't use SDRAM on ECS P6STMT board. > Do you know what errors of original code have been corrected after using the new code? > tks If I remember correctly the page size and the ram boundrys were not being set correctly. The orginal RAM routines tried to set all the registers in one big loop so it was really hard to debug. I switced to the newer code since it did things one step at a time and would be easier to debug. Switching had the side-effect of making things work so I didn't bother totaly figureing out what was wrong with the orginal code.

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Starting point for a SuperIO port (SMC LPC47B272)
by Chris Love July 22, 2004

July 22, 2004

I am trying to bring up LinuxBIOS on an x86 CPCI blade here. Output from lspci is included below. The one item I've noticed so far is that the SuperIO device doesn't appear to be supported in either source tree. The northbridge, southbridge, and BIOS flash device (82802AC) appear to be supported in the freebios tree. Has anyone dealt with this SuperIO device before? Are any of the other SMC superio drivers a good or bad starting point for a port? My first step is probably going to be comparing datasheets between this and some of the other devices, but other suggestions would be welcome. Thanks in advance, Chris 00:00.0 Host bridge: Intel Corp.: Unknown device 254c (rev 01) 00:02.0 PCI bridge: Intel Corp. e7500 [Plumas] HI_B Virtual PCI Bridge (F0) (rev 01) 00:1d.0 USB Controller: Intel Corp. 82801CA/CAM USB (Hub #1) (rev 02) 00:1e.0 PCI bridge: Intel Corp. 82801BA/CA/DB PCI Bridge (rev 42) 00:1f.0 ISA bridge: Intel Corp. 82801CA ISA Bridge (LPC) (rev 02) 00:1f.1 IDE interface: Intel Corp. 82801CA IDE U100 (rev 02) 00:1f.3 SMBus: Intel Corp. 82801CA/CAM SMBus (rev 02) 01:01.0 SCSI storage controller: LSI Logic / Symbios Logic 53c896 (rev 07) 01:01.1 SCSI storage controller: LSI Logic / Symbios Logic 53c896 (rev 07) 01:02.0 Ethernet controller: Intel Corp. 82559ER (rev 09) 01:03.0 Ethernet controller: Intel Corp. 82559ER (rev 09) 01:05.0 Serial controller: Exar Corp.: Unknown device 0154 (rev 03) 01:08.0 Ethernet controller: Intel Corp. 82801CAM (ICH3) PRO/100 VE (LOM) Ethernet Controller (rev 42) 02:1c.0 PIC: Intel Corp. 82870P2 P64H2 I/OxAPIC (rev 04) 02:1d.0 PCI bridge: Intel Corp. 82870P2 P64H2 Hub PCI Bridge (rev 04) 02:1e.0 PIC: Intel Corp. 82870P2 P64H2 I/OxAPIC (rev 04) 02:1f.0 PCI bridge: Intel Corp. 82870P2 P64H2 Hub PCI Bridge (rev 04) 03:01.0 PCI bridge: Intel Corp. 21154 PCI-to-PCI Bridge 03:02.0 VGA compatible controller: Silicon Motion, Inc. SM710 LynxEM (rev a3) 05:01.0 Ethernet controller: Intel Corp. 82546EB Gigabit Ethernet Controller (Copper) (rev 01) 05:01.1 Ethernet controller: Intel Corp. 82546EB Gigabit Ethernet Controller (Copper) (rev 01) -- Chris Love // Continuous Computing Corporation love(a)ccpu.com // http://www.ccpu.com

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